1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
26 simplefb_lcd: framebuffer-lcd {
27 compatible = "allwinner,simple-framebuffer",
29 allwinner,pipeline = "mixer0-lcd0";
30 clocks = <&ccu CLK_TCON0>,
31 <&display_clocks CLK_MIXER0>;
35 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "allwinner,simple-framebuffer",
38 allwinner,pipeline = "mixer1-lcd1-hdmi";
39 clocks = <&display_clocks CLK_MIXER1>,
40 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
50 compatible = "arm,cortex-a53";
53 enable-method = "psci";
54 next-level-cache = <&L2>;
55 clocks = <&ccu CLK_CPUX>;
61 compatible = "arm,cortex-a53";
64 enable-method = "psci";
65 next-level-cache = <&L2>;
66 clocks = <&ccu CLK_CPUX>;
72 compatible = "arm,cortex-a53";
75 enable-method = "psci";
76 next-level-cache = <&L2>;
77 clocks = <&ccu CLK_CPUX>;
83 compatible = "arm,cortex-a53";
86 enable-method = "psci";
87 next-level-cache = <&L2>;
88 clocks = <&ccu CLK_CPUX>;
101 compatible = "allwinner,sun50i-a64-display-engine";
102 allwinner,pipelines = <&mixer0>,
107 gpu_opp_table: opp-table-gpu {
108 compatible = "operating-points-v2";
111 opp-hz = /bits/ 64 <120000000>;
115 opp-hz = /bits/ 64 <312000000>;
119 opp-hz = /bits/ 64 <432000000>;
125 compatible = "fixed-clock";
126 clock-frequency = <24000000>;
127 clock-output-names = "osc24M";
132 compatible = "fixed-clock";
133 clock-frequency = <32768>;
134 clock-output-names = "ext-osc32k";
138 compatible = "arm,cortex-a53-pmu";
139 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
143 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
147 compatible = "arm,psci-0.2";
152 #address-cells = <1>;
154 compatible = "simple-audio-card";
155 simple-audio-card,name = "sun50i-a64-audio";
156 simple-audio-card,aux-devs = <&codec_analog>;
157 simple-audio-card,routing =
164 simple-audio-card,dai-link@0 {
166 frame-master = <&link0_cpu>;
167 bitclock-master = <&link0_cpu>;
175 sound-dai = <&codec 0>;
181 compatible = "arm,armv8-timer";
182 allwinner,erratum-unknown1;
183 arm,no-tick-in-suspend;
184 interrupts = <GIC_PPI 13
185 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
187 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
189 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
191 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
195 cpu_thermal: cpu0-thermal {
197 polling-delay-passive = <0>;
199 thermal-sensors = <&ths 0>;
203 trip = <&cpu_alert0>;
204 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
205 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
206 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210 trip = <&cpu_alert1>;
211 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
212 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
213 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
214 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
219 cpu_alert0: cpu_alert0 {
221 temperature = <75000>;
226 cpu_alert1: cpu_alert1 {
228 temperature = <90000>;
235 temperature = <110000>;
242 gpu0_thermal: gpu0-thermal {
244 polling-delay-passive = <0>;
246 thermal-sensors = <&ths 1>;
249 gpu1_thermal: gpu1-thermal {
251 polling-delay-passive = <0>;
253 thermal-sensors = <&ths 2>;
258 compatible = "simple-bus";
259 #address-cells = <1>;
264 compatible = "allwinner,sun50i-a64-de2";
265 reg = <0x1000000 0x400000>;
266 allwinner,sram = <&de2_sram 1>;
267 #address-cells = <1>;
269 ranges = <0 0x1000000 0x400000>;
271 display_clocks: clock@0 {
272 compatible = "allwinner,sun50i-a64-de2-clk";
274 clocks = <&ccu CLK_BUS_DE>,
278 resets = <&ccu RST_BUS_DE>;
283 rotate: rotate@20000 {
284 compatible = "allwinner,sun50i-a64-de2-rotate",
285 "allwinner,sun8i-a83t-de2-rotate";
286 reg = <0x20000 0x10000>;
287 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&display_clocks CLK_BUS_ROT>,
289 <&display_clocks CLK_ROT>;
292 resets = <&display_clocks RST_ROT>;
295 mixer0: mixer@100000 {
296 compatible = "allwinner,sun50i-a64-de2-mixer-0";
297 reg = <0x100000 0x100000>;
298 clocks = <&display_clocks CLK_BUS_MIXER0>,
299 <&display_clocks CLK_MIXER0>;
302 resets = <&display_clocks RST_MIXER0>;
305 #address-cells = <1>;
309 #address-cells = <1>;
313 mixer0_out_tcon0: endpoint@0 {
315 remote-endpoint = <&tcon0_in_mixer0>;
318 mixer0_out_tcon1: endpoint@1 {
320 remote-endpoint = <&tcon1_in_mixer0>;
326 mixer1: mixer@200000 {
327 compatible = "allwinner,sun50i-a64-de2-mixer-1";
328 reg = <0x200000 0x100000>;
329 clocks = <&display_clocks CLK_BUS_MIXER1>,
330 <&display_clocks CLK_MIXER1>;
333 resets = <&display_clocks RST_MIXER1>;
336 #address-cells = <1>;
340 #address-cells = <1>;
344 mixer1_out_tcon0: endpoint@0 {
346 remote-endpoint = <&tcon0_in_mixer1>;
349 mixer1_out_tcon1: endpoint@1 {
351 remote-endpoint = <&tcon1_in_mixer1>;
358 syscon: syscon@1c00000 {
359 compatible = "allwinner,sun50i-a64-system-control";
360 reg = <0x01c00000 0x1000>;
361 #address-cells = <1>;
366 compatible = "mmio-sram";
367 reg = <0x00018000 0x28000>;
368 #address-cells = <1>;
370 ranges = <0 0x00018000 0x28000>;
372 de2_sram: sram-section@0 {
373 compatible = "allwinner,sun50i-a64-sram-c";
374 reg = <0x0000 0x28000>;
378 sram_c1: sram@1d00000 {
379 compatible = "mmio-sram";
380 reg = <0x01d00000 0x40000>;
381 #address-cells = <1>;
383 ranges = <0 0x01d00000 0x40000>;
385 ve_sram: sram-section@0 {
386 compatible = "allwinner,sun50i-a64-sram-c1",
387 "allwinner,sun4i-a10-sram-c1";
388 reg = <0x000000 0x40000>;
393 dma: dma-controller@1c02000 {
394 compatible = "allwinner,sun50i-a64-dma";
395 reg = <0x01c02000 0x1000>;
396 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&ccu CLK_BUS_DMA>;
400 resets = <&ccu RST_BUS_DMA>;
404 tcon0: lcd-controller@1c0c000 {
405 compatible = "allwinner,sun50i-a64-tcon-lcd",
406 "allwinner,sun8i-a83t-tcon-lcd";
407 reg = <0x01c0c000 0x1000>;
408 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
410 clock-names = "ahb", "tcon-ch0";
411 clock-output-names = "tcon-data-clock";
413 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
414 reset-names = "lcd", "lvds";
417 #address-cells = <1>;
421 #address-cells = <1>;
425 tcon0_in_mixer0: endpoint@0 {
427 remote-endpoint = <&mixer0_out_tcon0>;
430 tcon0_in_mixer1: endpoint@1 {
432 remote-endpoint = <&mixer1_out_tcon0>;
437 #address-cells = <1>;
441 tcon0_out_dsi: endpoint@1 {
443 remote-endpoint = <&dsi_in_tcon0>;
444 allwinner,tcon-channel = <1>;
450 tcon1: lcd-controller@1c0d000 {
451 compatible = "allwinner,sun50i-a64-tcon-tv",
452 "allwinner,sun8i-a83t-tcon-tv";
453 reg = <0x01c0d000 0x1000>;
454 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
456 clock-names = "ahb", "tcon-ch1";
457 resets = <&ccu RST_BUS_TCON1>;
461 #address-cells = <1>;
465 #address-cells = <1>;
469 tcon1_in_mixer0: endpoint@0 {
471 remote-endpoint = <&mixer0_out_tcon1>;
474 tcon1_in_mixer1: endpoint@1 {
476 remote-endpoint = <&mixer1_out_tcon1>;
481 #address-cells = <1>;
485 tcon1_out_hdmi: endpoint@1 {
487 remote-endpoint = <&hdmi_in_tcon1>;
493 video-codec@1c0e000 {
494 compatible = "allwinner,sun50i-a64-video-engine";
495 reg = <0x01c0e000 0x1000>;
496 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
498 clock-names = "ahb", "mod", "ram";
499 resets = <&ccu RST_BUS_VE>;
500 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
501 allwinner,sram = <&ve_sram 1>;
505 compatible = "allwinner,sun50i-a64-mmc";
506 reg = <0x01c0f000 0x1000>;
507 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
508 clock-names = "ahb", "mmc";
509 resets = <&ccu RST_BUS_MMC0>;
511 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
512 max-frequency = <150000000>;
514 #address-cells = <1>;
519 compatible = "allwinner,sun50i-a64-mmc";
520 reg = <0x01c10000 0x1000>;
521 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
522 clock-names = "ahb", "mmc";
523 resets = <&ccu RST_BUS_MMC1>;
525 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
526 max-frequency = <150000000>;
528 #address-cells = <1>;
533 compatible = "allwinner,sun50i-a64-emmc";
534 reg = <0x01c11000 0x1000>;
535 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
536 clock-names = "ahb", "mmc";
537 resets = <&ccu RST_BUS_MMC2>;
539 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
540 max-frequency = <150000000>;
542 #address-cells = <1>;
546 sid: eeprom@1c14000 {
547 compatible = "allwinner,sun50i-a64-sid";
548 reg = <0x1c14000 0x400>;
549 #address-cells = <1>;
552 ths_calibration: thermal-sensor-calibration@34 {
557 crypto: crypto@1c15000 {
558 compatible = "allwinner,sun50i-a64-crypto";
559 reg = <0x01c15000 0x1000>;
560 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
562 clock-names = "bus", "mod";
563 resets = <&ccu RST_BUS_CE>;
566 msgbox: mailbox@1c17000 {
567 compatible = "allwinner,sun50i-a64-msgbox",
568 "allwinner,sun6i-a31-msgbox";
569 reg = <0x01c17000 0x1000>;
570 clocks = <&ccu CLK_BUS_MSGBOX>;
571 resets = <&ccu RST_BUS_MSGBOX>;
572 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
576 usb_otg: usb@1c19000 {
577 compatible = "allwinner,sun8i-a33-musb";
578 reg = <0x01c19000 0x0400>;
579 clocks = <&ccu CLK_BUS_OTG>;
580 resets = <&ccu RST_BUS_OTG>;
581 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
582 interrupt-names = "mc";
585 extcon = <&usbphy 0>;
590 usbphy: phy@1c19400 {
591 compatible = "allwinner,sun50i-a64-usb-phy";
592 reg = <0x01c19400 0x14>,
595 reg-names = "phy_ctrl",
598 clocks = <&ccu CLK_USB_PHY0>,
600 clock-names = "usb0_phy",
602 resets = <&ccu RST_USB_PHY0>,
604 reset-names = "usb0_reset",
611 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
612 reg = <0x01c1a000 0x100>;
613 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&ccu CLK_BUS_OHCI0>,
615 <&ccu CLK_BUS_EHCI0>,
616 <&ccu CLK_USB_OHCI0>;
617 resets = <&ccu RST_BUS_OHCI0>,
618 <&ccu RST_BUS_EHCI0>;
625 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
626 reg = <0x01c1a400 0x100>;
627 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&ccu CLK_BUS_OHCI0>,
629 <&ccu CLK_USB_OHCI0>;
630 resets = <&ccu RST_BUS_OHCI0>;
637 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
638 reg = <0x01c1b000 0x100>;
639 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&ccu CLK_BUS_OHCI1>,
641 <&ccu CLK_BUS_EHCI1>,
642 <&ccu CLK_USB_OHCI1>;
643 resets = <&ccu RST_BUS_OHCI1>,
644 <&ccu RST_BUS_EHCI1>;
651 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
652 reg = <0x01c1b400 0x100>;
653 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&ccu CLK_BUS_OHCI1>,
655 <&ccu CLK_USB_OHCI1>;
656 resets = <&ccu RST_BUS_OHCI1>;
663 compatible = "allwinner,sun50i-a64-ccu";
664 reg = <0x01c20000 0x400>;
665 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
666 clock-names = "hosc", "losc";
671 pio: pinctrl@1c20800 {
672 compatible = "allwinner,sun50i-a64-pinctrl";
673 reg = <0x01c20800 0x400>;
674 interrupt-parent = <&r_intc>;
675 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
680 clock-names = "apb", "hosc", "losc";
683 interrupt-controller;
684 #interrupt-cells = <3>;
687 aif2_pins: aif2-pins {
688 pins = "PB4", "PB5", "PB6", "PB7";
693 aif3_pins: aif3-pins {
694 pins = "PG10", "PG11", "PG12", "PG13";
699 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
700 "PE7", "PE8", "PE9", "PE10", "PE11";
705 csi_mclk_pin: csi-mclk-pin {
710 i2c0_pins: i2c0-pins {
715 i2c1_pins: i2c1-pins {
720 i2c2_pins: i2c2-pins {
721 pins = "PE14", "PE15";
726 lcd_rgb666_pins: lcd-rgb666-pins {
727 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
728 "PD5", "PD6", "PD7", "PD8", "PD9",
729 "PD10", "PD11", "PD12", "PD13",
730 "PD14", "PD15", "PD16", "PD17",
731 "PD18", "PD19", "PD20", "PD21";
735 mmc0_pins: mmc0-pins {
736 pins = "PF0", "PF1", "PF2", "PF3",
739 drive-strength = <30>;
743 mmc1_pins: mmc1-pins {
744 pins = "PG0", "PG1", "PG2", "PG3",
747 drive-strength = <30>;
751 mmc2_pins: mmc2-pins {
752 pins = "PC5", "PC6", "PC8", "PC9",
753 "PC10","PC11", "PC12", "PC13",
754 "PC14", "PC15", "PC16";
756 drive-strength = <30>;
760 mmc2_ds_pin: mmc2-ds-pin {
763 drive-strength = <30>;
772 rmii_pins: rmii-pins {
773 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
774 "PD18", "PD19", "PD20", "PD22", "PD23";
776 drive-strength = <40>;
779 rgmii_pins: rgmii-pins {
780 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
781 "PD13", "PD15", "PD16", "PD17", "PD18",
782 "PD19", "PD20", "PD21", "PD22", "PD23";
784 drive-strength = <40>;
787 spdif_tx_pin: spdif-tx-pin {
792 spi0_pins: spi0-pins {
793 pins = "PC0", "PC1", "PC2", "PC3";
797 spi1_pins: spi1-pins {
798 pins = "PD0", "PD1", "PD2", "PD3";
802 uart0_pb_pins: uart0-pb-pins {
807 uart1_pins: uart1-pins {
812 uart1_rts_cts_pins: uart1-rts-cts-pins {
817 uart2_pins: uart2-pins {
822 uart3_pins: uart3-pins {
827 uart4_pins: uart4-pins {
832 uart4_rts_cts_pins: uart4-rts-cts-pins {
839 compatible = "allwinner,sun50i-a64-timer",
840 "allwinner,sun8i-a23-timer";
841 reg = <0x01c20c00 0xa0>;
842 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
843 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
847 wdt0: watchdog@1c20ca0 {
848 compatible = "allwinner,sun50i-a64-wdt",
849 "allwinner,sun6i-a31-wdt";
850 reg = <0x01c20ca0 0x20>;
851 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
855 spdif: spdif@1c21000 {
856 #sound-dai-cells = <0>;
857 compatible = "allwinner,sun50i-a64-spdif",
858 "allwinner,sun8i-h3-spdif";
859 reg = <0x01c21000 0x400>;
860 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
862 resets = <&ccu RST_BUS_SPDIF>;
863 clock-names = "apb", "spdif";
866 pinctrl-names = "default";
867 pinctrl-0 = <&spdif_tx_pin>;
871 lradc: lradc@1c21800 {
872 compatible = "allwinner,sun50i-a64-lradc",
873 "allwinner,sun8i-a83t-r-lradc";
874 reg = <0x01c21800 0x400>;
875 interrupt-parent = <&r_intc>;
876 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
881 #sound-dai-cells = <0>;
882 compatible = "allwinner,sun50i-a64-i2s",
883 "allwinner,sun8i-h3-i2s";
884 reg = <0x01c22000 0x400>;
885 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
887 clock-names = "apb", "mod";
888 resets = <&ccu RST_BUS_I2S0>;
889 dma-names = "rx", "tx";
890 dmas = <&dma 3>, <&dma 3>;
895 #sound-dai-cells = <0>;
896 compatible = "allwinner,sun50i-a64-i2s",
897 "allwinner,sun8i-h3-i2s";
898 reg = <0x01c22400 0x400>;
899 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
901 clock-names = "apb", "mod";
902 resets = <&ccu RST_BUS_I2S1>;
903 dma-names = "rx", "tx";
904 dmas = <&dma 4>, <&dma 4>;
909 #sound-dai-cells = <0>;
910 compatible = "allwinner,sun50i-a64-i2s",
911 "allwinner,sun8i-h3-i2s";
912 reg = <0x01c22800 0x400>;
913 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
915 clock-names = "apb", "mod";
916 resets = <&ccu RST_BUS_I2S2>;
917 dma-names = "rx", "tx";
918 dmas = <&dma 27>, <&dma 27>;
923 #sound-dai-cells = <0>;
924 compatible = "allwinner,sun50i-a64-codec-i2s";
925 reg = <0x01c22c00 0x200>;
926 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
928 clock-names = "apb", "mod";
929 resets = <&ccu RST_BUS_CODEC>;
930 dmas = <&dma 15>, <&dma 15>;
931 dma-names = "rx", "tx";
935 codec: codec@1c22e00 {
936 #sound-dai-cells = <1>;
937 compatible = "allwinner,sun50i-a64-codec",
938 "allwinner,sun8i-a33-codec";
939 reg = <0x01c22e00 0x600>;
940 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
941 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
942 clock-names = "bus", "mod";
946 ths: thermal-sensor@1c25000 {
947 compatible = "allwinner,sun50i-a64-ths";
948 reg = <0x01c25000 0x100>;
949 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
950 clock-names = "bus", "mod";
951 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
952 resets = <&ccu RST_BUS_THS>;
953 nvmem-cells = <&ths_calibration>;
954 nvmem-cell-names = "calibration";
955 #thermal-sensor-cells = <1>;
958 uart0: serial@1c28000 {
959 compatible = "snps,dw-apb-uart";
960 reg = <0x01c28000 0x400>;
961 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
964 clocks = <&ccu CLK_BUS_UART0>;
965 resets = <&ccu RST_BUS_UART0>;
969 uart1: serial@1c28400 {
970 compatible = "snps,dw-apb-uart";
971 reg = <0x01c28400 0x400>;
972 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&ccu CLK_BUS_UART1>;
976 resets = <&ccu RST_BUS_UART1>;
980 uart2: serial@1c28800 {
981 compatible = "snps,dw-apb-uart";
982 reg = <0x01c28800 0x400>;
983 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
986 clocks = <&ccu CLK_BUS_UART2>;
987 resets = <&ccu RST_BUS_UART2>;
991 uart3: serial@1c28c00 {
992 compatible = "snps,dw-apb-uart";
993 reg = <0x01c28c00 0x400>;
994 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&ccu CLK_BUS_UART3>;
998 resets = <&ccu RST_BUS_UART3>;
1002 uart4: serial@1c29000 {
1003 compatible = "snps,dw-apb-uart";
1004 reg = <0x01c29000 0x400>;
1005 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&ccu CLK_BUS_UART4>;
1009 resets = <&ccu RST_BUS_UART4>;
1010 status = "disabled";
1014 compatible = "allwinner,sun6i-a31-i2c";
1015 reg = <0x01c2ac00 0x400>;
1016 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&ccu CLK_BUS_I2C0>;
1018 resets = <&ccu RST_BUS_I2C0>;
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&i2c0_pins>;
1021 status = "disabled";
1022 #address-cells = <1>;
1027 compatible = "allwinner,sun6i-a31-i2c";
1028 reg = <0x01c2b000 0x400>;
1029 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&ccu CLK_BUS_I2C1>;
1031 resets = <&ccu RST_BUS_I2C1>;
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&i2c1_pins>;
1034 status = "disabled";
1035 #address-cells = <1>;
1040 compatible = "allwinner,sun6i-a31-i2c";
1041 reg = <0x01c2b400 0x400>;
1042 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&ccu CLK_BUS_I2C2>;
1044 resets = <&ccu RST_BUS_I2C2>;
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&i2c2_pins>;
1047 status = "disabled";
1048 #address-cells = <1>;
1053 compatible = "allwinner,sun8i-h3-spi";
1054 reg = <0x01c68000 0x1000>;
1055 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1056 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1057 clock-names = "ahb", "mod";
1058 dmas = <&dma 23>, <&dma 23>;
1059 dma-names = "rx", "tx";
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&spi0_pins>;
1062 resets = <&ccu RST_BUS_SPI0>;
1063 status = "disabled";
1065 #address-cells = <1>;
1070 compatible = "allwinner,sun8i-h3-spi";
1071 reg = <0x01c69000 0x1000>;
1072 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1074 clock-names = "ahb", "mod";
1075 dmas = <&dma 24>, <&dma 24>;
1076 dma-names = "rx", "tx";
1077 pinctrl-names = "default";
1078 pinctrl-0 = <&spi1_pins>;
1079 resets = <&ccu RST_BUS_SPI1>;
1080 status = "disabled";
1082 #address-cells = <1>;
1086 emac: ethernet@1c30000 {
1087 compatible = "allwinner,sun50i-a64-emac";
1089 reg = <0x01c30000 0x10000>;
1090 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1091 interrupt-names = "macirq";
1092 resets = <&ccu RST_BUS_EMAC>;
1093 reset-names = "stmmaceth";
1094 clocks = <&ccu CLK_BUS_EMAC>;
1095 clock-names = "stmmaceth";
1096 status = "disabled";
1099 compatible = "snps,dwmac-mdio";
1100 #address-cells = <1>;
1106 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1107 reg = <0x01c40000 0x10000>;
1108 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1115 interrupt-names = "gp",
1122 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1123 clock-names = "bus", "core";
1124 resets = <&ccu RST_BUS_GPU>;
1125 operating-points-v2 = <&gpu_opp_table>;
1128 gic: interrupt-controller@1c81000 {
1129 compatible = "arm,gic-400";
1130 reg = <0x01c81000 0x1000>,
1131 <0x01c82000 0x2000>,
1132 <0x01c84000 0x2000>,
1133 <0x01c86000 0x2000>;
1134 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1135 interrupt-controller;
1136 #interrupt-cells = <3>;
1140 compatible = "allwinner,sun50i-a64-pwm",
1141 "allwinner,sun5i-a13-pwm";
1142 reg = <0x01c21400 0x400>;
1144 pinctrl-names = "default";
1145 pinctrl-0 = <&pwm_pin>;
1147 status = "disabled";
1150 mbus: dram-controller@1c62000 {
1151 compatible = "allwinner,sun50i-a64-mbus";
1152 reg = <0x01c62000 0x1000>,
1153 <0x01c63000 0x1000>;
1154 reg-names = "mbus", "dram";
1155 clocks = <&ccu CLK_MBUS>,
1157 <&ccu CLK_BUS_DRAM>;
1158 clock-names = "mbus", "dram", "bus";
1159 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1160 #address-cells = <1>;
1162 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1163 #interconnect-cells = <1>;
1167 compatible = "allwinner,sun50i-a64-csi";
1168 reg = <0x01cb0000 0x1000>;
1169 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&ccu CLK_BUS_CSI>,
1171 <&ccu CLK_CSI_SCLK>,
1172 <&ccu CLK_DRAM_CSI>;
1173 clock-names = "bus", "mod", "ram";
1174 resets = <&ccu RST_BUS_CSI>;
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&csi_pins>;
1177 status = "disabled";
1181 compatible = "allwinner,sun50i-a64-mipi-dsi";
1182 reg = <0x01ca0000 0x1000>;
1183 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1184 clocks = <&ccu CLK_BUS_MIPI_DSI>;
1185 resets = <&ccu RST_BUS_MIPI_DSI>;
1188 status = "disabled";
1189 #address-cells = <1>;
1193 dsi_in_tcon0: endpoint {
1194 remote-endpoint = <&tcon0_out_dsi>;
1199 dphy: d-phy@1ca1000 {
1200 compatible = "allwinner,sun50i-a64-mipi-dphy",
1201 "allwinner,sun6i-a31-mipi-dphy";
1202 reg = <0x01ca1000 0x1000>;
1203 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1204 clocks = <&ccu CLK_BUS_MIPI_DSI>,
1205 <&ccu CLK_DSI_DPHY>;
1206 clock-names = "bus", "mod";
1207 resets = <&ccu RST_BUS_MIPI_DSI>;
1208 status = "disabled";
1212 deinterlace: deinterlace@1e00000 {
1213 compatible = "allwinner,sun50i-a64-deinterlace",
1214 "allwinner,sun8i-h3-deinterlace";
1215 reg = <0x01e00000 0x20000>;
1216 clocks = <&ccu CLK_BUS_DEINTERLACE>,
1217 <&ccu CLK_DEINTERLACE>,
1218 <&ccu CLK_DRAM_DEINTERLACE>;
1219 clock-names = "bus", "mod", "ram";
1220 resets = <&ccu RST_BUS_DEINTERLACE>;
1221 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1222 interconnects = <&mbus 9>;
1223 interconnect-names = "dma-mem";
1226 hdmi: hdmi@1ee0000 {
1227 compatible = "allwinner,sun50i-a64-dw-hdmi",
1228 "allwinner,sun8i-a83t-dw-hdmi";
1229 reg = <0x01ee0000 0x10000>;
1231 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1232 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1233 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
1234 clock-names = "iahb", "isfr", "tmds", "cec";
1235 resets = <&ccu RST_BUS_HDMI1>;
1236 reset-names = "ctrl";
1239 status = "disabled";
1242 #address-cells = <1>;
1248 hdmi_in_tcon1: endpoint {
1249 remote-endpoint = <&tcon1_out_hdmi>;
1259 hdmi_phy: hdmi-phy@1ef0000 {
1260 compatible = "allwinner,sun50i-a64-hdmi-phy";
1261 reg = <0x01ef0000 0x10000>;
1262 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1263 <&ccu CLK_PLL_VIDEO0>;
1264 clock-names = "bus", "mod", "pll-0";
1265 resets = <&ccu RST_BUS_HDMI0>;
1266 reset-names = "phy";
1271 compatible = "allwinner,sun50i-a64-rtc",
1272 "allwinner,sun8i-h3-rtc";
1273 reg = <0x01f00000 0x400>;
1274 interrupt-parent = <&r_intc>;
1275 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1277 clock-output-names = "osc32k", "osc32k-out", "iosc";
1282 r_intc: interrupt-controller@1f00c00 {
1283 compatible = "allwinner,sun50i-a64-r-intc",
1284 "allwinner,sun6i-a31-r-intc";
1285 interrupt-controller;
1286 #interrupt-cells = <3>;
1287 reg = <0x01f00c00 0x400>;
1288 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1291 r_ccu: clock@1f01400 {
1292 compatible = "allwinner,sun50i-a64-r-ccu";
1293 reg = <0x01f01400 0x100>;
1294 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
1295 <&ccu CLK_PLL_PERIPH0>;
1296 clock-names = "hosc", "losc", "iosc", "pll-periph";
1301 codec_analog: codec-analog@1f015c0 {
1302 compatible = "allwinner,sun50i-a64-codec-analog";
1303 reg = <0x01f015c0 0x4>;
1304 status = "disabled";
1307 r_i2c: i2c@1f02400 {
1308 compatible = "allwinner,sun50i-a64-i2c",
1309 "allwinner,sun6i-a31-i2c";
1310 reg = <0x01f02400 0x400>;
1311 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1312 clocks = <&r_ccu CLK_APB0_I2C>;
1313 resets = <&r_ccu RST_APB0_I2C>;
1314 status = "disabled";
1315 #address-cells = <1>;
1320 compatible = "allwinner,sun50i-a64-ir",
1321 "allwinner,sun6i-a31-ir";
1322 reg = <0x01f02000 0x400>;
1323 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1324 clock-names = "apb", "ir";
1325 resets = <&r_ccu RST_APB0_IR>;
1326 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1327 pinctrl-names = "default";
1328 pinctrl-0 = <&r_ir_rx_pin>;
1329 status = "disabled";
1332 r_pwm: pwm@1f03800 {
1333 compatible = "allwinner,sun50i-a64-pwm",
1334 "allwinner,sun5i-a13-pwm";
1335 reg = <0x01f03800 0x400>;
1337 pinctrl-names = "default";
1338 pinctrl-0 = <&r_pwm_pin>;
1340 status = "disabled";
1343 r_pio: pinctrl@1f02c00 {
1344 compatible = "allwinner,sun50i-a64-r-pinctrl";
1345 reg = <0x01f02c00 0x400>;
1346 interrupt-parent = <&r_intc>;
1347 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1348 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1349 clock-names = "apb", "hosc", "losc";
1352 interrupt-controller;
1353 #interrupt-cells = <3>;
1355 r_i2c_pl89_pins: r-i2c-pl89-pins {
1356 pins = "PL8", "PL9";
1360 r_ir_rx_pin: r-ir-rx-pin {
1362 function = "s_cir_rx";
1365 r_pwm_pin: r-pwm-pin {
1370 r_rsb_pins: r-rsb-pins {
1371 pins = "PL0", "PL1";
1376 r_rsb: rsb@1f03400 {
1377 compatible = "allwinner,sun8i-a23-rsb";
1378 reg = <0x01f03400 0x400>;
1379 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1380 clocks = <&r_ccu 6>;
1381 clock-frequency = <3000000>;
1382 resets = <&r_ccu 2>;
1383 pinctrl-names = "default";
1384 pinctrl-0 = <&r_rsb_pins>;
1385 status = "disabled";
1386 #address-cells = <1>;