2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
47 #include <dt-bindings/clock/sun8i-r-ccu.h>
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 #include <dt-bindings/reset/sun8i-de2.h>
51 #include <dt-bindings/reset/sun8i-r-ccu.h>
54 interrupt-parent = <&gic>;
63 simplefb_lcd: framebuffer-lcd {
64 compatible = "allwinner,simple-framebuffer",
66 allwinner,pipeline = "mixer0-lcd0";
67 clocks = <&ccu CLK_TCON0>,
68 <&display_clocks CLK_MIXER0>;
72 simplefb_hdmi: framebuffer-hdmi {
73 compatible = "allwinner,simple-framebuffer",
75 allwinner,pipeline = "mixer1-lcd1-hdmi";
76 clocks = <&display_clocks CLK_MIXER1>,
77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
87 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 next-level-cache = <&L2>;
95 compatible = "arm,cortex-a53";
98 enable-method = "psci";
99 next-level-cache = <&L2>;
103 compatible = "arm,cortex-a53";
106 enable-method = "psci";
107 next-level-cache = <&L2>;
111 compatible = "arm,cortex-a53";
114 enable-method = "psci";
115 next-level-cache = <&L2>;
119 compatible = "cache";
125 compatible = "allwinner,sun50i-a64-display-engine";
126 allwinner,pipelines = <&mixer0>,
133 compatible = "fixed-clock";
134 clock-frequency = <24000000>;
135 clock-output-names = "osc24M";
140 compatible = "fixed-clock";
141 clock-frequency = <32768>;
142 clock-output-names = "ext-osc32k";
146 compatible = "arm,cortex-a53-pmu";
147 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
155 compatible = "arm,psci-0.2";
160 compatible = "simple-audio-card";
161 simple-audio-card,name = "sun50i-a64-audio";
162 simple-audio-card,format = "i2s";
163 simple-audio-card,frame-master = <&cpudai>;
164 simple-audio-card,bitclock-master = <&cpudai>;
165 simple-audio-card,mclk-fs = <128>;
166 simple-audio-card,aux-devs = <&codec_analog>;
167 simple-audio-card,routing =
168 "Left DAC", "AIF1 Slot 0 Left",
169 "Right DAC", "AIF1 Slot 0 Right",
170 "AIF1 Slot 0 Left ADC", "Left ADC",
171 "AIF1 Slot 0 Right ADC", "Right ADC";
174 cpudai: simple-audio-card,cpu {
178 link_codec: simple-audio-card,codec {
179 sound-dai = <&codec>;
184 compatible = "simple-audio-card";
185 simple-audio-card,name = "On-board SPDIF";
187 simple-audio-card,cpu {
188 sound-dai = <&spdif>;
191 simple-audio-card,codec {
192 sound-dai = <&spdif_out>;
196 spdif_out: spdif-out {
197 #sound-dai-cells = <0>;
198 compatible = "linux,spdif-dit";
202 compatible = "arm,armv8-timer";
203 allwinner,erratum-unknown1;
204 interrupts = <GIC_PPI 13
205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
207 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
211 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
215 compatible = "simple-bus";
216 #address-cells = <1>;
221 compatible = "allwinner,sun50i-a64-de2";
222 reg = <0x1000000 0x400000>;
223 allwinner,sram = <&de2_sram 1>;
224 #address-cells = <1>;
226 ranges = <0 0x1000000 0x400000>;
228 display_clocks: clock@0 {
229 compatible = "allwinner,sun50i-a64-de2-clk";
231 clocks = <&ccu CLK_BUS_DE>,
235 resets = <&ccu RST_BUS_DE>;
240 mixer0: mixer@100000 {
241 compatible = "allwinner,sun50i-a64-de2-mixer-0";
242 reg = <0x100000 0x100000>;
243 clocks = <&display_clocks CLK_BUS_MIXER0>,
244 <&display_clocks CLK_MIXER0>;
247 resets = <&display_clocks RST_MIXER0>;
250 #address-cells = <1>;
254 #address-cells = <1>;
258 mixer0_out_tcon0: endpoint@0 {
260 remote-endpoint = <&tcon0_in_mixer0>;
263 mixer0_out_tcon1: endpoint@1 {
265 remote-endpoint = <&tcon1_in_mixer0>;
271 mixer1: mixer@200000 {
272 compatible = "allwinner,sun50i-a64-de2-mixer-1";
273 reg = <0x200000 0x100000>;
274 clocks = <&display_clocks CLK_BUS_MIXER1>,
275 <&display_clocks CLK_MIXER1>;
278 resets = <&display_clocks RST_MIXER1>;
281 #address-cells = <1>;
285 #address-cells = <1>;
289 mixer1_out_tcon0: endpoint@0 {
291 remote-endpoint = <&tcon0_in_mixer1>;
294 mixer1_out_tcon1: endpoint@1 {
296 remote-endpoint = <&tcon1_in_mixer1>;
303 syscon: syscon@1c00000 {
304 compatible = "allwinner,sun50i-a64-system-control";
305 reg = <0x01c00000 0x1000>;
306 #address-cells = <1>;
311 compatible = "mmio-sram";
312 reg = <0x00018000 0x28000>;
313 #address-cells = <1>;
315 ranges = <0 0x00018000 0x28000>;
317 de2_sram: sram-section@0 {
318 compatible = "allwinner,sun50i-a64-sram-c";
319 reg = <0x0000 0x28000>;
323 sram_c1: sram@1d00000 {
324 compatible = "mmio-sram";
325 reg = <0x01d00000 0x40000>;
326 #address-cells = <1>;
328 ranges = <0 0x01d00000 0x40000>;
330 ve_sram: sram-section@0 {
331 compatible = "allwinner,sun50i-a64-sram-c1",
332 "allwinner,sun4i-a10-sram-c1";
333 reg = <0x000000 0x40000>;
338 dma: dma-controller@1c02000 {
339 compatible = "allwinner,sun50i-a64-dma";
340 reg = <0x01c02000 0x1000>;
341 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&ccu CLK_BUS_DMA>;
345 resets = <&ccu RST_BUS_DMA>;
349 tcon0: lcd-controller@1c0c000 {
350 compatible = "allwinner,sun50i-a64-tcon-lcd",
351 "allwinner,sun8i-a83t-tcon-lcd";
352 reg = <0x01c0c000 0x1000>;
353 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
355 clock-names = "ahb", "tcon-ch0";
356 clock-output-names = "tcon-pixel-clock";
358 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
359 reset-names = "lcd", "lvds";
362 #address-cells = <1>;
366 #address-cells = <1>;
370 tcon0_in_mixer0: endpoint@0 {
372 remote-endpoint = <&mixer0_out_tcon0>;
375 tcon0_in_mixer1: endpoint@1 {
377 remote-endpoint = <&mixer1_out_tcon0>;
382 #address-cells = <1>;
389 tcon1: lcd-controller@1c0d000 {
390 compatible = "allwinner,sun50i-a64-tcon-tv",
391 "allwinner,sun8i-a83t-tcon-tv";
392 reg = <0x01c0d000 0x1000>;
393 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
395 clock-names = "ahb", "tcon-ch1";
396 resets = <&ccu RST_BUS_TCON1>;
400 #address-cells = <1>;
404 #address-cells = <1>;
408 tcon1_in_mixer0: endpoint@0 {
410 remote-endpoint = <&mixer0_out_tcon1>;
413 tcon1_in_mixer1: endpoint@1 {
415 remote-endpoint = <&mixer1_out_tcon1>;
420 #address-cells = <1>;
424 tcon1_out_hdmi: endpoint@1 {
426 remote-endpoint = <&hdmi_in_tcon1>;
432 video-codec@1c0e000 {
433 compatible = "allwinner,sun50i-a64-video-engine";
434 reg = <0x01c0e000 0x1000>;
435 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
437 clock-names = "ahb", "mod", "ram";
438 resets = <&ccu RST_BUS_VE>;
439 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
440 allwinner,sram = <&ve_sram 1>;
444 compatible = "allwinner,sun50i-a64-mmc";
445 reg = <0x01c0f000 0x1000>;
446 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
447 clock-names = "ahb", "mmc";
448 resets = <&ccu RST_BUS_MMC0>;
450 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
451 max-frequency = <150000000>;
453 #address-cells = <1>;
458 compatible = "allwinner,sun50i-a64-mmc";
459 reg = <0x01c10000 0x1000>;
460 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
461 clock-names = "ahb", "mmc";
462 resets = <&ccu RST_BUS_MMC1>;
464 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
465 max-frequency = <150000000>;
467 #address-cells = <1>;
472 compatible = "allwinner,sun50i-a64-emmc";
473 reg = <0x01c11000 0x1000>;
474 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
475 clock-names = "ahb", "mmc";
476 resets = <&ccu RST_BUS_MMC2>;
478 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
479 max-frequency = <150000000>;
481 #address-cells = <1>;
485 sid: eeprom@1c14000 {
486 compatible = "allwinner,sun50i-a64-sid";
487 reg = <0x1c14000 0x400>;
490 usb_otg: usb@1c19000 {
491 compatible = "allwinner,sun8i-a33-musb";
492 reg = <0x01c19000 0x0400>;
493 clocks = <&ccu CLK_BUS_OTG>;
494 resets = <&ccu RST_BUS_OTG>;
495 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
496 interrupt-names = "mc";
499 extcon = <&usbphy 0>;
504 usbphy: phy@1c19400 {
505 compatible = "allwinner,sun50i-a64-usb-phy";
506 reg = <0x01c19400 0x14>,
509 reg-names = "phy_ctrl",
512 clocks = <&ccu CLK_USB_PHY0>,
514 clock-names = "usb0_phy",
516 resets = <&ccu RST_USB_PHY0>,
518 reset-names = "usb0_reset",
525 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
526 reg = <0x01c1a000 0x100>;
527 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&ccu CLK_BUS_OHCI0>,
529 <&ccu CLK_BUS_EHCI0>,
530 <&ccu CLK_USB_OHCI0>;
531 resets = <&ccu RST_BUS_OHCI0>,
532 <&ccu RST_BUS_EHCI0>;
539 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
540 reg = <0x01c1a400 0x100>;
541 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&ccu CLK_BUS_OHCI0>,
543 <&ccu CLK_USB_OHCI0>;
544 resets = <&ccu RST_BUS_OHCI0>;
551 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
552 reg = <0x01c1b000 0x100>;
553 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&ccu CLK_BUS_OHCI1>,
555 <&ccu CLK_BUS_EHCI1>,
556 <&ccu CLK_USB_OHCI1>;
557 resets = <&ccu RST_BUS_OHCI1>,
558 <&ccu RST_BUS_EHCI1>;
565 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
566 reg = <0x01c1b400 0x100>;
567 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&ccu CLK_BUS_OHCI1>,
569 <&ccu CLK_USB_OHCI1>;
570 resets = <&ccu RST_BUS_OHCI1>;
577 compatible = "allwinner,sun50i-a64-ccu";
578 reg = <0x01c20000 0x400>;
579 clocks = <&osc24M>, <&rtc 0>;
580 clock-names = "hosc", "losc";
585 pio: pinctrl@1c20800 {
586 compatible = "allwinner,sun50i-a64-pinctrl";
587 reg = <0x01c20800 0x400>;
588 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>;
592 clock-names = "apb", "hosc", "losc";
595 interrupt-controller;
596 #interrupt-cells = <3>;
599 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
600 "PE7", "PE8", "PE9", "PE10", "PE11";
605 csi_mclk_pin: csi-mclk-pin {
610 i2c0_pins: i2c0-pins {
615 i2c1_pins: i2c1-pins {
621 lcd_rgb666_pins: lcd-rgb666-pins {
622 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
623 "PD5", "PD6", "PD7", "PD8", "PD9",
624 "PD10", "PD11", "PD12", "PD13",
625 "PD14", "PD15", "PD16", "PD17",
626 "PD18", "PD19", "PD20", "PD21";
630 mmc0_pins: mmc0-pins {
631 pins = "PF0", "PF1", "PF2", "PF3",
634 drive-strength = <30>;
638 mmc1_pins: mmc1-pins {
639 pins = "PG0", "PG1", "PG2", "PG3",
642 drive-strength = <30>;
646 mmc2_pins: mmc2-pins {
647 pins = "PC5", "PC6", "PC8", "PC9",
648 "PC10","PC11", "PC12", "PC13",
649 "PC14", "PC15", "PC16";
651 drive-strength = <30>;
655 mmc2_ds_pin: mmc2-ds-pin {
658 drive-strength = <30>;
667 rmii_pins: rmii-pins {
668 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
669 "PD18", "PD19", "PD20", "PD22", "PD23";
671 drive-strength = <40>;
674 rgmii_pins: rgmii-pins {
675 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
676 "PD13", "PD15", "PD16", "PD17", "PD18",
677 "PD19", "PD20", "PD21", "PD22", "PD23";
679 drive-strength = <40>;
682 spdif_tx_pin: spdif-tx-pin {
687 spi0_pins: spi0-pins {
688 pins = "PC0", "PC1", "PC2", "PC3";
692 spi1_pins: spi1-pins {
693 pins = "PD0", "PD1", "PD2", "PD3";
697 uart0_pb_pins: uart0-pb-pins {
702 uart1_pins: uart1-pins {
707 uart1_rts_cts_pins: uart1-rts-cts-pins {
712 uart2_pins: uart2-pins {
717 uart3_pins: uart3-pins {
722 uart4_pins: uart4-pins {
727 uart4_rts_cts_pins: uart4-rts-cts-pins {
733 spdif: spdif@1c21000 {
734 #sound-dai-cells = <0>;
735 compatible = "allwinner,sun50i-a64-spdif",
736 "allwinner,sun8i-h3-spdif";
737 reg = <0x01c21000 0x400>;
738 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
740 resets = <&ccu RST_BUS_SPDIF>;
741 clock-names = "apb", "spdif";
744 pinctrl-names = "default";
745 pinctrl-0 = <&spdif_tx_pin>;
749 lradc: lradc@1c21800 {
750 compatible = "allwinner,sun50i-a64-lradc",
751 "allwinner,sun8i-a83t-r-lradc";
752 reg = <0x01c21800 0x400>;
753 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
758 #sound-dai-cells = <0>;
759 compatible = "allwinner,sun50i-a64-i2s",
760 "allwinner,sun8i-h3-i2s";
761 reg = <0x01c22000 0x400>;
762 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
764 clock-names = "apb", "mod";
765 resets = <&ccu RST_BUS_I2S0>;
766 dma-names = "rx", "tx";
767 dmas = <&dma 3>, <&dma 3>;
772 #sound-dai-cells = <0>;
773 compatible = "allwinner,sun50i-a64-i2s",
774 "allwinner,sun8i-h3-i2s";
775 reg = <0x01c22400 0x400>;
776 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
778 clock-names = "apb", "mod";
779 resets = <&ccu RST_BUS_I2S1>;
780 dma-names = "rx", "tx";
781 dmas = <&dma 4>, <&dma 4>;
786 #sound-dai-cells = <0>;
787 compatible = "allwinner,sun50i-a64-codec-i2s";
788 reg = <0x01c22c00 0x200>;
789 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
791 clock-names = "apb", "mod";
792 resets = <&ccu RST_BUS_CODEC>;
793 dmas = <&dma 15>, <&dma 15>;
794 dma-names = "rx", "tx";
798 codec: codec@1c22e00 {
799 #sound-dai-cells = <0>;
800 compatible = "allwinner,sun8i-a33-codec";
801 reg = <0x01c22e00 0x600>;
802 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
804 clock-names = "bus", "mod";
808 uart0: serial@1c28000 {
809 compatible = "snps,dw-apb-uart";
810 reg = <0x01c28000 0x400>;
811 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&ccu CLK_BUS_UART0>;
815 resets = <&ccu RST_BUS_UART0>;
819 uart1: serial@1c28400 {
820 compatible = "snps,dw-apb-uart";
821 reg = <0x01c28400 0x400>;
822 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&ccu CLK_BUS_UART1>;
826 resets = <&ccu RST_BUS_UART1>;
830 uart2: serial@1c28800 {
831 compatible = "snps,dw-apb-uart";
832 reg = <0x01c28800 0x400>;
833 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&ccu CLK_BUS_UART2>;
837 resets = <&ccu RST_BUS_UART2>;
841 uart3: serial@1c28c00 {
842 compatible = "snps,dw-apb-uart";
843 reg = <0x01c28c00 0x400>;
844 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&ccu CLK_BUS_UART3>;
848 resets = <&ccu RST_BUS_UART3>;
852 uart4: serial@1c29000 {
853 compatible = "snps,dw-apb-uart";
854 reg = <0x01c29000 0x400>;
855 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&ccu CLK_BUS_UART4>;
859 resets = <&ccu RST_BUS_UART4>;
864 compatible = "allwinner,sun6i-a31-i2c";
865 reg = <0x01c2ac00 0x400>;
866 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&ccu CLK_BUS_I2C0>;
868 resets = <&ccu RST_BUS_I2C0>;
869 pinctrl-names = "default";
870 pinctrl-0 = <&i2c0_pins>;
872 #address-cells = <1>;
877 compatible = "allwinner,sun6i-a31-i2c";
878 reg = <0x01c2b000 0x400>;
879 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&ccu CLK_BUS_I2C1>;
881 resets = <&ccu RST_BUS_I2C1>;
882 pinctrl-names = "default";
883 pinctrl-0 = <&i2c1_pins>;
885 #address-cells = <1>;
890 compatible = "allwinner,sun6i-a31-i2c";
891 reg = <0x01c2b400 0x400>;
892 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&ccu CLK_BUS_I2C2>;
894 resets = <&ccu RST_BUS_I2C2>;
896 #address-cells = <1>;
902 compatible = "allwinner,sun8i-h3-spi";
903 reg = <0x01c68000 0x1000>;
904 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
906 clock-names = "ahb", "mod";
907 dmas = <&dma 23>, <&dma 23>;
908 dma-names = "rx", "tx";
909 pinctrl-names = "default";
910 pinctrl-0 = <&spi0_pins>;
911 resets = <&ccu RST_BUS_SPI0>;
914 #address-cells = <1>;
919 compatible = "allwinner,sun8i-h3-spi";
920 reg = <0x01c69000 0x1000>;
921 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
922 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
923 clock-names = "ahb", "mod";
924 dmas = <&dma 24>, <&dma 24>;
925 dma-names = "rx", "tx";
926 pinctrl-names = "default";
927 pinctrl-0 = <&spi1_pins>;
928 resets = <&ccu RST_BUS_SPI1>;
931 #address-cells = <1>;
935 emac: ethernet@1c30000 {
936 compatible = "allwinner,sun50i-a64-emac";
938 reg = <0x01c30000 0x10000>;
939 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
940 interrupt-names = "macirq";
941 resets = <&ccu RST_BUS_EMAC>;
942 reset-names = "stmmaceth";
943 clocks = <&ccu CLK_BUS_EMAC>;
944 clock-names = "stmmaceth";
948 compatible = "snps,dwmac-mdio";
949 #address-cells = <1>;
955 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
956 reg = <0x01c40000 0x10000>;
957 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
964 interrupt-names = "gp",
971 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
972 clock-names = "bus", "core";
973 resets = <&ccu RST_BUS_GPU>;
976 gic: interrupt-controller@1c81000 {
977 compatible = "arm,gic-400";
978 reg = <0x01c81000 0x1000>,
982 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
983 interrupt-controller;
984 #interrupt-cells = <3>;
988 compatible = "allwinner,sun50i-a64-pwm",
989 "allwinner,sun5i-a13-pwm";
990 reg = <0x01c21400 0x400>;
992 pinctrl-names = "default";
993 pinctrl-0 = <&pwm_pin>;
999 compatible = "allwinner,sun50i-a64-csi";
1000 reg = <0x01cb0000 0x1000>;
1001 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&ccu CLK_BUS_CSI>,
1003 <&ccu CLK_CSI_SCLK>,
1004 <&ccu CLK_DRAM_CSI>;
1005 clock-names = "bus", "mod", "ram";
1006 resets = <&ccu RST_BUS_CSI>;
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&csi_pins>;
1009 status = "disabled";
1012 hdmi: hdmi@1ee0000 {
1013 compatible = "allwinner,sun50i-a64-dw-hdmi",
1014 "allwinner,sun8i-a83t-dw-hdmi";
1015 reg = <0x01ee0000 0x10000>;
1017 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1018 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1020 clock-names = "iahb", "isfr", "tmds";
1021 resets = <&ccu RST_BUS_HDMI1>;
1022 reset-names = "ctrl";
1025 status = "disabled";
1028 #address-cells = <1>;
1034 hdmi_in_tcon1: endpoint {
1035 remote-endpoint = <&tcon1_out_hdmi>;
1045 hdmi_phy: hdmi-phy@1ef0000 {
1046 compatible = "allwinner,sun50i-a64-hdmi-phy";
1047 reg = <0x01ef0000 0x10000>;
1048 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1050 clock-names = "bus", "mod", "pll-0";
1051 resets = <&ccu RST_BUS_HDMI0>;
1052 reset-names = "phy";
1057 compatible = "allwinner,sun50i-a64-rtc",
1058 "allwinner,sun8i-h3-rtc";
1059 reg = <0x01f00000 0x400>;
1060 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1061 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1062 clock-output-names = "osc32k", "osc32k-out", "iosc";
1067 r_intc: interrupt-controller@1f00c00 {
1068 compatible = "allwinner,sun50i-a64-r-intc",
1069 "allwinner,sun6i-a31-r-intc";
1070 interrupt-controller;
1071 #interrupt-cells = <2>;
1072 reg = <0x01f00c00 0x400>;
1073 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1076 r_ccu: clock@1f01400 {
1077 compatible = "allwinner,sun50i-a64-r-ccu";
1078 reg = <0x01f01400 0x100>;
1079 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>;
1080 clock-names = "hosc", "losc", "iosc", "pll-periph";
1085 codec_analog: codec-analog@1f015c0 {
1086 compatible = "allwinner,sun50i-a64-codec-analog";
1087 reg = <0x01f015c0 0x4>;
1088 status = "disabled";
1091 r_i2c: i2c@1f02400 {
1092 compatible = "allwinner,sun50i-a64-i2c",
1093 "allwinner,sun6i-a31-i2c";
1094 reg = <0x01f02400 0x400>;
1095 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&r_ccu CLK_APB0_I2C>;
1097 resets = <&r_ccu RST_APB0_I2C>;
1098 status = "disabled";
1099 #address-cells = <1>;
1104 compatible = "allwinner,sun50i-a64-ir",
1105 "allwinner,sun6i-a31-ir";
1106 reg = <0x01f02000 0x400>;
1107 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1108 clock-names = "apb", "ir";
1109 resets = <&r_ccu RST_APB0_IR>;
1110 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1111 pinctrl-names = "default";
1112 pinctrl-0 = <&r_ir_rx_pin>;
1113 status = "disabled";
1116 r_pwm: pwm@1f03800 {
1117 compatible = "allwinner,sun50i-a64-pwm",
1118 "allwinner,sun5i-a13-pwm";
1119 reg = <0x01f03800 0x400>;
1121 pinctrl-names = "default";
1122 pinctrl-0 = <&r_pwm_pin>;
1124 status = "disabled";
1127 r_pio: pinctrl@1f02c00 {
1128 compatible = "allwinner,sun50i-a64-r-pinctrl";
1129 reg = <0x01f02c00 0x400>;
1130 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1131 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1132 clock-names = "apb", "hosc", "losc";
1135 interrupt-controller;
1136 #interrupt-cells = <3>;
1138 r_i2c_pl89_pins: r-i2c-pl89-pins {
1139 pins = "PL8", "PL9";
1143 r_ir_rx_pin: r-ir-rx-pin {
1145 function = "s_cir_rx";
1148 r_pwm_pin: r-pwm-pin {
1153 r_rsb_pins: r-rsb-pins {
1154 pins = "PL0", "PL1";
1159 r_rsb: rsb@1f03400 {
1160 compatible = "allwinner,sun8i-a23-rsb";
1161 reg = <0x01f03400 0x400>;
1162 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1163 clocks = <&r_ccu 6>;
1164 clock-frequency = <3000000>;
1165 resets = <&r_ccu 2>;
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&r_rsb_pins>;
1168 status = "disabled";
1169 #address-cells = <1>;
1173 wdt0: watchdog@1c20ca0 {
1174 compatible = "allwinner,sun50i-a64-wdt",
1175 "allwinner,sun6i-a31-wdt";
1176 reg = <0x01c20ca0 0x20>;
1177 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;