2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
46 #include <dt-bindings/clock/sun8i-r-ccu.h>
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/reset/sun50i-a64-ccu.h>
51 interrupt-parent = <&gic>;
60 compatible = "arm,cortex-a53", "arm,armv8";
63 enable-method = "psci";
67 compatible = "arm,cortex-a53", "arm,armv8";
70 enable-method = "psci";
74 compatible = "arm,cortex-a53", "arm,armv8";
77 enable-method = "psci";
81 compatible = "arm,cortex-a53", "arm,armv8";
84 enable-method = "psci";
90 compatible = "fixed-clock";
91 clock-frequency = <24000000>;
92 clock-output-names = "osc24M";
97 compatible = "fixed-clock";
98 clock-frequency = <32768>;
99 clock-output-names = "osc32k";
102 iosc: internal-osc-clk {
104 compatible = "fixed-clock";
105 clock-frequency = <16000000>;
106 clock-accuracy = <300000000>;
107 clock-output-names = "iosc";
111 compatible = "arm,psci-0.2";
116 compatible = "arm,armv8-timer";
117 interrupts = <GIC_PPI 13
118 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
120 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
122 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
124 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
128 compatible = "simple-bus";
129 #address-cells = <1>;
133 syscon: syscon@1c00000 {
134 compatible = "allwinner,sun50i-a64-system-controller",
136 reg = <0x01c00000 0x1000>;
140 compatible = "allwinner,sun50i-a64-mmc";
141 reg = <0x01c0f000 0x1000>;
142 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
143 clock-names = "ahb", "mmc";
144 resets = <&ccu RST_BUS_MMC0>;
146 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
147 max-frequency = <150000000>;
149 #address-cells = <1>;
154 compatible = "allwinner,sun50i-a64-mmc";
155 reg = <0x01c10000 0x1000>;
156 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
157 clock-names = "ahb", "mmc";
158 resets = <&ccu RST_BUS_MMC1>;
160 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
161 max-frequency = <150000000>;
163 #address-cells = <1>;
168 compatible = "allwinner,sun50i-a64-emmc";
169 reg = <0x01c11000 0x1000>;
170 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
171 clock-names = "ahb", "mmc";
172 resets = <&ccu RST_BUS_MMC2>;
174 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
175 max-frequency = <200000000>;
177 #address-cells = <1>;
181 usb_otg: usb@01c19000 {
182 compatible = "allwinner,sun8i-a33-musb";
183 reg = <0x01c19000 0x0400>;
184 clocks = <&ccu CLK_BUS_OTG>;
185 resets = <&ccu RST_BUS_OTG>;
186 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
187 interrupt-names = "mc";
190 extcon = <&usbphy 0>;
194 usbphy: phy@01c19400 {
195 compatible = "allwinner,sun50i-a64-usb-phy";
196 reg = <0x01c19400 0x14>,
199 reg-names = "phy_ctrl",
202 clocks = <&ccu CLK_USB_PHY0>,
204 clock-names = "usb0_phy",
206 resets = <&ccu RST_USB_PHY0>,
208 reset-names = "usb0_reset",
214 ehci0: usb@01c1a000 {
215 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
216 reg = <0x01c1a000 0x100>;
217 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&ccu CLK_BUS_OHCI0>,
219 <&ccu CLK_BUS_EHCI0>,
220 <&ccu CLK_USB_OHCI0>;
221 resets = <&ccu RST_BUS_OHCI0>,
222 <&ccu RST_BUS_EHCI0>;
226 ohci0: usb@01c1a400 {
227 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
228 reg = <0x01c1a400 0x100>;
229 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&ccu CLK_BUS_OHCI0>,
231 <&ccu CLK_USB_OHCI0>;
232 resets = <&ccu RST_BUS_OHCI0>;
236 ehci1: usb@01c1b000 {
237 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
238 reg = <0x01c1b000 0x100>;
239 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&ccu CLK_BUS_OHCI1>,
241 <&ccu CLK_BUS_EHCI1>,
242 <&ccu CLK_USB_OHCI1>;
243 resets = <&ccu RST_BUS_OHCI1>,
244 <&ccu RST_BUS_EHCI1>;
250 ohci1: usb@01c1b400 {
251 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
252 reg = <0x01c1b400 0x100>;
253 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&ccu CLK_BUS_OHCI1>,
255 <&ccu CLK_USB_OHCI1>;
256 resets = <&ccu RST_BUS_OHCI1>;
262 ccu: clock@01c20000 {
263 compatible = "allwinner,sun50i-a64-ccu";
264 reg = <0x01c20000 0x400>;
265 clocks = <&osc24M>, <&osc32k>;
266 clock-names = "hosc", "losc";
271 pio: pinctrl@1c20800 {
272 compatible = "allwinner,sun50i-a64-pinctrl";
273 reg = <0x01c20800 0x400>;
274 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>;
278 clock-names = "apb", "hosc", "losc";
281 interrupt-controller;
282 #interrupt-cells = <3>;
284 i2c1_pins: i2c1_pins {
289 mmc0_pins: mmc0-pins {
290 pins = "PF0", "PF1", "PF2", "PF3",
293 drive-strength = <30>;
297 mmc1_pins: mmc1-pins {
298 pins = "PG0", "PG1", "PG2", "PG3",
301 drive-strength = <30>;
305 mmc2_pins: mmc2-pins {
306 pins = "PC1", "PC5", "PC6", "PC8", "PC9",
307 "PC10","PC11", "PC12", "PC13",
308 "PC14", "PC15", "PC16";
310 drive-strength = <30>;
314 rmii_pins: rmii_pins {
315 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
316 "PD18", "PD19", "PD20", "PD22", "PD23";
318 drive-strength = <40>;
321 rgmii_pins: rgmii_pins {
322 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
323 "PD13", "PD15", "PD16", "PD17", "PD18",
324 "PD19", "PD20", "PD21", "PD22", "PD23";
326 drive-strength = <40>;
329 uart0_pins_a: uart0@0 {
334 uart1_pins: uart1_pins {
339 uart1_rts_cts_pins: uart1_rts_cts_pins {
344 uart2_pins: uart2-pins {
349 uart3_pins: uart3-pins {
354 uart4_pins: uart4-pins {
359 uart4_rts_cts_pins: uart4-rts-cts-pins {
365 uart0: serial@1c28000 {
366 compatible = "snps,dw-apb-uart";
367 reg = <0x01c28000 0x400>;
368 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&ccu CLK_BUS_UART0>;
372 resets = <&ccu RST_BUS_UART0>;
376 uart1: serial@1c28400 {
377 compatible = "snps,dw-apb-uart";
378 reg = <0x01c28400 0x400>;
379 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&ccu CLK_BUS_UART1>;
383 resets = <&ccu RST_BUS_UART1>;
387 uart2: serial@1c28800 {
388 compatible = "snps,dw-apb-uart";
389 reg = <0x01c28800 0x400>;
390 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&ccu CLK_BUS_UART2>;
394 resets = <&ccu RST_BUS_UART2>;
398 uart3: serial@1c28c00 {
399 compatible = "snps,dw-apb-uart";
400 reg = <0x01c28c00 0x400>;
401 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&ccu CLK_BUS_UART3>;
405 resets = <&ccu RST_BUS_UART3>;
409 uart4: serial@1c29000 {
410 compatible = "snps,dw-apb-uart";
411 reg = <0x01c29000 0x400>;
412 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&ccu CLK_BUS_UART4>;
416 resets = <&ccu RST_BUS_UART4>;
421 compatible = "allwinner,sun6i-a31-i2c";
422 reg = <0x01c2ac00 0x400>;
423 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&ccu CLK_BUS_I2C0>;
425 resets = <&ccu RST_BUS_I2C0>;
427 #address-cells = <1>;
432 compatible = "allwinner,sun6i-a31-i2c";
433 reg = <0x01c2b000 0x400>;
434 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&ccu CLK_BUS_I2C1>;
436 resets = <&ccu RST_BUS_I2C1>;
438 #address-cells = <1>;
443 compatible = "allwinner,sun6i-a31-i2c";
444 reg = <0x01c2b400 0x400>;
445 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&ccu CLK_BUS_I2C2>;
447 resets = <&ccu RST_BUS_I2C2>;
449 #address-cells = <1>;
453 gic: interrupt-controller@1c81000 {
454 compatible = "arm,gic-400";
455 reg = <0x01c81000 0x1000>,
459 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
460 interrupt-controller;
461 #interrupt-cells = <3>;
465 compatible = "allwinner,sun6i-a31-rtc";
466 reg = <0x01f00000 0x54>;
467 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
471 r_intc: interrupt-controller@1f00c00 {
472 compatible = "allwinner,sun50i-a64-r-intc",
473 "allwinner,sun6i-a31-r-intc";
474 interrupt-controller;
475 #interrupt-cells = <2>;
476 reg = <0x01f00c00 0x400>;
477 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
480 r_ccu: clock@1f01400 {
481 compatible = "allwinner,sun50i-a64-r-ccu";
482 reg = <0x01f01400 0x100>;
483 clocks = <&osc24M>, <&osc32k>, <&iosc>,
485 clock-names = "hosc", "losc", "iosc", "pll-periph";
490 r_pio: pinctrl@01f02c00 {
491 compatible = "allwinner,sun50i-a64-r-pinctrl";
492 reg = <0x01f02c00 0x400>;
493 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
495 clock-names = "apb", "hosc", "losc";
498 interrupt-controller;
499 #interrupt-cells = <3>;
508 compatible = "allwinner,sun8i-a23-rsb";
509 reg = <0x01f03400 0x400>;
510 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
512 clock-frequency = <3000000>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&r_rsb_pins>;
517 #address-cells = <1>;