3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ACPI_MCFG if ACPI
7 select ACPI_SPCR_TABLE if ACPI
8 select ARCH_CLOCKSOURCE_DATA
9 select ARCH_HAS_DEVMEM_IS_ALLOWED
10 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
11 select ARCH_HAS_ELF_RANDOMIZE
12 select ARCH_HAS_GCOV_PROFILE_ALL
13 select ARCH_HAS_GIGANTIC_PAGE
15 select ARCH_HAS_SG_CHAIN
16 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
17 select ARCH_USE_CMPXCHG_LOCKREF
18 select ARCH_SUPPORTS_ATOMIC_RMW
19 select ARCH_SUPPORTS_NUMA_BALANCING
20 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
21 select ARCH_WANT_FRAME_POINTERS
22 select ARCH_HAS_UBSAN_SANITIZE_ALL
26 select AUDIT_ARCH_COMPAT_GENERIC
27 select ARM_GIC_V2M if PCI
29 select ARM_GIC_V3_ITS if PCI
31 select BUILDTIME_EXTABLE_SORT
32 select CLONE_BACKWARDS
34 select CPU_PM if (SUSPEND || CPU_IDLE)
35 select DCACHE_WORD_ACCESS
38 select GENERIC_ALLOCATOR
39 select GENERIC_CLOCKEVENTS
40 select GENERIC_CLOCKEVENTS_BROADCAST
41 select GENERIC_CPU_AUTOPROBE
42 select GENERIC_EARLY_IOREMAP
43 select GENERIC_IDLE_POLL_SETUP
44 select GENERIC_IRQ_PROBE
45 select GENERIC_IRQ_SHOW
46 select GENERIC_IRQ_SHOW_LEVEL
47 select GENERIC_PCI_IOMAP
48 select GENERIC_SCHED_CLOCK
49 select GENERIC_SMP_IDLE_THREAD
50 select GENERIC_STRNCPY_FROM_USER
51 select GENERIC_STRNLEN_USER
52 select GENERIC_TIME_VSYSCALL
53 select HANDLE_DOMAIN_IRQ
54 select HARDIRQS_SW_RESEND
55 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
56 select HAVE_ARCH_AUDITSYSCALL
57 select HAVE_ARCH_BITREVERSE
58 select HAVE_ARCH_HARDENED_USERCOPY
59 select HAVE_ARCH_HUGE_VMAP
60 select HAVE_ARCH_JUMP_LABEL
61 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
63 select HAVE_ARCH_MMAP_RND_BITS
64 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
65 select HAVE_ARCH_SECCOMP_FILTER
66 select HAVE_ARCH_TRACEHOOK
67 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
70 select HAVE_C_RECORDMCOUNT
71 select HAVE_CC_STACKPROTECTOR
72 select HAVE_CMPXCHG_DOUBLE
73 select HAVE_CMPXCHG_LOCAL
74 select HAVE_CONTEXT_TRACKING
75 select HAVE_DEBUG_BUGVERBOSE
76 select HAVE_DEBUG_KMEMLEAK
77 select HAVE_DMA_API_DEBUG
78 select HAVE_DMA_CONTIGUOUS
79 select HAVE_DYNAMIC_FTRACE
80 select HAVE_EFFICIENT_UNALIGNED_ACCESS
81 select HAVE_FTRACE_MCOUNT_RECORD
82 select HAVE_FUNCTION_TRACER
83 select HAVE_FUNCTION_GRAPH_TRACER
84 select HAVE_GCC_PLUGINS
85 select HAVE_GENERIC_DMA_COHERENT
86 select HAVE_HW_BREAKPOINT if PERF_EVENTS
87 select HAVE_IRQ_TIME_ACCOUNTING
89 select HAVE_MEMBLOCK_NODE_MAP if NUMA
90 select HAVE_PATA_PLATFORM
91 select HAVE_PERF_EVENTS
93 select HAVE_PERF_USER_STACK_DUMP
94 select HAVE_REGS_AND_STACK_ACCESS_API
95 select HAVE_RCU_TABLE_FREE
96 select HAVE_SYSCALL_TRACEPOINTS
98 select HAVE_KRETPROBES if HAVE_KPROBES
99 select IOMMU_DMA if IOMMU_SUPPORT
101 select IRQ_FORCED_THREADING
102 select MODULES_USE_ELF_RELA
105 select OF_EARLY_FLATTREE
106 select OF_RESERVED_MEM
107 select PCI_ECAM if ACPI
111 select SYSCTL_EXCEPTION_TRACE
113 ARM 64-bit (AArch64) Linux support.
118 config ARCH_PHYS_ADDR_T_64BIT
127 config ARM64_PAGE_SHIFT
129 default 16 if ARM64_64K_PAGES
130 default 14 if ARM64_16K_PAGES
133 config ARM64_CONT_SHIFT
135 default 5 if ARM64_64K_PAGES
136 default 7 if ARM64_16K_PAGES
139 config ARCH_MMAP_RND_BITS_MIN
140 default 14 if ARM64_64K_PAGES
141 default 16 if ARM64_16K_PAGES
144 # max bits determined by the following formula:
145 # VA_BITS - PAGE_SHIFT - 3
146 config ARCH_MMAP_RND_BITS_MAX
147 default 19 if ARM64_VA_BITS=36
148 default 24 if ARM64_VA_BITS=39
149 default 27 if ARM64_VA_BITS=42
150 default 30 if ARM64_VA_BITS=47
151 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
152 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
153 default 33 if ARM64_VA_BITS=48
154 default 14 if ARM64_64K_PAGES
155 default 16 if ARM64_16K_PAGES
158 config ARCH_MMAP_RND_COMPAT_BITS_MIN
159 default 7 if ARM64_64K_PAGES
160 default 9 if ARM64_16K_PAGES
163 config ARCH_MMAP_RND_COMPAT_BITS_MAX
169 config STACKTRACE_SUPPORT
172 config ILLEGAL_POINTER_VALUE
174 default 0xdead000000000000
176 config LOCKDEP_SUPPORT
179 config TRACE_IRQFLAGS_SUPPORT
182 config RWSEM_XCHGADD_ALGORITHM
189 config GENERIC_BUG_RELATIVE_POINTERS
191 depends on GENERIC_BUG
193 config GENERIC_HWEIGHT
199 config GENERIC_CALIBRATE_DELAY
205 config HAVE_GENERIC_RCU_GUP
208 config ARCH_DMA_ADDR_T_64BIT
211 config NEED_DMA_MAP_STATE
214 config NEED_SG_DMA_LENGTH
226 config KERNEL_MODE_NEON
229 config FIX_EARLYCON_MEM
232 config PGTABLE_LEVELS
234 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
235 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
236 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
237 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
238 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
239 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
241 source "init/Kconfig"
243 source "kernel/Kconfig.freezer"
245 source "arch/arm64/Kconfig.platforms"
252 This feature enables support for PCI bus system. If you say Y
253 here, the kernel will include drivers and infrastructure code
254 to support PCI bus devices.
259 config PCI_DOMAINS_GENERIC
265 source "drivers/pci/Kconfig"
269 menu "Kernel Features"
271 menu "ARM errata workarounds via the alternatives framework"
273 config ARM64_ERRATUM_826319
274 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
277 This option adds an alternative code sequence to work around ARM
278 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
279 AXI master interface and an L2 cache.
281 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
282 and is unable to accept a certain write via this interface, it will
283 not progress on read data presented on the read data channel and the
286 The workaround promotes data cache clean instructions to
287 data cache clean-and-invalidate.
288 Please note that this does not necessarily enable the workaround,
289 as it depends on the alternative framework, which will only patch
290 the kernel if an affected CPU is detected.
294 config ARM64_ERRATUM_827319
295 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
298 This option adds an alternative code sequence to work around ARM
299 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
300 master interface and an L2 cache.
302 Under certain conditions this erratum can cause a clean line eviction
303 to occur at the same time as another transaction to the same address
304 on the AMBA 5 CHI interface, which can cause data corruption if the
305 interconnect reorders the two transactions.
307 The workaround promotes data cache clean instructions to
308 data cache clean-and-invalidate.
309 Please note that this does not necessarily enable the workaround,
310 as it depends on the alternative framework, which will only patch
311 the kernel if an affected CPU is detected.
315 config ARM64_ERRATUM_824069
316 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
319 This option adds an alternative code sequence to work around ARM
320 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
321 to a coherent interconnect.
323 If a Cortex-A53 processor is executing a store or prefetch for
324 write instruction at the same time as a processor in another
325 cluster is executing a cache maintenance operation to the same
326 address, then this erratum might cause a clean cache line to be
327 incorrectly marked as dirty.
329 The workaround promotes data cache clean instructions to
330 data cache clean-and-invalidate.
331 Please note that this option does not necessarily enable the
332 workaround, as it depends on the alternative framework, which will
333 only patch the kernel if an affected CPU is detected.
337 config ARM64_ERRATUM_819472
338 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
341 This option adds an alternative code sequence to work around ARM
342 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
343 present when it is connected to a coherent interconnect.
345 If the processor is executing a load and store exclusive sequence at
346 the same time as a processor in another cluster is executing a cache
347 maintenance operation to the same address, then this erratum might
348 cause data corruption.
350 The workaround promotes data cache clean instructions to
351 data cache clean-and-invalidate.
352 Please note that this does not necessarily enable the workaround,
353 as it depends on the alternative framework, which will only patch
354 the kernel if an affected CPU is detected.
358 config ARM64_ERRATUM_832075
359 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
362 This option adds an alternative code sequence to work around ARM
363 erratum 832075 on Cortex-A57 parts up to r1p2.
365 Affected Cortex-A57 parts might deadlock when exclusive load/store
366 instructions to Write-Back memory are mixed with Device loads.
368 The workaround is to promote device loads to use Load-Acquire
370 Please note that this does not necessarily enable the workaround,
371 as it depends on the alternative framework, which will only patch
372 the kernel if an affected CPU is detected.
376 config ARM64_ERRATUM_834220
377 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
381 This option adds an alternative code sequence to work around ARM
382 erratum 834220 on Cortex-A57 parts up to r1p2.
384 Affected Cortex-A57 parts might report a Stage 2 translation
385 fault as the result of a Stage 1 fault for load crossing a
386 page boundary when there is a permission or device memory
387 alignment fault at Stage 1 and a translation fault at Stage 2.
389 The workaround is to verify that the Stage 1 translation
390 doesn't generate a fault before handling the Stage 2 fault.
391 Please note that this does not necessarily enable the workaround,
392 as it depends on the alternative framework, which will only patch
393 the kernel if an affected CPU is detected.
397 config ARM64_ERRATUM_845719
398 bool "Cortex-A53: 845719: a load might read incorrect data"
402 This option adds an alternative code sequence to work around ARM
403 erratum 845719 on Cortex-A53 parts up to r0p4.
405 When running a compat (AArch32) userspace on an affected Cortex-A53
406 part, a load at EL0 from a virtual address that matches the bottom 32
407 bits of the virtual address used by a recent load at (AArch64) EL1
408 might return incorrect data.
410 The workaround is to write the contextidr_el1 register on exception
411 return to a 32-bit task.
412 Please note that this does not necessarily enable the workaround,
413 as it depends on the alternative framework, which will only patch
414 the kernel if an affected CPU is detected.
418 config ARM64_ERRATUM_843419
419 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
421 select ARM64_MODULE_CMODEL_LARGE if MODULES
423 This option links the kernel with '--fix-cortex-a53-843419' and
424 builds modules using the large memory model in order to avoid the use
425 of the ADRP instruction, which can cause a subsequent memory access
426 to use an incorrect address on Cortex-A53 parts up to r0p4.
430 config ARM64_ERRATUM_1024718
431 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
434 This option adds work around for Arm Cortex-A55 Erratum 1024718.
436 Affected Cortex-A55 cores (all revisions) could cause incorrect
437 update of the hardware dirty bit when the DBM/AP bits are updated
438 without a break-before-make. The work around is to disable the usage
439 of hardware DBM locally on the affected cores. CPUs not affected by
440 erratum will continue to use the feature.
444 config ARM64_ERRATUM_1188873
445 bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
448 select ARM_ARCH_TIMER_OOL_WORKAROUND
450 This option adds work arounds for ARM Cortex-A76 erratum 1188873
452 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
453 register corruption when accessing the timer registers from
458 config CAVIUM_ERRATUM_22375
459 bool "Cavium erratum 22375, 24313"
462 Enable workaround for erratum 22375, 24313.
464 This implements two gicv3-its errata workarounds for ThunderX. Both
465 with small impact affecting only ITS table allocation.
467 erratum 22375: only alloc 8MB table size
468 erratum 24313: ignore memory access type
470 The fixes are in ITS initialization and basically ignore memory access
471 type and table size provided by the TYPER and BASER registers.
475 config CAVIUM_ERRATUM_23144
476 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
480 ITS SYNC command hang for cross node io and collections/cpu mapping.
484 config CAVIUM_ERRATUM_23154
485 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
488 The gicv3 of ThunderX requires a modified version for
489 reading the IAR status to ensure data synchronization
490 (access to icc_iar1_el1 is not sync'ed before and after).
494 config CAVIUM_ERRATUM_27456
495 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
498 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
499 instructions may cause the icache to become corrupted if it
500 contains data for a non-current ASID. The fix is to
501 invalidate the icache when changing the mm context.
505 config QCOM_QDF2400_ERRATUM_0065
506 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
509 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
510 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
511 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
520 default ARM64_4K_PAGES
522 Page size (translation granule) configuration.
524 config ARM64_4K_PAGES
527 This feature enables 4KB pages support.
529 config ARM64_16K_PAGES
532 The system will use 16KB pages support. AArch32 emulation
533 requires applications compiled with 16K (or a multiple of 16K)
536 config ARM64_64K_PAGES
539 This feature enables 64KB pages support (4KB by default)
540 allowing only two levels of page tables and faster TLB
541 look-up. AArch32 emulation requires applications compiled
542 with 64K aligned segments.
547 prompt "Virtual address space size"
548 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
549 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
550 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
552 Allows choosing one of multiple possible virtual address
553 space sizes. The level of translation table is determined by
554 a combination of page size and virtual address space size.
556 config ARM64_VA_BITS_36
557 bool "36-bit" if EXPERT
558 depends on ARM64_16K_PAGES
560 config ARM64_VA_BITS_39
562 depends on ARM64_4K_PAGES
564 config ARM64_VA_BITS_42
566 depends on ARM64_64K_PAGES
568 config ARM64_VA_BITS_47
570 depends on ARM64_16K_PAGES
572 config ARM64_VA_BITS_48
579 default 36 if ARM64_VA_BITS_36
580 default 39 if ARM64_VA_BITS_39
581 default 42 if ARM64_VA_BITS_42
582 default 47 if ARM64_VA_BITS_47
583 default 48 if ARM64_VA_BITS_48
585 config CPU_BIG_ENDIAN
586 bool "Build big-endian kernel"
588 Say Y if you plan on running a kernel in big-endian mode.
591 bool "Multi-core scheduler support"
593 Multi-core scheduler support improves the CPU scheduler's decision
594 making when dealing with multi-core CPU chips at a cost of slightly
595 increased overhead in some places. If unsure say N here.
598 bool "SMT scheduler support"
600 Improves the CPU scheduler's decision making when dealing with
601 MultiThreading at a cost of slightly increased overhead in some
602 places. If unsure say N here.
605 int "Maximum number of CPUs (2-4096)"
607 # These have to remain sorted largest to smallest
611 bool "Support for hot-pluggable CPUs"
612 select GENERIC_IRQ_MIGRATION
614 Say Y here to experiment with turning CPUs off and on. CPUs
615 can be controlled through /sys/devices/system/cpu.
617 # Common NUMA Features
619 bool "Numa Memory Allocation and Scheduler Support"
620 select ACPI_NUMA if ACPI
623 Enable NUMA (Non Uniform Memory Access) support.
625 The kernel will try to allocate memory used by a CPU on the
626 local memory of the CPU and add some more
627 NUMA awareness to the kernel.
630 int "Maximum NUMA Nodes (as a power of 2)"
633 depends on NEED_MULTIPLE_NODES
635 Specify the maximum number of NUMA Nodes available on the target
636 system. Increases memory reserved to accommodate various tables.
638 config USE_PERCPU_NUMA_NODE_ID
642 config HAVE_SETUP_PER_CPU_AREA
646 config NEED_PER_CPU_EMBED_FIRST_CHUNK
650 source kernel/Kconfig.preempt
651 source kernel/Kconfig.hz
653 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
656 config ARCH_HAS_HOLES_MEMORYMODEL
657 def_bool y if SPARSEMEM
659 config ARCH_SPARSEMEM_ENABLE
661 select SPARSEMEM_VMEMMAP_ENABLE
663 config ARCH_SPARSEMEM_DEFAULT
664 def_bool ARCH_SPARSEMEM_ENABLE
666 config ARCH_SELECT_MEMORY_MODEL
667 def_bool ARCH_SPARSEMEM_ENABLE
669 config HAVE_ARCH_PFN_VALID
670 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
672 config HW_PERF_EVENTS
676 config SYS_SUPPORTS_HUGETLBFS
679 config ARCH_WANT_HUGE_PMD_SHARE
680 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
682 config ARCH_HAS_CACHE_LINE_SIZE
688 bool "Enable seccomp to safely compute untrusted bytecode"
690 This kernel feature is useful for number crunching applications
691 that may need to compute untrusted bytecode during their
692 execution. By using pipes or other transports made available to
693 the process as file descriptors supporting the read/write
694 syscalls, it's possible to isolate those applications in
695 their own address space using seccomp. Once seccomp is
696 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
697 and the task is only allowed to execute a few safe syscalls
698 defined by each seccomp mode.
701 bool "Enable paravirtualization code"
703 This changes the kernel so it can modify itself when it is run
704 under a hypervisor, potentially improving performance significantly
705 over full virtualization.
707 config PARAVIRT_TIME_ACCOUNTING
708 bool "Paravirtual steal time accounting"
712 Select this option to enable fine granularity task steal time
713 accounting. Time spent executing other tasks in parallel with
714 the current vCPU is discounted from the vCPU power. To account for
715 that, there can be a small performance impact.
717 If in doubt, say N here.
720 depends on PM_SLEEP_SMP
722 bool "kexec system call"
724 kexec is a system call that implements the ability to shutdown your
725 current kernel, and to start another kernel. It is like a reboot
726 but it is independent of the system firmware. And like a reboot
727 you can start any kernel with it, not just Linux.
734 bool "Xen guest support on ARM64"
735 depends on ARM64 && OF
739 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
741 config FORCE_MAX_ZONEORDER
743 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
744 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
747 The kernel memory allocator divides physically contiguous memory
748 blocks into "zones", where each zone is a power of two number of
749 pages. This option selects the largest power of two that the kernel
750 keeps in the memory allocator. If you need to allocate very large
751 blocks of physically contiguous memory, then you may need to
754 This config option is actually maximum order plus one. For example,
755 a value of 11 means that the largest free memory block is 2^10 pages.
757 We make sure that we can allocate upto a HugePage size for each configuration.
759 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
761 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
762 4M allocations matching the default size used by generic code.
764 config UNMAP_KERNEL_AT_EL0
765 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
768 Speculation attacks against some high-performance processors can
769 be used to bypass MMU permission checks and leak kernel data to
770 userspace. This can be defended against by unmapping the kernel
771 when running in userspace, mapping it back in on exception entry
772 via a trampoline page in the vector table.
776 config HARDEN_BRANCH_PREDICTOR
777 bool "Harden the branch predictor against aliasing attacks" if EXPERT
780 Speculation attacks against some high-performance processors rely on
781 being able to manipulate the branch predictor for a victim context by
782 executing aliasing branches in the attacker context. Such attacks
783 can be partially mitigated against by clearing internal branch
784 predictor state and limiting the prediction logic in some situations.
786 This config option will take CPU-specific actions to harden the
787 branch predictor against aliasing attacks and may rely on specific
788 instruction sequences or control bits being set by the system
794 bool "Speculative Store Bypass Disable" if EXPERT
797 This enables mitigation of the bypassing of previous stores
798 by speculative loads.
802 config MITIGATE_SPECTRE_BRANCH_HISTORY
803 bool "Mitigate Spectre style attacks against branch history" if EXPERT
805 depends on HARDEN_BRANCH_PREDICTOR || !KVM
807 Speculation attacks against some high-performance processors can
808 make use of branch history to influence future speculation.
809 When taking an exception from user-space, a sequence of branches
810 or a firmware call overwrites the branch history.
812 menuconfig ARMV8_DEPRECATED
813 bool "Emulate deprecated/obsolete ARMv8 instructions"
816 Legacy software support may require certain instructions
817 that have been deprecated or obsoleted in the architecture.
819 Enable this config to enable selective emulation of these
827 bool "Emulate SWP/SWPB instructions"
829 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
830 they are always undefined. Say Y here to enable software
831 emulation of these instructions for userspace using LDXR/STXR.
833 In some older versions of glibc [<=2.8] SWP is used during futex
834 trylock() operations with the assumption that the code will not
835 be preempted. This invalid assumption may be more likely to fail
836 with SWP emulation enabled, leading to deadlock of the user
839 NOTE: when accessing uncached shared regions, LDXR/STXR rely
840 on an external transaction monitoring block called a global
841 monitor to maintain update atomicity. If your system does not
842 implement a global monitor, this option can cause programs that
843 perform SWP operations to uncached memory to deadlock.
847 config CP15_BARRIER_EMULATION
848 bool "Emulate CP15 Barrier instructions"
850 The CP15 barrier instructions - CP15ISB, CP15DSB, and
851 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
852 strongly recommended to use the ISB, DSB, and DMB
853 instructions instead.
855 Say Y here to enable software emulation of these
856 instructions for AArch32 userspace code. When this option is
857 enabled, CP15 barrier usage is traced which can help
858 identify software that needs updating.
862 config SETEND_EMULATION
863 bool "Emulate SETEND instruction"
865 The SETEND instruction alters the data-endianness of the
866 AArch32 EL0, and is deprecated in ARMv8.
868 Say Y here to enable software emulation of the instruction
869 for AArch32 userspace code.
871 Note: All the cpus on the system must have mixed endian support at EL0
872 for this feature to be enabled. If a new CPU - which doesn't support mixed
873 endian - is hotplugged in after this feature has been enabled, there could
874 be unexpected results in the applications.
879 menu "ARMv8.1 architectural features"
881 config ARM64_HW_AFDBM
882 bool "Support for hardware updates of the Access and Dirty page flags"
885 The ARMv8.1 architecture extensions introduce support for
886 hardware updates of the access and dirty information in page
887 table entries. When enabled in TCR_EL1 (HA and HD bits) on
888 capable processors, accesses to pages with PTE_AF cleared will
889 set this bit instead of raising an access flag fault.
890 Similarly, writes to read-only pages with the DBM bit set will
891 clear the read-only bit (AP[2]) instead of raising a
894 Kernels built with this configuration option enabled continue
895 to work on pre-ARMv8.1 hardware and the performance impact is
896 minimal. If unsure, say Y.
899 bool "Enable support for Privileged Access Never (PAN)"
902 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
903 prevents the kernel or hypervisor from accessing user-space (EL0)
906 Choosing this option will cause any unprotected (not using
907 copy_to_user et al) memory access to fail with a permission fault.
909 The feature is detected at runtime, and will remain as a 'nop'
910 instruction if the cpu does not implement the feature.
912 config ARM64_LSE_ATOMICS
913 bool "Atomic instructions"
915 As part of the Large System Extensions, ARMv8.1 introduces new
916 atomic instructions that are designed specifically to scale in
919 Say Y here to make use of these instructions for the in-kernel
920 atomic routines. This incurs a small overhead on CPUs that do
921 not support these instructions and requires the kernel to be
922 built with binutils >= 2.25.
925 bool "Enable support for Virtualization Host Extensions (VHE)"
928 Virtualization Host Extensions (VHE) allow the kernel to run
929 directly at EL2 (instead of EL1) on processors that support
930 it. This leads to better performance for KVM, as they reduce
931 the cost of the world switch.
933 Selecting this option allows the VHE feature to be detected
934 at runtime, and does not affect processors that do not
935 implement this feature.
939 menu "ARMv8.2 architectural features"
942 bool "Enable support for User Access Override (UAO)"
945 User Access Override (UAO; part of the ARMv8.2 Extensions)
946 causes the 'unprivileged' variant of the load/store instructions to
947 be overriden to be privileged.
949 This option changes get_user() and friends to use the 'unprivileged'
950 variant of the load/store instructions. This ensures that user-space
951 really did have access to the supplied memory. When addr_limit is
952 set to kernel memory the UAO bit will be set, allowing privileged
953 access to kernel memory.
955 Choosing this option will cause copy_to_user() et al to use user-space
958 The feature is detected at runtime, the kernel will use the
959 regular load/store instructions if the cpu does not implement the
964 config ARM64_MODULE_CMODEL_LARGE
967 config ARM64_MODULE_PLTS
969 select ARM64_MODULE_CMODEL_LARGE
970 select HAVE_MOD_ARCH_SPECIFIC
975 This builds the kernel as a Position Independent Executable (PIE),
976 which retains all relocation metadata required to relocate the
977 kernel binary at runtime to a different virtual address than the
978 address it was linked at.
979 Since AArch64 uses the RELA relocation format, this requires a
980 relocation pass at runtime even if the kernel is loaded at the
981 same address it was linked at.
983 config RANDOMIZE_BASE
984 bool "Randomize the address of the kernel image"
985 select ARM64_MODULE_PLTS if MODULES
988 Randomizes the virtual address at which the kernel image is
989 loaded, as a security feature that deters exploit attempts
990 relying on knowledge of the location of kernel internals.
992 It is the bootloader's job to provide entropy, by passing a
993 random u64 value in /chosen/kaslr-seed at kernel entry.
995 When booting via the UEFI stub, it will invoke the firmware's
996 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
997 to the kernel proper. In addition, it will randomise the physical
998 location of the kernel Image as well.
1002 config RANDOMIZE_MODULE_REGION_FULL
1003 bool "Randomize the module region independently from the core kernel"
1004 depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE
1007 Randomizes the location of the module region without considering the
1008 location of the core kernel. This way, it is impossible for modules
1009 to leak information about the location of core kernel data structures
1010 but it does imply that function calls between modules and the core
1011 kernel will need to be resolved via veneers in the module PLT.
1013 When this option is not set, the module region will be randomized over
1014 a limited range that contains the [_stext, _etext] interval of the
1015 core kernel, so branch relocations are always in range.
1021 config ARM64_ACPI_PARKING_PROTOCOL
1022 bool "Enable support for the ARM64 ACPI parking protocol"
1025 Enable support for the ARM64 ACPI parking protocol. If disabled
1026 the kernel will not allow booting through the ARM64 ACPI parking
1027 protocol even if the corresponding data is present in the ACPI
1031 string "Default kernel command string"
1034 Provide a set of default command-line options at build time by
1035 entering them here. As a minimum, you should specify the the
1036 root device (e.g. root=/dev/nfs).
1038 config CMDLINE_FORCE
1039 bool "Always use the default kernel command string"
1041 Always use the default kernel command string, even if the boot
1042 loader passes other arguments to the kernel.
1043 This is useful if you cannot or don't want to change the
1044 command-line options your boot loader passes to the kernel.
1050 bool "UEFI runtime support"
1051 depends on OF && !CPU_BIG_ENDIAN
1054 select EFI_PARAMS_FROM_FDT
1055 select EFI_RUNTIME_WRAPPERS
1060 This option provides support for runtime services provided
1061 by UEFI firmware (such as non-volatile variables, realtime
1062 clock, and platform reset). A UEFI stub is also provided to
1063 allow the kernel to be booted as an EFI application. This
1064 is only useful on systems that have UEFI firmware.
1067 bool "Enable support for SMBIOS (DMI) tables"
1071 This enables SMBIOS/DMI feature for systems.
1073 This option is only useful on systems that have UEFI firmware.
1074 However, even with this option, the resultant kernel should
1075 continue to boot on existing non-UEFI platforms.
1079 menu "Userspace binary formats"
1081 source "fs/Kconfig.binfmt"
1084 bool "Kernel support for 32-bit EL0"
1085 depends on ARM64_4K_PAGES || EXPERT
1086 select COMPAT_BINFMT_ELF if BINFMT_ELF
1088 select OLD_SIGSUSPEND3
1089 select COMPAT_OLD_SIGACTION
1091 This option enables support for a 32-bit EL0 running under a 64-bit
1092 kernel at EL1. AArch32-specific components such as system calls,
1093 the user helper functions, VFP support and the ptrace interface are
1094 handled appropriately by the kernel.
1096 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1097 that you will only be able to execute AArch32 binaries that were compiled
1098 with page size aligned segments.
1100 If you want to execute 32-bit userspace applications, say Y.
1102 config SYSVIPC_COMPAT
1104 depends on COMPAT && SYSVIPC
1108 depends on COMPAT && KEYS
1112 menu "Power management options"
1114 source "kernel/power/Kconfig"
1116 config ARCH_HIBERNATION_POSSIBLE
1120 config ARCH_HIBERNATION_HEADER
1122 depends on HIBERNATION
1124 config ARCH_SUSPEND_POSSIBLE
1129 menu "CPU Power Management"
1131 source "drivers/cpuidle/Kconfig"
1133 source "drivers/cpufreq/Kconfig"
1137 source "net/Kconfig"
1139 source "drivers/Kconfig"
1141 source "drivers/firmware/Kconfig"
1143 source "drivers/acpi/Kconfig"
1147 source "arch/arm64/kvm/Kconfig"
1149 source "arch/arm64/Kconfig.debug"
1151 source "security/Kconfig"
1153 source "crypto/Kconfig"
1155 source "arch/arm64/crypto/Kconfig"
1158 source "lib/Kconfig"