1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_HAS_DEBUG_VIRTUAL
15 select ARCH_HAS_DEBUG_VM_PGTABLE
16 select ARCH_HAS_DEVMEM_IS_ALLOWED
17 select ARCH_HAS_DMA_PREP_COHERENT
18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19 select ARCH_HAS_FAST_MULTIPLIER
20 select ARCH_HAS_FORTIFY_SOURCE
21 select ARCH_HAS_GCOV_PROFILE_ALL
22 select ARCH_HAS_GIGANTIC_PAGE
24 select ARCH_HAS_KEEPINITRD
25 select ARCH_HAS_MEMBARRIER_SYNC_CORE
26 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
27 select ARCH_HAS_PTE_DEVMAP
28 select ARCH_HAS_PTE_SPECIAL
29 select ARCH_HAS_SETUP_DMA_OPS
30 select ARCH_HAS_SET_DIRECT_MAP
31 select ARCH_HAS_SET_MEMORY
33 select ARCH_HAS_STRICT_KERNEL_RWX
34 select ARCH_HAS_STRICT_MODULE_RWX
35 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
36 select ARCH_HAS_SYNC_DMA_FOR_CPU
37 select ARCH_HAS_SYSCALL_WRAPPER
38 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
39 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
40 select ARCH_HAVE_ELF_PROT
41 select ARCH_HAVE_NMI_SAFE_CMPXCHG
42 select ARCH_INLINE_READ_LOCK if !PREEMPTION
43 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
44 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
45 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
46 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
47 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
48 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
49 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
50 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
51 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
52 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
53 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
54 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
55 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
56 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
58 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
59 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
61 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
62 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
64 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
65 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
67 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
68 select ARCH_KEEP_MEMBLOCK
69 select ARCH_USE_CMPXCHG_LOCKREF
70 select ARCH_USE_GNU_PROPERTY
71 select ARCH_USE_QUEUED_RWLOCKS
72 select ARCH_USE_QUEUED_SPINLOCKS
73 select ARCH_USE_SYM_ANNOTATIONS
74 select ARCH_SUPPORTS_MEMORY_FAILURE
75 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
76 select ARCH_SUPPORTS_ATOMIC_RMW
77 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
78 select ARCH_SUPPORTS_NUMA_BALANCING
79 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
80 select ARCH_WANT_DEFAULT_BPF_JIT
81 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
82 select ARCH_WANT_FRAME_POINTERS
83 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
84 select ARCH_WANT_LD_ORPHAN_WARN
85 select ARCH_HAS_UBSAN_SANITIZE_ALL
89 select AUDIT_ARCH_COMPAT_GENERIC
90 select ARM_GIC_V2M if PCI
92 select ARM_GIC_V3_ITS if PCI
94 select BUILDTIME_TABLE_SORT
95 select CLONE_BACKWARDS
97 select CPU_PM if (SUSPEND || CPU_IDLE)
99 select DCACHE_WORD_ACCESS
100 select DMA_DIRECT_REMAP
103 select GENERIC_ALLOCATOR
104 select GENERIC_ARCH_TOPOLOGY
105 select GENERIC_CLOCKEVENTS
106 select GENERIC_CLOCKEVENTS_BROADCAST
107 select GENERIC_CPU_AUTOPROBE
108 select GENERIC_CPU_VULNERABILITIES
109 select GENERIC_EARLY_IOREMAP
110 select GENERIC_IDLE_POLL_SETUP
111 select GENERIC_IRQ_IPI
112 select GENERIC_IRQ_MULTI_HANDLER
113 select GENERIC_IRQ_PROBE
114 select GENERIC_IRQ_SHOW
115 select GENERIC_IRQ_SHOW_LEVEL
116 select GENERIC_PCI_IOMAP
117 select GENERIC_PTDUMP
118 select GENERIC_SCHED_CLOCK
119 select GENERIC_SMP_IDLE_THREAD
120 select GENERIC_STRNCPY_FROM_USER
121 select GENERIC_STRNLEN_USER
122 select GENERIC_TIME_VSYSCALL
123 select GENERIC_GETTIMEOFDAY
124 select GENERIC_VDSO_TIME_NS
125 select HANDLE_DOMAIN_IRQ
126 select HARDIRQS_SW_RESEND
129 select HAVE_ACPI_APEI if (ACPI && EFI)
130 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
131 select HAVE_ARCH_AUDITSYSCALL
132 select HAVE_ARCH_BITREVERSE
133 select HAVE_ARCH_COMPILER_H
134 select HAVE_ARCH_HUGE_VMAP
135 select HAVE_ARCH_JUMP_LABEL
136 select HAVE_ARCH_JUMP_LABEL_RELATIVE
137 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
138 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
139 select HAVE_ARCH_KGDB
140 select HAVE_ARCH_MMAP_RND_BITS
141 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
142 select HAVE_ARCH_PREL32_RELOCATIONS
143 select HAVE_ARCH_SECCOMP_FILTER
144 select HAVE_ARCH_STACKLEAK
145 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
146 select HAVE_ARCH_TRACEHOOK
147 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
148 select HAVE_ARCH_VMAP_STACK
149 select HAVE_ARM_SMCCC
150 select HAVE_ASM_MODVERSIONS
152 select HAVE_C_RECORDMCOUNT
153 select HAVE_CMPXCHG_DOUBLE
154 select HAVE_CMPXCHG_LOCAL
155 select HAVE_CONTEXT_TRACKING
156 select HAVE_DEBUG_BUGVERBOSE
157 select HAVE_DEBUG_KMEMLEAK
158 select HAVE_DMA_CONTIGUOUS
159 select HAVE_DYNAMIC_FTRACE
160 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
161 if $(cc-option,-fpatchable-function-entry=2)
162 select HAVE_EFFICIENT_UNALIGNED_ACCESS
164 select HAVE_FTRACE_MCOUNT_RECORD
165 select HAVE_FUNCTION_TRACER
166 select HAVE_FUNCTION_ERROR_INJECTION
167 select HAVE_FUNCTION_GRAPH_TRACER
168 select HAVE_GCC_PLUGINS
169 select HAVE_HW_BREAKPOINT if PERF_EVENTS
170 select HAVE_IRQ_TIME_ACCOUNTING
172 select HAVE_PATA_PLATFORM
173 select HAVE_PERF_EVENTS
174 select HAVE_PERF_REGS
175 select HAVE_PERF_USER_STACK_DUMP
176 select HAVE_REGS_AND_STACK_ACCESS_API
177 select HAVE_FUNCTION_ARG_ACCESS_API
178 select HAVE_FUTEX_CMPXCHG if FUTEX
179 select MMU_GATHER_RCU_TABLE_FREE
181 select HAVE_STACKPROTECTOR
182 select HAVE_SYSCALL_TRACEPOINTS
184 select HAVE_KRETPROBES
185 select HAVE_GENERIC_VDSO
186 select IOMMU_DMA if IOMMU_SUPPORT
188 select IRQ_FORCED_THREADING
189 select MODULES_USE_ELF_RELA
190 select NEED_DMA_MAP_STATE
191 select NEED_SG_DMA_LENGTH
193 select OF_EARLY_FLATTREE
194 select PCI_DOMAINS_GENERIC if PCI
195 select PCI_ECAM if (ACPI && PCI)
196 select PCI_SYSCALL if PCI
202 select SYSCTL_EXCEPTION_TRACE
203 select THREAD_INFO_IN_TASK
205 ARM 64-bit (AArch64) Linux support.
213 config ARM64_PAGE_SHIFT
215 default 16 if ARM64_64K_PAGES
216 default 14 if ARM64_16K_PAGES
219 config ARM64_CONT_PTE_SHIFT
221 default 5 if ARM64_64K_PAGES
222 default 7 if ARM64_16K_PAGES
225 config ARM64_CONT_PMD_SHIFT
227 default 5 if ARM64_64K_PAGES
228 default 5 if ARM64_16K_PAGES
231 config ARCH_MMAP_RND_BITS_MIN
232 default 14 if ARM64_64K_PAGES
233 default 16 if ARM64_16K_PAGES
236 # max bits determined by the following formula:
237 # VA_BITS - PAGE_SHIFT - 3
238 config ARCH_MMAP_RND_BITS_MAX
239 default 19 if ARM64_VA_BITS=36
240 default 24 if ARM64_VA_BITS=39
241 default 27 if ARM64_VA_BITS=42
242 default 30 if ARM64_VA_BITS=47
243 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
244 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
245 default 33 if ARM64_VA_BITS=48
246 default 14 if ARM64_64K_PAGES
247 default 16 if ARM64_16K_PAGES
250 config ARCH_MMAP_RND_COMPAT_BITS_MIN
251 default 7 if ARM64_64K_PAGES
252 default 9 if ARM64_16K_PAGES
255 config ARCH_MMAP_RND_COMPAT_BITS_MAX
261 config STACKTRACE_SUPPORT
264 config ILLEGAL_POINTER_VALUE
266 default 0xdead000000000000
268 config LOCKDEP_SUPPORT
271 config TRACE_IRQFLAGS_SUPPORT
278 config GENERIC_BUG_RELATIVE_POINTERS
280 depends on GENERIC_BUG
282 config GENERIC_HWEIGHT
288 config GENERIC_CALIBRATE_DELAY
292 bool "Support DMA zone" if EXPERT
296 bool "Support DMA32 zone" if EXPERT
299 config ARCH_ENABLE_MEMORY_HOTPLUG
302 config ARCH_ENABLE_MEMORY_HOTREMOVE
308 config KERNEL_MODE_NEON
311 config FIX_EARLYCON_MEM
314 config PGTABLE_LEVELS
316 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
317 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
318 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
319 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
320 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
321 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
323 config ARCH_SUPPORTS_UPROBES
326 config ARCH_PROC_KCORE_TEXT
329 config BROKEN_GAS_INST
330 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
332 config KASAN_SHADOW_OFFSET
335 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
336 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
337 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
338 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
339 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
340 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
341 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
342 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
343 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
344 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
345 default 0xffffffffffffffff
347 source "arch/arm64/Kconfig.platforms"
349 menu "Kernel Features"
351 menu "ARM errata workarounds via the alternatives framework"
353 config ARM64_WORKAROUND_CLEAN_CACHE
356 config ARM64_ERRATUM_826319
357 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
359 select ARM64_WORKAROUND_CLEAN_CACHE
361 This option adds an alternative code sequence to work around ARM
362 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
363 AXI master interface and an L2 cache.
365 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
366 and is unable to accept a certain write via this interface, it will
367 not progress on read data presented on the read data channel and the
370 The workaround promotes data cache clean instructions to
371 data cache clean-and-invalidate.
372 Please note that this does not necessarily enable the workaround,
373 as it depends on the alternative framework, which will only patch
374 the kernel if an affected CPU is detected.
378 config ARM64_ERRATUM_827319
379 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
381 select ARM64_WORKAROUND_CLEAN_CACHE
383 This option adds an alternative code sequence to work around ARM
384 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
385 master interface and an L2 cache.
387 Under certain conditions this erratum can cause a clean line eviction
388 to occur at the same time as another transaction to the same address
389 on the AMBA 5 CHI interface, which can cause data corruption if the
390 interconnect reorders the two transactions.
392 The workaround promotes data cache clean instructions to
393 data cache clean-and-invalidate.
394 Please note that this does not necessarily enable the workaround,
395 as it depends on the alternative framework, which will only patch
396 the kernel if an affected CPU is detected.
400 config ARM64_ERRATUM_824069
401 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
403 select ARM64_WORKAROUND_CLEAN_CACHE
405 This option adds an alternative code sequence to work around ARM
406 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
407 to a coherent interconnect.
409 If a Cortex-A53 processor is executing a store or prefetch for
410 write instruction at the same time as a processor in another
411 cluster is executing a cache maintenance operation to the same
412 address, then this erratum might cause a clean cache line to be
413 incorrectly marked as dirty.
415 The workaround promotes data cache clean instructions to
416 data cache clean-and-invalidate.
417 Please note that this option does not necessarily enable the
418 workaround, as it depends on the alternative framework, which will
419 only patch the kernel if an affected CPU is detected.
423 config ARM64_ERRATUM_819472
424 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
426 select ARM64_WORKAROUND_CLEAN_CACHE
428 This option adds an alternative code sequence to work around ARM
429 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
430 present when it is connected to a coherent interconnect.
432 If the processor is executing a load and store exclusive sequence at
433 the same time as a processor in another cluster is executing a cache
434 maintenance operation to the same address, then this erratum might
435 cause data corruption.
437 The workaround promotes data cache clean instructions to
438 data cache clean-and-invalidate.
439 Please note that this does not necessarily enable the workaround,
440 as it depends on the alternative framework, which will only patch
441 the kernel if an affected CPU is detected.
445 config ARM64_ERRATUM_832075
446 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
449 This option adds an alternative code sequence to work around ARM
450 erratum 832075 on Cortex-A57 parts up to r1p2.
452 Affected Cortex-A57 parts might deadlock when exclusive load/store
453 instructions to Write-Back memory are mixed with Device loads.
455 The workaround is to promote device loads to use Load-Acquire
457 Please note that this does not necessarily enable the workaround,
458 as it depends on the alternative framework, which will only patch
459 the kernel if an affected CPU is detected.
463 config ARM64_ERRATUM_834220
464 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
468 This option adds an alternative code sequence to work around ARM
469 erratum 834220 on Cortex-A57 parts up to r1p2.
471 Affected Cortex-A57 parts might report a Stage 2 translation
472 fault as the result of a Stage 1 fault for load crossing a
473 page boundary when there is a permission or device memory
474 alignment fault at Stage 1 and a translation fault at Stage 2.
476 The workaround is to verify that the Stage 1 translation
477 doesn't generate a fault before handling the Stage 2 fault.
478 Please note that this does not necessarily enable the workaround,
479 as it depends on the alternative framework, which will only patch
480 the kernel if an affected CPU is detected.
484 config ARM64_ERRATUM_1742098
485 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
489 This option removes the AES hwcap for aarch32 user-space to
490 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
492 Affected parts may corrupt the AES state if an interrupt is
493 taken between a pair of AES instructions. These instructions
494 are only present if the cryptography extensions are present.
495 All software should have a fallback implementation for CPUs
496 that don't implement the cryptography extensions.
500 config ARM64_ERRATUM_845719
501 bool "Cortex-A53: 845719: a load might read incorrect data"
505 This option adds an alternative code sequence to work around ARM
506 erratum 845719 on Cortex-A53 parts up to r0p4.
508 When running a compat (AArch32) userspace on an affected Cortex-A53
509 part, a load at EL0 from a virtual address that matches the bottom 32
510 bits of the virtual address used by a recent load at (AArch64) EL1
511 might return incorrect data.
513 The workaround is to write the contextidr_el1 register on exception
514 return to a 32-bit task.
515 Please note that this does not necessarily enable the workaround,
516 as it depends on the alternative framework, which will only patch
517 the kernel if an affected CPU is detected.
521 config ARM64_ERRATUM_843419
522 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
524 select ARM64_MODULE_PLTS if MODULES
526 This option links the kernel with '--fix-cortex-a53-843419' and
527 enables PLT support to replace certain ADRP instructions, which can
528 cause subsequent memory accesses to use an incorrect address on
529 Cortex-A53 parts up to r0p4.
533 config ARM64_ERRATUM_1024718
534 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
537 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
539 Affected Cortex-A55 cores (all revisions) could cause incorrect
540 update of the hardware dirty bit when the DBM/AP bits are updated
541 without a break-before-make. The workaround is to disable the usage
542 of hardware DBM locally on the affected cores. CPUs not affected by
543 this erratum will continue to use the feature.
547 config ARM64_ERRATUM_1418040
548 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
552 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
553 errata 1188873 and 1418040.
555 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
556 cause register corruption when accessing the timer registers
557 from AArch32 userspace.
561 config ARM64_WORKAROUND_SPECULATIVE_AT
564 config ARM64_ERRATUM_1165522
565 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
567 select ARM64_WORKAROUND_SPECULATIVE_AT
569 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
571 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
572 corrupted TLBs by speculating an AT instruction during a guest
577 config ARM64_ERRATUM_1319367
578 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
580 select ARM64_WORKAROUND_SPECULATIVE_AT
582 This option adds work arounds for ARM Cortex-A57 erratum 1319537
583 and A72 erratum 1319367
585 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
586 speculating an AT instruction during a guest context switch.
590 config ARM64_ERRATUM_1530923
591 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
593 select ARM64_WORKAROUND_SPECULATIVE_AT
595 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
597 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
598 corrupted TLBs by speculating an AT instruction during a guest
603 config ARM64_WORKAROUND_REPEAT_TLBI
606 config ARM64_ERRATUM_1286807
607 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
609 select ARM64_WORKAROUND_REPEAT_TLBI
611 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
613 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
614 address for a cacheable mapping of a location is being
615 accessed by a core while another core is remapping the virtual
616 address to a new physical page using the recommended
617 break-before-make sequence, then under very rare circumstances
618 TLBI+DSB completes before a read using the translation being
619 invalidated has been observed by other observers. The
620 workaround repeats the TLBI+DSB operation.
622 config ARM64_ERRATUM_1463225
623 bool "Cortex-A76: Software Step might prevent interrupt recognition"
626 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
628 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
629 of a system call instruction (SVC) can prevent recognition of
630 subsequent interrupts when software stepping is disabled in the
631 exception handler of the system call and either kernel debugging
632 is enabled or VHE is in use.
634 Work around the erratum by triggering a dummy step exception
635 when handling a system call from a task that is being stepped
636 in a VHE configuration of the kernel.
640 config ARM64_ERRATUM_1542419
641 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
644 This option adds a workaround for ARM Neoverse-N1 erratum
647 Affected Neoverse-N1 cores could execute a stale instruction when
648 modified by another CPU. The workaround depends on a firmware
651 Workaround the issue by hiding the DIC feature from EL0. This
652 forces user-space to perform cache maintenance.
656 config ARM64_ERRATUM_1508412
657 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
660 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
662 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
663 of a store-exclusive or read of PAR_EL1 and a load with device or
664 non-cacheable memory attributes. The workaround depends on a firmware
667 KVM guests must also have the workaround implemented or they can
670 Work around the issue by inserting DMB SY barriers around PAR_EL1
671 register reads and warning KVM users. The DMB barrier is sufficient
672 to prevent a speculative PAR_EL1 read.
676 config ARM64_ERRATUM_2457168
677 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
678 depends on ARM64_AMU_EXTN
681 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
683 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
684 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
685 incorrectly giving a significantly higher output value.
687 Work around this problem by keeping the reference values of affected counters
688 to 0 thus signaling an error case. This effect is the same to firmware disabling
689 affected counters, in which case 0 will be returned when reading the disabled
694 config CAVIUM_ERRATUM_22375
695 bool "Cavium erratum 22375, 24313"
698 Enable workaround for errata 22375 and 24313.
700 This implements two gicv3-its errata workarounds for ThunderX. Both
701 with a small impact affecting only ITS table allocation.
703 erratum 22375: only alloc 8MB table size
704 erratum 24313: ignore memory access type
706 The fixes are in ITS initialization and basically ignore memory access
707 type and table size provided by the TYPER and BASER registers.
711 config CAVIUM_ERRATUM_23144
712 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
716 ITS SYNC command hang for cross node io and collections/cpu mapping.
720 config CAVIUM_ERRATUM_23154
721 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
724 The gicv3 of ThunderX requires a modified version for
725 reading the IAR status to ensure data synchronization
726 (access to icc_iar1_el1 is not sync'ed before and after).
730 config CAVIUM_ERRATUM_27456
731 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
734 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
735 instructions may cause the icache to become corrupted if it
736 contains data for a non-current ASID. The fix is to
737 invalidate the icache when changing the mm context.
741 config CAVIUM_ERRATUM_30115
742 bool "Cavium erratum 30115: Guest may disable interrupts in host"
745 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
746 1.2, and T83 Pass 1.0, KVM guest execution may disable
747 interrupts in host. Trapping both GICv3 group-0 and group-1
748 accesses sidesteps the issue.
752 config CAVIUM_TX2_ERRATUM_219
753 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
756 On Cavium ThunderX2, a load, store or prefetch instruction between a
757 TTBR update and the corresponding context synchronizing operation can
758 cause a spurious Data Abort to be delivered to any hardware thread in
761 Work around the issue by avoiding the problematic code sequence and
762 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
763 trap handler performs the corresponding register access, skips the
764 instruction and ensures context synchronization by virtue of the
769 config FUJITSU_ERRATUM_010001
770 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
773 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
774 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
775 accesses may cause undefined fault (Data abort, DFSC=0b111111).
776 This fault occurs under a specific hardware condition when a
777 load/store instruction performs an address translation using:
778 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
779 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
780 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
781 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
783 The workaround is to ensure these bits are clear in TCR_ELx.
784 The workaround only affects the Fujitsu-A64FX.
788 config HISILICON_ERRATUM_161600802
789 bool "Hip07 161600802: Erroneous redistributor VLPI base"
792 The HiSilicon Hip07 SoC uses the wrong redistributor base
793 when issued ITS commands such as VMOVP and VMAPP, and requires
794 a 128kB offset to be applied to the target address in this commands.
798 config QCOM_FALKOR_ERRATUM_1003
799 bool "Falkor E1003: Incorrect translation due to ASID change"
802 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
803 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
804 in TTBR1_EL1, this situation only occurs in the entry trampoline and
805 then only for entries in the walk cache, since the leaf translation
806 is unchanged. Work around the erratum by invalidating the walk cache
807 entries for the trampoline before entering the kernel proper.
809 config QCOM_FALKOR_ERRATUM_1009
810 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
812 select ARM64_WORKAROUND_REPEAT_TLBI
814 On Falkor v1, the CPU may prematurely complete a DSB following a
815 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
816 one more time to fix the issue.
820 config QCOM_QDF2400_ERRATUM_0065
821 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
824 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
825 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
826 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
830 config QCOM_FALKOR_ERRATUM_E1041
831 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
834 Falkor CPU may speculatively fetch instructions from an improper
835 memory location when MMU translation is changed from SCTLR_ELn[M]=1
836 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
840 config SOCIONEXT_SYNQUACER_PREITS
841 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
844 Socionext Synquacer SoCs implement a separate h/w block to generate
845 MSI doorbell writes with non-zero values for the device ID.
854 default ARM64_4K_PAGES
856 Page size (translation granule) configuration.
858 config ARM64_4K_PAGES
861 This feature enables 4KB pages support.
863 config ARM64_16K_PAGES
866 The system will use 16KB pages support. AArch32 emulation
867 requires applications compiled with 16K (or a multiple of 16K)
870 config ARM64_64K_PAGES
873 This feature enables 64KB pages support (4KB by default)
874 allowing only two levels of page tables and faster TLB
875 look-up. AArch32 emulation requires applications compiled
876 with 64K aligned segments.
881 prompt "Virtual address space size"
882 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
883 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
884 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
886 Allows choosing one of multiple possible virtual address
887 space sizes. The level of translation table is determined by
888 a combination of page size and virtual address space size.
890 config ARM64_VA_BITS_36
891 bool "36-bit" if EXPERT
892 depends on ARM64_16K_PAGES
894 config ARM64_VA_BITS_39
896 depends on ARM64_4K_PAGES
898 config ARM64_VA_BITS_42
900 depends on ARM64_64K_PAGES
902 config ARM64_VA_BITS_47
904 depends on ARM64_16K_PAGES
906 config ARM64_VA_BITS_48
909 config ARM64_VA_BITS_52
911 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
913 Enable 52-bit virtual addressing for userspace when explicitly
914 requested via a hint to mmap(). The kernel will also use 52-bit
915 virtual addresses for its own mappings (provided HW support for
916 this feature is available, otherwise it reverts to 48-bit).
918 NOTE: Enabling 52-bit virtual addressing in conjunction with
919 ARMv8.3 Pointer Authentication will result in the PAC being
920 reduced from 7 bits to 3 bits, which may have a significant
921 impact on its susceptibility to brute-force attacks.
923 If unsure, select 48-bit virtual addressing instead.
927 config ARM64_FORCE_52BIT
928 bool "Force 52-bit virtual addresses for userspace"
929 depends on ARM64_VA_BITS_52 && EXPERT
931 For systems with 52-bit userspace VAs enabled, the kernel will attempt
932 to maintain compatibility with older software by providing 48-bit VAs
933 unless a hint is supplied to mmap.
935 This configuration option disables the 48-bit compatibility logic, and
936 forces all userspace addresses to be 52-bit on HW that supports it. One
937 should only enable this configuration option for stress testing userspace
938 memory management code. If unsure say N here.
942 default 36 if ARM64_VA_BITS_36
943 default 39 if ARM64_VA_BITS_39
944 default 42 if ARM64_VA_BITS_42
945 default 47 if ARM64_VA_BITS_47
946 default 48 if ARM64_VA_BITS_48
947 default 52 if ARM64_VA_BITS_52
950 prompt "Physical address space size"
951 default ARM64_PA_BITS_48
953 Choose the maximum physical address range that the kernel will
956 config ARM64_PA_BITS_48
959 config ARM64_PA_BITS_52
960 bool "52-bit (ARMv8.2)"
961 depends on ARM64_64K_PAGES
962 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
964 Enable support for a 52-bit physical address space, introduced as
965 part of the ARMv8.2-LPA extension.
967 With this enabled, the kernel will also continue to work on CPUs that
968 do not support ARMv8.2-LPA, but with some added memory overhead (and
969 minor performance overhead).
975 default 48 if ARM64_PA_BITS_48
976 default 52 if ARM64_PA_BITS_52
980 default CPU_LITTLE_ENDIAN
982 Select the endianness of data accesses performed by the CPU. Userspace
983 applications will need to be compiled and linked for the endianness
984 that is selected here.
986 config CPU_BIG_ENDIAN
987 bool "Build big-endian kernel"
988 depends on !LD_IS_LLD || LLD_VERSION >= 130000
989 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
990 depends on AS_IS_GNU || AS_VERSION >= 150000
992 Say Y if you plan on running a kernel with a big-endian userspace.
994 config CPU_LITTLE_ENDIAN
995 bool "Build little-endian kernel"
997 Say Y if you plan on running a kernel with a little-endian userspace.
998 This is usually the case for distributions targeting arm64.
1003 bool "Multi-core scheduler support"
1005 Multi-core scheduler support improves the CPU scheduler's decision
1006 making when dealing with multi-core CPU chips at a cost of slightly
1007 increased overhead in some places. If unsure say N here.
1010 bool "SMT scheduler support"
1012 Improves the CPU scheduler's decision making when dealing with
1013 MultiThreading at a cost of slightly increased overhead in some
1014 places. If unsure say N here.
1017 int "Maximum number of CPUs (2-4096)"
1022 bool "Support for hot-pluggable CPUs"
1023 select GENERIC_IRQ_MIGRATION
1025 Say Y here to experiment with turning CPUs off and on. CPUs
1026 can be controlled through /sys/devices/system/cpu.
1028 # Common NUMA Features
1030 bool "NUMA Memory Allocation and Scheduler Support"
1031 select ACPI_NUMA if ACPI
1034 Enable NUMA (Non-Uniform Memory Access) support.
1036 The kernel will try to allocate memory used by a CPU on the
1037 local memory of the CPU and add some more
1038 NUMA awareness to the kernel.
1041 int "Maximum NUMA Nodes (as a power of 2)"
1044 depends on NEED_MULTIPLE_NODES
1046 Specify the maximum number of NUMA Nodes available on the target
1047 system. Increases memory reserved to accommodate various tables.
1049 config USE_PERCPU_NUMA_NODE_ID
1053 config HAVE_SETUP_PER_CPU_AREA
1057 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1061 config HOLES_IN_ZONE
1064 source "kernel/Kconfig.hz"
1066 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
1069 config ARCH_SPARSEMEM_ENABLE
1071 select SPARSEMEM_VMEMMAP_ENABLE
1073 config ARCH_SPARSEMEM_DEFAULT
1074 def_bool ARCH_SPARSEMEM_ENABLE
1076 config ARCH_SELECT_MEMORY_MODEL
1077 def_bool ARCH_SPARSEMEM_ENABLE
1079 config ARCH_FLATMEM_ENABLE
1082 config HAVE_ARCH_PFN_VALID
1085 config HW_PERF_EVENTS
1089 config SYS_SUPPORTS_HUGETLBFS
1092 config ARCH_WANT_HUGE_PMD_SHARE
1094 config ARCH_HAS_CACHE_LINE_SIZE
1097 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1098 def_bool y if PGTABLE_LEVELS > 2
1100 # Supported by clang >= 7.0
1101 config CC_HAVE_SHADOW_CALL_STACK
1102 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1105 bool "Enable paravirtualization code"
1107 This changes the kernel so it can modify itself when it is run
1108 under a hypervisor, potentially improving performance significantly
1109 over full virtualization.
1111 config PARAVIRT_TIME_ACCOUNTING
1112 bool "Paravirtual steal time accounting"
1115 Select this option to enable fine granularity task steal time
1116 accounting. Time spent executing other tasks in parallel with
1117 the current vCPU is discounted from the vCPU power. To account for
1118 that, there can be a small performance impact.
1120 If in doubt, say N here.
1123 depends on PM_SLEEP_SMP
1125 bool "kexec system call"
1127 kexec is a system call that implements the ability to shutdown your
1128 current kernel, and to start another kernel. It is like a reboot
1129 but it is independent of the system firmware. And like a reboot
1130 you can start any kernel with it, not just Linux.
1133 bool "kexec file based system call"
1136 This is new version of kexec system call. This system call is
1137 file based and takes file descriptors as system call argument
1138 for kernel and initramfs as opposed to list of segments as
1139 accepted by previous system call.
1142 bool "Verify kernel signature during kexec_file_load() syscall"
1143 depends on KEXEC_FILE
1145 Select this option to verify a signature with loaded kernel
1146 image. If configured, any attempt of loading a image without
1147 valid signature will fail.
1149 In addition to that option, you need to enable signature
1150 verification for the corresponding kernel image type being
1151 loaded in order for this to work.
1153 config KEXEC_IMAGE_VERIFY_SIG
1154 bool "Enable Image signature verification support"
1156 depends on KEXEC_SIG
1157 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1159 Enable Image signature verification support.
1161 comment "Support for PE file signature verification disabled"
1162 depends on KEXEC_SIG
1163 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1166 bool "Build kdump crash kernel"
1168 Generate crash dump after being started by kexec. This should
1169 be normally only set in special crash dump kernels which are
1170 loaded in the main kernel with kexec-tools into a specially
1171 reserved region and then later executed after a crash by
1174 For more details see Documentation/admin-guide/kdump/kdump.rst
1181 bool "Xen guest support on ARM64"
1182 depends on ARM64 && OF
1186 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1188 config FORCE_MAX_ZONEORDER
1190 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1191 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1194 The kernel memory allocator divides physically contiguous memory
1195 blocks into "zones", where each zone is a power of two number of
1196 pages. This option selects the largest power of two that the kernel
1197 keeps in the memory allocator. If you need to allocate very large
1198 blocks of physically contiguous memory, then you may need to
1199 increase this value.
1201 This config option is actually maximum order plus one. For example,
1202 a value of 11 means that the largest free memory block is 2^10 pages.
1204 We make sure that we can allocate upto a HugePage size for each configuration.
1206 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1208 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1209 4M allocations matching the default size used by generic code.
1211 config UNMAP_KERNEL_AT_EL0
1212 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1215 Speculation attacks against some high-performance processors can
1216 be used to bypass MMU permission checks and leak kernel data to
1217 userspace. This can be defended against by unmapping the kernel
1218 when running in userspace, mapping it back in on exception entry
1219 via a trampoline page in the vector table.
1223 config MITIGATE_SPECTRE_BRANCH_HISTORY
1224 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1227 Speculation attacks against some high-performance processors can
1228 make use of branch history to influence future speculation.
1229 When taking an exception from user-space, a sequence of branches
1230 or a firmware call overwrites the branch history.
1232 config RODATA_FULL_DEFAULT_ENABLED
1233 bool "Apply r/o permissions of VM areas also to their linear aliases"
1236 Apply read-only attributes of VM areas to the linear alias of
1237 the backing pages as well. This prevents code or read-only data
1238 from being modified (inadvertently or intentionally) via another
1239 mapping of the same memory page. This additional enhancement can
1240 be turned off at runtime by passing rodata=[off|on] (and turned on
1241 with rodata=full if this option is set to 'n')
1243 This requires the linear region to be mapped down to pages,
1244 which may adversely affect performance in some cases.
1246 config ARM64_SW_TTBR0_PAN
1247 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1249 Enabling this option prevents the kernel from accessing
1250 user-space memory directly by pointing TTBR0_EL1 to a reserved
1251 zeroed area and reserved ASID. The user access routines
1252 restore the valid TTBR0_EL1 temporarily.
1254 config ARM64_TAGGED_ADDR_ABI
1255 bool "Enable the tagged user addresses syscall ABI"
1258 When this option is enabled, user applications can opt in to a
1259 relaxed ABI via prctl() allowing tagged addresses to be passed
1260 to system calls as pointer arguments. For details, see
1261 Documentation/arm64/tagged-address-abi.rst.
1264 bool "Kernel support for 32-bit EL0"
1265 depends on ARM64_4K_PAGES || EXPERT
1266 select COMPAT_BINFMT_ELF if BINFMT_ELF
1268 select OLD_SIGSUSPEND3
1269 select COMPAT_OLD_SIGACTION
1271 This option enables support for a 32-bit EL0 running under a 64-bit
1272 kernel at EL1. AArch32-specific components such as system calls,
1273 the user helper functions, VFP support and the ptrace interface are
1274 handled appropriately by the kernel.
1276 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1277 that you will only be able to execute AArch32 binaries that were compiled
1278 with page size aligned segments.
1280 If you want to execute 32-bit userspace applications, say Y.
1284 config KUSER_HELPERS
1285 bool "Enable kuser helpers page for 32-bit applications"
1288 Warning: disabling this option may break 32-bit user programs.
1290 Provide kuser helpers to compat tasks. The kernel provides
1291 helper code to userspace in read only form at a fixed location
1292 to allow userspace to be independent of the CPU type fitted to
1293 the system. This permits binaries to be run on ARMv4 through
1294 to ARMv8 without modification.
1296 See Documentation/arm/kernel_user_helpers.rst for details.
1298 However, the fixed address nature of these helpers can be used
1299 by ROP (return orientated programming) authors when creating
1302 If all of the binaries and libraries which run on your platform
1303 are built specifically for your platform, and make no use of
1304 these helpers, then you can turn this option off to hinder
1305 such exploits. However, in that case, if a binary or library
1306 relying on those helpers is run, it will not function correctly.
1308 Say N here only if you are absolutely certain that you do not
1309 need these helpers; otherwise, the safe option is to say Y.
1312 bool "Enable vDSO for 32-bit applications"
1313 depends on !CPU_BIG_ENDIAN
1314 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1315 select GENERIC_COMPAT_VDSO
1318 Place in the process address space of 32-bit applications an
1319 ELF shared object providing fast implementations of gettimeofday
1322 You must have a 32-bit build of glibc 2.22 or later for programs
1323 to seamlessly take advantage of this.
1325 config THUMB2_COMPAT_VDSO
1326 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1327 depends on COMPAT_VDSO
1330 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1331 otherwise with '-marm'.
1333 menuconfig ARMV8_DEPRECATED
1334 bool "Emulate deprecated/obsolete ARMv8 instructions"
1337 Legacy software support may require certain instructions
1338 that have been deprecated or obsoleted in the architecture.
1340 Enable this config to enable selective emulation of these
1347 config SWP_EMULATION
1348 bool "Emulate SWP/SWPB instructions"
1350 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1351 they are always undefined. Say Y here to enable software
1352 emulation of these instructions for userspace using LDXR/STXR.
1353 This feature can be controlled at runtime with the abi.swp
1354 sysctl which is disabled by default.
1356 In some older versions of glibc [<=2.8] SWP is used during futex
1357 trylock() operations with the assumption that the code will not
1358 be preempted. This invalid assumption may be more likely to fail
1359 with SWP emulation enabled, leading to deadlock of the user
1362 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1363 on an external transaction monitoring block called a global
1364 monitor to maintain update atomicity. If your system does not
1365 implement a global monitor, this option can cause programs that
1366 perform SWP operations to uncached memory to deadlock.
1370 config CP15_BARRIER_EMULATION
1371 bool "Emulate CP15 Barrier instructions"
1373 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1374 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1375 strongly recommended to use the ISB, DSB, and DMB
1376 instructions instead.
1378 Say Y here to enable software emulation of these
1379 instructions for AArch32 userspace code. When this option is
1380 enabled, CP15 barrier usage is traced which can help
1381 identify software that needs updating. This feature can be
1382 controlled at runtime with the abi.cp15_barrier sysctl.
1386 config SETEND_EMULATION
1387 bool "Emulate SETEND instruction"
1389 The SETEND instruction alters the data-endianness of the
1390 AArch32 EL0, and is deprecated in ARMv8.
1392 Say Y here to enable software emulation of the instruction
1393 for AArch32 userspace code. This feature can be controlled
1394 at runtime with the abi.setend sysctl.
1396 Note: All the cpus on the system must have mixed endian support at EL0
1397 for this feature to be enabled. If a new CPU - which doesn't support mixed
1398 endian - is hotplugged in after this feature has been enabled, there could
1399 be unexpected results in the applications.
1406 menu "ARMv8.1 architectural features"
1408 config ARM64_HW_AFDBM
1409 bool "Support for hardware updates of the Access and Dirty page flags"
1412 The ARMv8.1 architecture extensions introduce support for
1413 hardware updates of the access and dirty information in page
1414 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1415 capable processors, accesses to pages with PTE_AF cleared will
1416 set this bit instead of raising an access flag fault.
1417 Similarly, writes to read-only pages with the DBM bit set will
1418 clear the read-only bit (AP[2]) instead of raising a
1421 Kernels built with this configuration option enabled continue
1422 to work on pre-ARMv8.1 hardware and the performance impact is
1423 minimal. If unsure, say Y.
1426 bool "Enable support for Privileged Access Never (PAN)"
1429 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1430 prevents the kernel or hypervisor from accessing user-space (EL0)
1433 Choosing this option will cause any unprotected (not using
1434 copy_to_user et al) memory access to fail with a permission fault.
1436 The feature is detected at runtime, and will remain as a 'nop'
1437 instruction if the cpu does not implement the feature.
1439 config AS_HAS_LSE_ATOMICS
1440 def_bool $(as-instr,.arch_extension lse)
1442 config ARM64_LSE_ATOMICS
1444 default ARM64_USE_LSE_ATOMICS
1445 depends on AS_HAS_LSE_ATOMICS
1447 config ARM64_USE_LSE_ATOMICS
1448 bool "Atomic instructions"
1449 depends on JUMP_LABEL
1452 As part of the Large System Extensions, ARMv8.1 introduces new
1453 atomic instructions that are designed specifically to scale in
1456 Say Y here to make use of these instructions for the in-kernel
1457 atomic routines. This incurs a small overhead on CPUs that do
1458 not support these instructions and requires the kernel to be
1459 built with binutils >= 2.25 in order for the new instructions
1463 bool "Enable support for Virtualization Host Extensions (VHE)"
1466 Virtualization Host Extensions (VHE) allow the kernel to run
1467 directly at EL2 (instead of EL1) on processors that support
1468 it. This leads to better performance for KVM, as they reduce
1469 the cost of the world switch.
1471 Selecting this option allows the VHE feature to be detected
1472 at runtime, and does not affect processors that do not
1473 implement this feature.
1477 menu "ARMv8.2 architectural features"
1480 bool "Enable support for User Access Override (UAO)"
1483 User Access Override (UAO; part of the ARMv8.2 Extensions)
1484 causes the 'unprivileged' variant of the load/store instructions to
1485 be overridden to be privileged.
1487 This option changes get_user() and friends to use the 'unprivileged'
1488 variant of the load/store instructions. This ensures that user-space
1489 really did have access to the supplied memory. When addr_limit is
1490 set to kernel memory the UAO bit will be set, allowing privileged
1491 access to kernel memory.
1493 Choosing this option will cause copy_to_user() et al to use user-space
1496 The feature is detected at runtime, the kernel will use the
1497 regular load/store instructions if the cpu does not implement the
1501 bool "Enable support for persistent memory"
1502 select ARCH_HAS_PMEM_API
1503 select ARCH_HAS_UACCESS_FLUSHCACHE
1505 Say Y to enable support for the persistent memory API based on the
1506 ARMv8.2 DCPoP feature.
1508 The feature is detected at runtime, and the kernel will use DC CVAC
1509 operations if DC CVAP is not supported (following the behaviour of
1510 DC CVAP itself if the system does not define a point of persistence).
1512 config ARM64_RAS_EXTN
1513 bool "Enable support for RAS CPU Extensions"
1516 CPUs that support the Reliability, Availability and Serviceability
1517 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1518 errors, classify them and report them to software.
1520 On CPUs with these extensions system software can use additional
1521 barriers to determine if faults are pending and read the
1522 classification from a new set of registers.
1524 Selecting this feature will allow the kernel to use these barriers
1525 and access the new registers if the system supports the extension.
1526 Platform RAS features may additionally depend on firmware support.
1529 bool "Enable support for Common Not Private (CNP) translations"
1531 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1533 Common Not Private (CNP) allows translation table entries to
1534 be shared between different PEs in the same inner shareable
1535 domain, so the hardware can use this fact to optimise the
1536 caching of such entries in the TLB.
1538 Selecting this option allows the CNP feature to be detected
1539 at runtime, and does not affect PEs that do not implement
1544 menu "ARMv8.3 architectural features"
1546 config ARM64_PTR_AUTH
1547 bool "Enable support for pointer authentication"
1549 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1550 # Modern compilers insert a .note.gnu.property section note for PAC
1551 # which is only understood by binutils starting with version 2.33.1.
1552 depends on LD_IS_LLD || LD_VERSION >= 233010000 || (CC_IS_GCC && GCC_VERSION < 90100)
1553 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1554 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1556 Pointer authentication (part of the ARMv8.3 Extensions) provides
1557 instructions for signing and authenticating pointers against secret
1558 keys, which can be used to mitigate Return Oriented Programming (ROP)
1561 This option enables these instructions at EL0 (i.e. for userspace).
1562 Choosing this option will cause the kernel to initialise secret keys
1563 for each process at exec() time, with these keys being
1564 context-switched along with the process.
1566 If the compiler supports the -mbranch-protection or
1567 -msign-return-address flag (e.g. GCC 7 or later), then this option
1568 will also cause the kernel itself to be compiled with return address
1569 protection. In this case, and if the target hardware is known to
1570 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1571 disabled with minimal loss of protection.
1573 The feature is detected at runtime. If the feature is not present in
1574 hardware it will not be advertised to userspace/KVM guest nor will it
1577 If the feature is present on the boot CPU but not on a late CPU, then
1578 the late CPU will be parked. Also, if the boot CPU does not have
1579 address auth and the late CPU has then the late CPU will still boot
1580 but with the feature disabled. On such a system, this option should
1583 This feature works with FUNCTION_GRAPH_TRACER option only if
1584 DYNAMIC_FTRACE_WITH_REGS is enabled.
1586 config CC_HAS_BRANCH_PROT_PAC_RET
1587 # GCC 9 or later, clang 8 or later
1588 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1590 config CC_HAS_SIGN_RETURN_ADDRESS
1592 def_bool $(cc-option,-msign-return-address=all)
1595 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1597 config AS_HAS_CFI_NEGATE_RA_STATE
1598 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1602 menu "ARMv8.4 architectural features"
1604 config ARM64_AMU_EXTN
1605 bool "Enable support for the Activity Monitors Unit CPU extension"
1608 The activity monitors extension is an optional extension introduced
1609 by the ARMv8.4 CPU architecture. This enables support for version 1
1610 of the activity monitors architecture, AMUv1.
1612 To enable the use of this extension on CPUs that implement it, say Y.
1614 Note that for architectural reasons, firmware _must_ implement AMU
1615 support when running on CPUs that present the activity monitors
1616 extension. The required support is present in:
1617 * Version 1.5 and later of the ARM Trusted Firmware
1619 For kernels that have this configuration enabled but boot with broken
1620 firmware, you may need to say N here until the firmware is fixed.
1621 Otherwise you may experience firmware panics or lockups when
1622 accessing the counter registers. Even if you are not observing these
1623 symptoms, the values returned by the register reads might not
1624 correctly reflect reality. Most commonly, the value read will be 0,
1625 indicating that the counter is not enabled.
1627 config AS_HAS_ARMV8_4
1628 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1630 config ARM64_TLB_RANGE
1631 bool "Enable support for tlbi range feature"
1633 depends on AS_HAS_ARMV8_4
1635 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1636 range of input addresses.
1638 The feature introduces new assembly instructions, and they were
1639 support when binutils >= 2.30.
1643 menu "ARMv8.5 architectural features"
1646 bool "Branch Target Identification support"
1649 Branch Target Identification (part of the ARMv8.5 Extensions)
1650 provides a mechanism to limit the set of locations to which computed
1651 branch instructions such as BR or BLR can jump.
1653 To make use of BTI on CPUs that support it, say Y.
1655 BTI is intended to provide complementary protection to other control
1656 flow integrity protection mechanisms, such as the Pointer
1657 authentication mechanism provided as part of the ARMv8.3 Extensions.
1658 For this reason, it does not make sense to enable this option without
1659 also enabling support for pointer authentication. Thus, when
1660 enabling this option you should also select ARM64_PTR_AUTH=y.
1662 Userspace binaries must also be specifically compiled to make use of
1663 this mechanism. If you say N here or the hardware does not support
1664 BTI, such binaries can still run, but you get no additional
1665 enforcement of branch destinations.
1667 config ARM64_BTI_KERNEL
1668 bool "Use Branch Target Identification for kernel"
1670 depends on ARM64_BTI
1671 depends on ARM64_PTR_AUTH
1672 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1673 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1674 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1675 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1676 depends on !CC_IS_GCC
1677 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1678 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1679 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1681 Build the kernel with Branch Target Identification annotations
1682 and enable enforcement of this for kernel code. When this option
1683 is enabled and the system supports BTI all kernel code including
1684 modular code must have BTI enabled.
1686 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1687 # GCC 9 or later, clang 8 or later
1688 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1691 bool "Enable support for E0PD"
1694 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1695 that EL0 accesses made via TTBR1 always fault in constant time,
1696 providing similar benefits to KASLR as those provided by KPTI, but
1697 with lower overhead and without disrupting legitimate access to
1698 kernel memory such as SPE.
1700 This option enables E0PD for TTBR1 where available.
1703 bool "Enable support for random number generation"
1706 Random number generation (part of the ARMv8.5 Extensions)
1707 provides a high bandwidth, cryptographically secure
1708 hardware random number generator.
1710 config ARM64_AS_HAS_MTE
1711 # Initial support for MTE went in binutils 2.32.0, checked with
1712 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1713 # as a late addition to the final architecture spec (LDGM/STGM)
1714 # is only supported in the newer 2.32.x and 2.33 binutils
1715 # versions, hence the extra "stgm" instruction check below.
1716 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1719 bool "Memory Tagging Extension support"
1721 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1722 depends on AS_HAS_LSE_ATOMICS
1723 select ARCH_USES_HIGH_VMA_FLAGS
1725 Memory Tagging (part of the ARMv8.5 Extensions) provides
1726 architectural support for run-time, always-on detection of
1727 various classes of memory error to aid with software debugging
1728 to eliminate vulnerabilities arising from memory-unsafe
1731 This option enables the support for the Memory Tagging
1732 Extension at EL0 (i.e. for userspace).
1734 Selecting this option allows the feature to be detected at
1735 runtime. Any secondary CPU not implementing this feature will
1736 not be allowed a late bring-up.
1738 Userspace binaries that want to use this feature must
1739 explicitly opt in. The mechanism for the userspace is
1742 Documentation/arm64/memory-tagging-extension.rst.
1747 bool "ARM Scalable Vector Extension support"
1749 depends on !KVM || ARM64_VHE
1751 The Scalable Vector Extension (SVE) is an extension to the AArch64
1752 execution state which complements and extends the SIMD functionality
1753 of the base architecture to support much larger vectors and to enable
1754 additional vectorisation opportunities.
1756 To enable use of this extension on CPUs that implement it, say Y.
1758 On CPUs that support the SVE2 extensions, this option will enable
1761 Note that for architectural reasons, firmware _must_ implement SVE
1762 support when running on SVE capable hardware. The required support
1765 * version 1.5 and later of the ARM Trusted Firmware
1766 * the AArch64 boot wrapper since commit 5e1261e08abf
1767 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1769 For other firmware implementations, consult the firmware documentation
1772 If you need the kernel to boot on SVE-capable hardware with broken
1773 firmware, you may need to say N here until you get your firmware
1774 fixed. Otherwise, you may experience firmware panics or lockups when
1775 booting the kernel. If unsure and you are not observing these
1776 symptoms, you should assume that it is safe to say Y.
1778 CPUs that support SVE are architecturally required to support the
1779 Virtualization Host Extensions (VHE), so the kernel makes no
1780 provision for supporting SVE alongside KVM without VHE enabled.
1781 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1782 KVM in the same kernel image.
1784 config ARM64_MODULE_PLTS
1785 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1787 select HAVE_MOD_ARCH_SPECIFIC
1789 Allocate PLTs when loading modules so that jumps and calls whose
1790 targets are too far away for their relative offsets to be encoded
1791 in the instructions themselves can be bounced via veneers in the
1792 module's PLT. This allows modules to be allocated in the generic
1793 vmalloc area after the dedicated module memory area has been
1796 When running with address space randomization (KASLR), the module
1797 region itself may be too far away for ordinary relative jumps and
1798 calls, and so in that case, module PLTs are required and cannot be
1801 Specific errata workaround(s) might also force module PLTs to be
1802 enabled (ARM64_ERRATUM_843419).
1804 config ARM64_PSEUDO_NMI
1805 bool "Support for NMI-like interrupts"
1808 Adds support for mimicking Non-Maskable Interrupts through the use of
1809 GIC interrupt priority. This support requires version 3 or later of
1812 This high priority configuration for interrupts needs to be
1813 explicitly enabled by setting the kernel parameter
1814 "irqchip.gicv3_pseudo_nmi" to 1.
1819 config ARM64_DEBUG_PRIORITY_MASKING
1820 bool "Debug interrupt priority masking"
1822 This adds runtime checks to functions enabling/disabling
1823 interrupts when using priority masking. The additional checks verify
1824 the validity of ICC_PMR_EL1 when calling concerned functions.
1830 bool "Build a relocatable kernel image" if EXPERT
1831 select ARCH_HAS_RELR
1834 This builds the kernel as a Position Independent Executable (PIE),
1835 which retains all relocation metadata required to relocate the
1836 kernel binary at runtime to a different virtual address than the
1837 address it was linked at.
1838 Since AArch64 uses the RELA relocation format, this requires a
1839 relocation pass at runtime even if the kernel is loaded at the
1840 same address it was linked at.
1842 config RANDOMIZE_BASE
1843 bool "Randomize the address of the kernel image"
1844 select ARM64_MODULE_PLTS if MODULES
1847 Randomizes the virtual address at which the kernel image is
1848 loaded, as a security feature that deters exploit attempts
1849 relying on knowledge of the location of kernel internals.
1851 It is the bootloader's job to provide entropy, by passing a
1852 random u64 value in /chosen/kaslr-seed at kernel entry.
1854 When booting via the UEFI stub, it will invoke the firmware's
1855 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1856 to the kernel proper. In addition, it will randomise the physical
1857 location of the kernel Image as well.
1861 config RANDOMIZE_MODULE_REGION_FULL
1862 bool "Randomize the module region over a 4 GB range"
1863 depends on RANDOMIZE_BASE
1866 Randomizes the location of the module region inside a 4 GB window
1867 covering the core kernel. This way, it is less likely for modules
1868 to leak information about the location of core kernel data structures
1869 but it does imply that function calls between modules and the core
1870 kernel will need to be resolved via veneers in the module PLT.
1872 When this option is not set, the module region will be randomized over
1873 a limited range that contains the [_stext, _etext] interval of the
1874 core kernel, so branch relocations are always in range.
1876 config CC_HAVE_STACKPROTECTOR_SYSREG
1877 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1879 config STACKPROTECTOR_PER_TASK
1881 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1887 config ARM64_ACPI_PARKING_PROTOCOL
1888 bool "Enable support for the ARM64 ACPI parking protocol"
1891 Enable support for the ARM64 ACPI parking protocol. If disabled
1892 the kernel will not allow booting through the ARM64 ACPI parking
1893 protocol even if the corresponding data is present in the ACPI
1897 string "Default kernel command string"
1900 Provide a set of default command-line options at build time by
1901 entering them here. As a minimum, you should specify the the
1902 root device (e.g. root=/dev/nfs).
1904 config CMDLINE_FORCE
1905 bool "Always use the default kernel command string"
1906 depends on CMDLINE != ""
1908 Always use the default kernel command string, even if the boot
1909 loader passes other arguments to the kernel.
1910 This is useful if you cannot or don't want to change the
1911 command-line options your boot loader passes to the kernel.
1917 bool "UEFI runtime support"
1918 depends on OF && !CPU_BIG_ENDIAN
1919 depends on KERNEL_MODE_NEON
1920 select ARCH_SUPPORTS_ACPI
1923 select EFI_PARAMS_FROM_FDT
1924 select EFI_RUNTIME_WRAPPERS
1926 select EFI_GENERIC_STUB
1929 This option provides support for runtime services provided
1930 by UEFI firmware (such as non-volatile variables, realtime
1931 clock, and platform reset). A UEFI stub is also provided to
1932 allow the kernel to be booted as an EFI application. This
1933 is only useful on systems that have UEFI firmware.
1936 bool "Enable support for SMBIOS (DMI) tables"
1940 This enables SMBIOS/DMI feature for systems.
1942 This option is only useful on systems that have UEFI firmware.
1943 However, even with this option, the resultant kernel should
1944 continue to boot on existing non-UEFI platforms.
1948 config SYSVIPC_COMPAT
1950 depends on COMPAT && SYSVIPC
1952 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1954 depends on HUGETLB_PAGE && MIGRATION
1956 config ARCH_ENABLE_THP_MIGRATION
1958 depends on TRANSPARENT_HUGEPAGE
1960 menu "Power management options"
1962 source "kernel/power/Kconfig"
1964 config ARCH_HIBERNATION_POSSIBLE
1968 config ARCH_HIBERNATION_HEADER
1970 depends on HIBERNATION
1972 config ARCH_SUSPEND_POSSIBLE
1977 menu "CPU Power Management"
1979 source "drivers/cpuidle/Kconfig"
1981 source "drivers/cpufreq/Kconfig"
1985 source "drivers/firmware/Kconfig"
1987 source "drivers/acpi/Kconfig"
1989 source "arch/arm64/kvm/Kconfig"
1992 source "arch/arm64/crypto/Kconfig"