3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
15 select ARCH_HAS_ELF_RANDOMIZE
16 select ARCH_HAS_FAST_MULTIPLIER
17 select ARCH_HAS_FORTIFY_SOURCE
18 select ARCH_HAS_GCOV_PROFILE_ALL
19 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
21 select ARCH_HAS_MEMBARRIER_SYNC_CORE
22 select ARCH_HAS_PTE_SPECIAL
23 select ARCH_HAS_SET_MEMORY
24 select ARCH_HAS_SG_CHAIN
25 select ARCH_HAS_STRICT_KERNEL_RWX
26 select ARCH_HAS_STRICT_MODULE_RWX
27 select ARCH_HAS_SYSCALL_WRAPPER
28 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
29 select ARCH_HAVE_NMI_SAFE_CMPXCHG
30 select ARCH_INLINE_READ_LOCK if !PREEMPT
31 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
32 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
33 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
34 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
35 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
36 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
37 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
38 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
39 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
40 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
42 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
43 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
44 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
46 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
47 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
48 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
49 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
50 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
51 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
52 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
53 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
54 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
55 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
56 select ARCH_USE_CMPXCHG_LOCKREF
57 select ARCH_USE_QUEUED_RWLOCKS
58 select ARCH_USE_QUEUED_SPINLOCKS
59 select ARCH_SUPPORTS_MEMORY_FAILURE
60 select ARCH_SUPPORTS_ATOMIC_RMW
61 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
62 select ARCH_SUPPORTS_NUMA_BALANCING
63 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
64 select ARCH_WANT_FRAME_POINTERS
65 select ARCH_HAS_UBSAN_SANITIZE_ALL
69 select AUDIT_ARCH_COMPAT_GENERIC
70 select ARM_GIC_V2M if PCI
72 select ARM_GIC_V3_ITS if PCI
74 select BUILDTIME_EXTABLE_SORT
75 select CLONE_BACKWARDS
77 select CPU_PM if (SUSPEND || CPU_IDLE)
78 select DCACHE_WORD_ACCESS
82 select GENERIC_ALLOCATOR
83 select GENERIC_ARCH_TOPOLOGY
84 select GENERIC_CLOCKEVENTS
85 select GENERIC_CLOCKEVENTS_BROADCAST
86 select GENERIC_CPU_AUTOPROBE
87 select GENERIC_CPU_VULNERABILITIES
88 select GENERIC_EARLY_IOREMAP
89 select GENERIC_IDLE_POLL_SETUP
90 select GENERIC_IRQ_MULTI_HANDLER
91 select GENERIC_IRQ_PROBE
92 select GENERIC_IRQ_SHOW
93 select GENERIC_IRQ_SHOW_LEVEL
94 select GENERIC_PCI_IOMAP
95 select GENERIC_SCHED_CLOCK
96 select GENERIC_SMP_IDLE_THREAD
97 select GENERIC_STRNCPY_FROM_USER
98 select GENERIC_STRNLEN_USER
99 select GENERIC_TIME_VSYSCALL
100 select HANDLE_DOMAIN_IRQ
101 select HARDIRQS_SW_RESEND
102 select HAVE_ACPI_APEI if (ACPI && EFI)
103 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
104 select HAVE_ARCH_AUDITSYSCALL
105 select HAVE_ARCH_BITREVERSE
106 select HAVE_ARCH_HUGE_VMAP
107 select HAVE_ARCH_JUMP_LABEL
108 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
109 select HAVE_ARCH_KGDB
110 select HAVE_ARCH_MMAP_RND_BITS
111 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
112 select HAVE_ARCH_PREL32_RELOCATIONS
113 select HAVE_ARCH_SECCOMP_FILTER
114 select HAVE_ARCH_STACKLEAK
115 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
116 select HAVE_ARCH_TRACEHOOK
117 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
118 select HAVE_ARCH_VMAP_STACK
119 select HAVE_ARM_SMCCC
121 select HAVE_C_RECORDMCOUNT
122 select HAVE_CMPXCHG_DOUBLE
123 select HAVE_CMPXCHG_LOCAL
124 select HAVE_CONTEXT_TRACKING
125 select HAVE_DEBUG_BUGVERBOSE
126 select HAVE_DEBUG_KMEMLEAK
127 select HAVE_DMA_CONTIGUOUS
128 select HAVE_DYNAMIC_FTRACE
129 select HAVE_EFFICIENT_UNALIGNED_ACCESS
130 select HAVE_FTRACE_MCOUNT_RECORD
131 select HAVE_FUNCTION_TRACER
132 select HAVE_FUNCTION_GRAPH_TRACER
133 select HAVE_GCC_PLUGINS
134 select HAVE_GENERIC_DMA_COHERENT
135 select HAVE_HW_BREAKPOINT if PERF_EVENTS
136 select HAVE_IRQ_TIME_ACCOUNTING
138 select HAVE_MEMBLOCK_NODE_MAP if NUMA
140 select HAVE_PATA_PLATFORM
141 select HAVE_PERF_EVENTS
142 select HAVE_PERF_REGS
143 select HAVE_PERF_USER_STACK_DUMP
144 select HAVE_REGS_AND_STACK_ACCESS_API
145 select HAVE_RCU_TABLE_FREE
147 select HAVE_STACKPROTECTOR
148 select HAVE_SYSCALL_TRACEPOINTS
150 select HAVE_KRETPROBES
151 select IOMMU_DMA if IOMMU_SUPPORT
153 select IRQ_FORCED_THREADING
154 select MODULES_USE_ELF_RELA
155 select MULTI_IRQ_HANDLER
156 select NEED_DMA_MAP_STATE
157 select NEED_SG_DMA_LENGTH
160 select OF_EARLY_FLATTREE
161 select OF_RESERVED_MEM
162 select PCI_ECAM if ACPI
168 select SYSCTL_EXCEPTION_TRACE
169 select THREAD_INFO_IN_TASK
171 ARM 64-bit (AArch64) Linux support.
179 config ARM64_PAGE_SHIFT
181 default 16 if ARM64_64K_PAGES
182 default 14 if ARM64_16K_PAGES
185 config ARM64_CONT_SHIFT
187 default 5 if ARM64_64K_PAGES
188 default 7 if ARM64_16K_PAGES
191 config ARCH_MMAP_RND_BITS_MIN
192 default 14 if ARM64_64K_PAGES
193 default 16 if ARM64_16K_PAGES
196 # max bits determined by the following formula:
197 # VA_BITS - PAGE_SHIFT - 3
198 config ARCH_MMAP_RND_BITS_MAX
199 default 19 if ARM64_VA_BITS=36
200 default 24 if ARM64_VA_BITS=39
201 default 27 if ARM64_VA_BITS=42
202 default 30 if ARM64_VA_BITS=47
203 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
204 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
205 default 33 if ARM64_VA_BITS=48
206 default 14 if ARM64_64K_PAGES
207 default 16 if ARM64_16K_PAGES
210 config ARCH_MMAP_RND_COMPAT_BITS_MIN
211 default 7 if ARM64_64K_PAGES
212 default 9 if ARM64_16K_PAGES
215 config ARCH_MMAP_RND_COMPAT_BITS_MAX
221 config STACKTRACE_SUPPORT
224 config ILLEGAL_POINTER_VALUE
226 default 0xdead000000000000
228 config LOCKDEP_SUPPORT
231 config TRACE_IRQFLAGS_SUPPORT
234 config RWSEM_XCHGADD_ALGORITHM
241 config GENERIC_BUG_RELATIVE_POINTERS
243 depends on GENERIC_BUG
245 config GENERIC_HWEIGHT
251 config GENERIC_CALIBRATE_DELAY
255 bool "Support DMA32 zone" if EXPERT
258 config HAVE_GENERIC_GUP
264 config KERNEL_MODE_NEON
267 config FIX_EARLYCON_MEM
270 config PGTABLE_LEVELS
272 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
273 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
274 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
275 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
276 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
277 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
279 config ARCH_SUPPORTS_UPROBES
282 config ARCH_PROC_KCORE_TEXT
285 source "arch/arm64/Kconfig.platforms"
292 This feature enables support for PCI bus system. If you say Y
293 here, the kernel will include drivers and infrastructure code
294 to support PCI bus devices.
299 config PCI_DOMAINS_GENERIC
305 source "drivers/pci/Kconfig"
309 menu "Kernel Features"
311 menu "ARM errata workarounds via the alternatives framework"
313 config ARM64_ERRATUM_826319
314 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
317 This option adds an alternative code sequence to work around ARM
318 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
319 AXI master interface and an L2 cache.
321 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
322 and is unable to accept a certain write via this interface, it will
323 not progress on read data presented on the read data channel and the
326 The workaround promotes data cache clean instructions to
327 data cache clean-and-invalidate.
328 Please note that this does not necessarily enable the workaround,
329 as it depends on the alternative framework, which will only patch
330 the kernel if an affected CPU is detected.
334 config ARM64_ERRATUM_827319
335 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
338 This option adds an alternative code sequence to work around ARM
339 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
340 master interface and an L2 cache.
342 Under certain conditions this erratum can cause a clean line eviction
343 to occur at the same time as another transaction to the same address
344 on the AMBA 5 CHI interface, which can cause data corruption if the
345 interconnect reorders the two transactions.
347 The workaround promotes data cache clean instructions to
348 data cache clean-and-invalidate.
349 Please note that this does not necessarily enable the workaround,
350 as it depends on the alternative framework, which will only patch
351 the kernel if an affected CPU is detected.
355 config ARM64_ERRATUM_824069
356 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
359 This option adds an alternative code sequence to work around ARM
360 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
361 to a coherent interconnect.
363 If a Cortex-A53 processor is executing a store or prefetch for
364 write instruction at the same time as a processor in another
365 cluster is executing a cache maintenance operation to the same
366 address, then this erratum might cause a clean cache line to be
367 incorrectly marked as dirty.
369 The workaround promotes data cache clean instructions to
370 data cache clean-and-invalidate.
371 Please note that this option does not necessarily enable the
372 workaround, as it depends on the alternative framework, which will
373 only patch the kernel if an affected CPU is detected.
377 config ARM64_ERRATUM_819472
378 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
381 This option adds an alternative code sequence to work around ARM
382 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
383 present when it is connected to a coherent interconnect.
385 If the processor is executing a load and store exclusive sequence at
386 the same time as a processor in another cluster is executing a cache
387 maintenance operation to the same address, then this erratum might
388 cause data corruption.
390 The workaround promotes data cache clean instructions to
391 data cache clean-and-invalidate.
392 Please note that this does not necessarily enable the workaround,
393 as it depends on the alternative framework, which will only patch
394 the kernel if an affected CPU is detected.
398 config ARM64_ERRATUM_832075
399 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
402 This option adds an alternative code sequence to work around ARM
403 erratum 832075 on Cortex-A57 parts up to r1p2.
405 Affected Cortex-A57 parts might deadlock when exclusive load/store
406 instructions to Write-Back memory are mixed with Device loads.
408 The workaround is to promote device loads to use Load-Acquire
410 Please note that this does not necessarily enable the workaround,
411 as it depends on the alternative framework, which will only patch
412 the kernel if an affected CPU is detected.
416 config ARM64_ERRATUM_834220
417 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
421 This option adds an alternative code sequence to work around ARM
422 erratum 834220 on Cortex-A57 parts up to r1p2.
424 Affected Cortex-A57 parts might report a Stage 2 translation
425 fault as the result of a Stage 1 fault for load crossing a
426 page boundary when there is a permission or device memory
427 alignment fault at Stage 1 and a translation fault at Stage 2.
429 The workaround is to verify that the Stage 1 translation
430 doesn't generate a fault before handling the Stage 2 fault.
431 Please note that this does not necessarily enable the workaround,
432 as it depends on the alternative framework, which will only patch
433 the kernel if an affected CPU is detected.
437 config ARM64_ERRATUM_845719
438 bool "Cortex-A53: 845719: a load might read incorrect data"
442 This option adds an alternative code sequence to work around ARM
443 erratum 845719 on Cortex-A53 parts up to r0p4.
445 When running a compat (AArch32) userspace on an affected Cortex-A53
446 part, a load at EL0 from a virtual address that matches the bottom 32
447 bits of the virtual address used by a recent load at (AArch64) EL1
448 might return incorrect data.
450 The workaround is to write the contextidr_el1 register on exception
451 return to a 32-bit task.
452 Please note that this does not necessarily enable the workaround,
453 as it depends on the alternative framework, which will only patch
454 the kernel if an affected CPU is detected.
458 config ARM64_ERRATUM_843419
459 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
461 select ARM64_MODULE_PLTS if MODULES
463 This option links the kernel with '--fix-cortex-a53-843419' and
464 enables PLT support to replace certain ADRP instructions, which can
465 cause subsequent memory accesses to use an incorrect address on
466 Cortex-A53 parts up to r0p4.
470 config ARM64_ERRATUM_1024718
471 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
474 This option adds work around for Arm Cortex-A55 Erratum 1024718.
476 Affected Cortex-A55 cores (all revisions) could cause incorrect
477 update of the hardware dirty bit when the DBM/AP bits are updated
478 without a break-before-make. The work around is to disable the usage
479 of hardware DBM locally on the affected cores. CPUs not affected by
480 erratum will continue to use the feature.
484 config ARM64_ERRATUM_1463225
485 bool "Cortex-A76: Software Step might prevent interrupt recognition"
488 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
490 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
491 of a system call instruction (SVC) can prevent recognition of
492 subsequent interrupts when software stepping is disabled in the
493 exception handler of the system call and either kernel debugging
494 is enabled or VHE is in use.
496 Work around the erratum by triggering a dummy step exception
497 when handling a system call from a task that is being stepped
498 in a VHE configuration of the kernel.
502 config ARM64_ERRATUM_1542419
503 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
506 This option adds a workaround for ARM Neoverse-N1 erratum
509 Affected Neoverse-N1 cores could execute a stale instruction when
510 modified by another CPU. The workaround depends on a firmware
513 Workaround the issue by hiding the DIC feature from EL0. This
514 forces user-space to perform cache maintenance.
518 config ARM64_ERRATUM_1742098
519 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
523 This option removes the AES hwcap for aarch32 user-space to
524 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
526 Affected parts may corrupt the AES state if an interrupt is
527 taken between a pair of AES instructions. These instructions
528 are only present if the cryptography extensions are present.
529 All software should have a fallback implementation for CPUs
530 that don't implement the cryptography extensions.
534 config CAVIUM_ERRATUM_22375
535 bool "Cavium erratum 22375, 24313"
538 Enable workaround for erratum 22375, 24313.
540 This implements two gicv3-its errata workarounds for ThunderX. Both
541 with small impact affecting only ITS table allocation.
543 erratum 22375: only alloc 8MB table size
544 erratum 24313: ignore memory access type
546 The fixes are in ITS initialization and basically ignore memory access
547 type and table size provided by the TYPER and BASER registers.
551 config CAVIUM_ERRATUM_23144
552 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
556 ITS SYNC command hang for cross node io and collections/cpu mapping.
560 config CAVIUM_ERRATUM_23154
561 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
564 The gicv3 of ThunderX requires a modified version for
565 reading the IAR status to ensure data synchronization
566 (access to icc_iar1_el1 is not sync'ed before and after).
570 config CAVIUM_ERRATUM_27456
571 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
574 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
575 instructions may cause the icache to become corrupted if it
576 contains data for a non-current ASID. The fix is to
577 invalidate the icache when changing the mm context.
581 config CAVIUM_ERRATUM_30115
582 bool "Cavium erratum 30115: Guest may disable interrupts in host"
585 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
586 1.2, and T83 Pass 1.0, KVM guest execution may disable
587 interrupts in host. Trapping both GICv3 group-0 and group-1
588 accesses sidesteps the issue.
592 config QCOM_FALKOR_ERRATUM_1003
593 bool "Falkor E1003: Incorrect translation due to ASID change"
596 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
597 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
598 in TTBR1_EL1, this situation only occurs in the entry trampoline and
599 then only for entries in the walk cache, since the leaf translation
600 is unchanged. Work around the erratum by invalidating the walk cache
601 entries for the trampoline before entering the kernel proper.
603 config QCOM_FALKOR_ERRATUM_1009
604 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
607 On Falkor v1, the CPU may prematurely complete a DSB following a
608 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
609 one more time to fix the issue.
613 config QCOM_QDF2400_ERRATUM_0065
614 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
617 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
618 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
619 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
623 config SOCIONEXT_SYNQUACER_PREITS
624 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
627 Socionext Synquacer SoCs implement a separate h/w block to generate
628 MSI doorbell writes with non-zero values for the device ID.
632 config HISILICON_ERRATUM_161600802
633 bool "Hip07 161600802: Erroneous redistributor VLPI base"
636 The HiSilicon Hip07 SoC usees the wrong redistributor base
637 when issued ITS commands such as VMOVP and VMAPP, and requires
638 a 128kB offset to be applied to the target address in this commands.
642 config QCOM_FALKOR_ERRATUM_E1041
643 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
646 Falkor CPU may speculatively fetch instructions from an improper
647 memory location when MMU translation is changed from SCTLR_ELn[M]=1
648 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
657 default ARM64_4K_PAGES
659 Page size (translation granule) configuration.
661 config ARM64_4K_PAGES
664 This feature enables 4KB pages support.
666 config ARM64_16K_PAGES
669 The system will use 16KB pages support. AArch32 emulation
670 requires applications compiled with 16K (or a multiple of 16K)
673 config ARM64_64K_PAGES
676 This feature enables 64KB pages support (4KB by default)
677 allowing only two levels of page tables and faster TLB
678 look-up. AArch32 emulation requires applications compiled
679 with 64K aligned segments.
684 prompt "Virtual address space size"
685 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
686 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
687 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
689 Allows choosing one of multiple possible virtual address
690 space sizes. The level of translation table is determined by
691 a combination of page size and virtual address space size.
693 config ARM64_VA_BITS_36
694 bool "36-bit" if EXPERT
695 depends on ARM64_16K_PAGES
697 config ARM64_VA_BITS_39
699 depends on ARM64_4K_PAGES
701 config ARM64_VA_BITS_42
703 depends on ARM64_64K_PAGES
705 config ARM64_VA_BITS_47
707 depends on ARM64_16K_PAGES
709 config ARM64_VA_BITS_48
716 default 36 if ARM64_VA_BITS_36
717 default 39 if ARM64_VA_BITS_39
718 default 42 if ARM64_VA_BITS_42
719 default 47 if ARM64_VA_BITS_47
720 default 48 if ARM64_VA_BITS_48
723 prompt "Physical address space size"
724 default ARM64_PA_BITS_48
726 Choose the maximum physical address range that the kernel will
729 config ARM64_PA_BITS_48
732 config ARM64_PA_BITS_52
733 bool "52-bit (ARMv8.2)"
734 depends on ARM64_64K_PAGES
735 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
737 Enable support for a 52-bit physical address space, introduced as
738 part of the ARMv8.2-LPA extension.
740 With this enabled, the kernel will also continue to work on CPUs that
741 do not support ARMv8.2-LPA, but with some added memory overhead (and
742 minor performance overhead).
748 default 48 if ARM64_PA_BITS_48
749 default 52 if ARM64_PA_BITS_52
751 config CPU_BIG_ENDIAN
752 bool "Build big-endian kernel"
754 Say Y if you plan on running a kernel in big-endian mode.
757 bool "Multi-core scheduler support"
759 Multi-core scheduler support improves the CPU scheduler's decision
760 making when dealing with multi-core CPU chips at a cost of slightly
761 increased overhead in some places. If unsure say N here.
764 bool "SMT scheduler support"
766 Improves the CPU scheduler's decision making when dealing with
767 MultiThreading at a cost of slightly increased overhead in some
768 places. If unsure say N here.
771 int "Maximum number of CPUs (2-4096)"
773 # These have to remain sorted largest to smallest
777 bool "Support for hot-pluggable CPUs"
778 select GENERIC_IRQ_MIGRATION
780 Say Y here to experiment with turning CPUs off and on. CPUs
781 can be controlled through /sys/devices/system/cpu.
783 # Common NUMA Features
785 bool "Numa Memory Allocation and Scheduler Support"
786 select ACPI_NUMA if ACPI
789 Enable NUMA (Non Uniform Memory Access) support.
791 The kernel will try to allocate memory used by a CPU on the
792 local memory of the CPU and add some more
793 NUMA awareness to the kernel.
796 int "Maximum NUMA Nodes (as a power of 2)"
799 depends on NEED_MULTIPLE_NODES
801 Specify the maximum number of NUMA Nodes available on the target
802 system. Increases memory reserved to accommodate various tables.
804 config USE_PERCPU_NUMA_NODE_ID
808 config HAVE_SETUP_PER_CPU_AREA
812 config NEED_PER_CPU_EMBED_FIRST_CHUNK
819 source kernel/Kconfig.hz
821 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
824 config ARCH_HAS_HOLES_MEMORYMODEL
825 def_bool y if SPARSEMEM
827 config ARCH_SPARSEMEM_ENABLE
829 select SPARSEMEM_VMEMMAP_ENABLE
831 config ARCH_SPARSEMEM_DEFAULT
832 def_bool ARCH_SPARSEMEM_ENABLE
834 config ARCH_SELECT_MEMORY_MODEL
835 def_bool ARCH_SPARSEMEM_ENABLE
837 config ARCH_FLATMEM_ENABLE
840 config HAVE_ARCH_PFN_VALID
841 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
843 config HW_PERF_EVENTS
847 config SYS_SUPPORTS_HUGETLBFS
850 config ARCH_WANT_HUGE_PMD_SHARE
851 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
853 config ARCH_HAS_CACHE_LINE_SIZE
857 bool "Enable seccomp to safely compute untrusted bytecode"
859 This kernel feature is useful for number crunching applications
860 that may need to compute untrusted bytecode during their
861 execution. By using pipes or other transports made available to
862 the process as file descriptors supporting the read/write
863 syscalls, it's possible to isolate those applications in
864 their own address space using seccomp. Once seccomp is
865 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
866 and the task is only allowed to execute a few safe syscalls
867 defined by each seccomp mode.
870 bool "Enable paravirtualization code"
872 This changes the kernel so it can modify itself when it is run
873 under a hypervisor, potentially improving performance significantly
874 over full virtualization.
876 config PARAVIRT_TIME_ACCOUNTING
877 bool "Paravirtual steal time accounting"
881 Select this option to enable fine granularity task steal time
882 accounting. Time spent executing other tasks in parallel with
883 the current vCPU is discounted from the vCPU power. To account for
884 that, there can be a small performance impact.
886 If in doubt, say N here.
889 depends on PM_SLEEP_SMP
891 bool "kexec system call"
893 kexec is a system call that implements the ability to shutdown your
894 current kernel, and to start another kernel. It is like a reboot
895 but it is independent of the system firmware. And like a reboot
896 you can start any kernel with it, not just Linux.
899 bool "Build kdump crash kernel"
901 Generate crash dump after being started by kexec. This should
902 be normally only set in special crash dump kernels which are
903 loaded in the main kernel with kexec-tools into a specially
904 reserved region and then later executed after a crash by
907 For more details see Documentation/kdump/kdump.txt
914 bool "Xen guest support on ARM64"
915 depends on ARM64 && OF
919 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
921 config FORCE_MAX_ZONEORDER
923 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
924 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
927 The kernel memory allocator divides physically contiguous memory
928 blocks into "zones", where each zone is a power of two number of
929 pages. This option selects the largest power of two that the kernel
930 keeps in the memory allocator. If you need to allocate very large
931 blocks of physically contiguous memory, then you may need to
934 This config option is actually maximum order plus one. For example,
935 a value of 11 means that the largest free memory block is 2^10 pages.
937 We make sure that we can allocate upto a HugePage size for each configuration.
939 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
941 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
942 4M allocations matching the default size used by generic code.
944 config UNMAP_KERNEL_AT_EL0
945 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
948 Speculation attacks against some high-performance processors can
949 be used to bypass MMU permission checks and leak kernel data to
950 userspace. This can be defended against by unmapping the kernel
951 when running in userspace, mapping it back in on exception entry
952 via a trampoline page in the vector table.
956 config HARDEN_BRANCH_PREDICTOR
957 bool "Harden the branch predictor against aliasing attacks" if EXPERT
960 Speculation attacks against some high-performance processors rely on
961 being able to manipulate the branch predictor for a victim context by
962 executing aliasing branches in the attacker context. Such attacks
963 can be partially mitigated against by clearing internal branch
964 predictor state and limiting the prediction logic in some situations.
966 This config option will take CPU-specific actions to harden the
967 branch predictor against aliasing attacks and may rely on specific
968 instruction sequences or control bits being set by the system
973 config HARDEN_EL2_VECTORS
974 bool "Harden EL2 vector mapping against system register leak" if EXPERT
977 Speculation attacks against some high-performance processors can
978 be used to leak privileged information such as the vector base
979 register, resulting in a potential defeat of the EL2 layout
982 This config option will map the vectors to a fixed location,
983 independent of the EL2 code mapping, so that revealing VBAR_EL2
984 to an attacker does not give away any extra information. This
985 only gets enabled on affected CPUs.
990 bool "Speculative Store Bypass Disable" if EXPERT
993 This enables mitigation of the bypassing of previous stores
994 by speculative loads.
998 config MITIGATE_SPECTRE_BRANCH_HISTORY
999 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1002 Speculation attacks against some high-performance processors can
1003 make use of branch history to influence future speculation.
1004 When taking an exception from user-space, a sequence of branches
1005 or a firmware call overwrites the branch history.
1007 menuconfig ARMV8_DEPRECATED
1008 bool "Emulate deprecated/obsolete ARMv8 instructions"
1012 Legacy software support may require certain instructions
1013 that have been deprecated or obsoleted in the architecture.
1015 Enable this config to enable selective emulation of these
1022 config SWP_EMULATION
1023 bool "Emulate SWP/SWPB instructions"
1025 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1026 they are always undefined. Say Y here to enable software
1027 emulation of these instructions for userspace using LDXR/STXR.
1029 In some older versions of glibc [<=2.8] SWP is used during futex
1030 trylock() operations with the assumption that the code will not
1031 be preempted. This invalid assumption may be more likely to fail
1032 with SWP emulation enabled, leading to deadlock of the user
1035 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1036 on an external transaction monitoring block called a global
1037 monitor to maintain update atomicity. If your system does not
1038 implement a global monitor, this option can cause programs that
1039 perform SWP operations to uncached memory to deadlock.
1043 config CP15_BARRIER_EMULATION
1044 bool "Emulate CP15 Barrier instructions"
1046 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1047 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1048 strongly recommended to use the ISB, DSB, and DMB
1049 instructions instead.
1051 Say Y here to enable software emulation of these
1052 instructions for AArch32 userspace code. When this option is
1053 enabled, CP15 barrier usage is traced which can help
1054 identify software that needs updating.
1058 config SETEND_EMULATION
1059 bool "Emulate SETEND instruction"
1061 The SETEND instruction alters the data-endianness of the
1062 AArch32 EL0, and is deprecated in ARMv8.
1064 Say Y here to enable software emulation of the instruction
1065 for AArch32 userspace code.
1067 Note: All the cpus on the system must have mixed endian support at EL0
1068 for this feature to be enabled. If a new CPU - which doesn't support mixed
1069 endian - is hotplugged in after this feature has been enabled, there could
1070 be unexpected results in the applications.
1075 config ARM64_SW_TTBR0_PAN
1076 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1078 Enabling this option prevents the kernel from accessing
1079 user-space memory directly by pointing TTBR0_EL1 to a reserved
1080 zeroed area and reserved ASID. The user access routines
1081 restore the valid TTBR0_EL1 temporarily.
1083 menu "ARMv8.1 architectural features"
1085 config ARM64_HW_AFDBM
1086 bool "Support for hardware updates of the Access and Dirty page flags"
1089 The ARMv8.1 architecture extensions introduce support for
1090 hardware updates of the access and dirty information in page
1091 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1092 capable processors, accesses to pages with PTE_AF cleared will
1093 set this bit instead of raising an access flag fault.
1094 Similarly, writes to read-only pages with the DBM bit set will
1095 clear the read-only bit (AP[2]) instead of raising a
1098 Kernels built with this configuration option enabled continue
1099 to work on pre-ARMv8.1 hardware and the performance impact is
1100 minimal. If unsure, say Y.
1103 bool "Enable support for Privileged Access Never (PAN)"
1106 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1107 prevents the kernel or hypervisor from accessing user-space (EL0)
1110 Choosing this option will cause any unprotected (not using
1111 copy_to_user et al) memory access to fail with a permission fault.
1113 The feature is detected at runtime, and will remain as a 'nop'
1114 instruction if the cpu does not implement the feature.
1116 config ARM64_LSE_ATOMICS
1117 bool "Atomic instructions"
1120 As part of the Large System Extensions, ARMv8.1 introduces new
1121 atomic instructions that are designed specifically to scale in
1124 Say Y here to make use of these instructions for the in-kernel
1125 atomic routines. This incurs a small overhead on CPUs that do
1126 not support these instructions and requires the kernel to be
1127 built with binutils >= 2.25 in order for the new instructions
1131 bool "Enable support for Virtualization Host Extensions (VHE)"
1134 Virtualization Host Extensions (VHE) allow the kernel to run
1135 directly at EL2 (instead of EL1) on processors that support
1136 it. This leads to better performance for KVM, as they reduce
1137 the cost of the world switch.
1139 Selecting this option allows the VHE feature to be detected
1140 at runtime, and does not affect processors that do not
1141 implement this feature.
1145 menu "ARMv8.2 architectural features"
1148 bool "Enable support for User Access Override (UAO)"
1151 User Access Override (UAO; part of the ARMv8.2 Extensions)
1152 causes the 'unprivileged' variant of the load/store instructions to
1153 be overridden to be privileged.
1155 This option changes get_user() and friends to use the 'unprivileged'
1156 variant of the load/store instructions. This ensures that user-space
1157 really did have access to the supplied memory. When addr_limit is
1158 set to kernel memory the UAO bit will be set, allowing privileged
1159 access to kernel memory.
1161 Choosing this option will cause copy_to_user() et al to use user-space
1164 The feature is detected at runtime, the kernel will use the
1165 regular load/store instructions if the cpu does not implement the
1169 bool "Enable support for persistent memory"
1170 select ARCH_HAS_PMEM_API
1171 select ARCH_HAS_UACCESS_FLUSHCACHE
1173 Say Y to enable support for the persistent memory API based on the
1174 ARMv8.2 DCPoP feature.
1176 The feature is detected at runtime, and the kernel will use DC CVAC
1177 operations if DC CVAP is not supported (following the behaviour of
1178 DC CVAP itself if the system does not define a point of persistence).
1180 config ARM64_RAS_EXTN
1181 bool "Enable support for RAS CPU Extensions"
1184 CPUs that support the Reliability, Availability and Serviceability
1185 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1186 errors, classify them and report them to software.
1188 On CPUs with these extensions system software can use additional
1189 barriers to determine if faults are pending and read the
1190 classification from a new set of registers.
1192 Selecting this feature will allow the kernel to use these barriers
1193 and access the new registers if the system supports the extension.
1194 Platform RAS features may additionally depend on firmware support.
1199 bool "ARM Scalable Vector Extension support"
1201 depends on !KVM || ARM64_VHE
1203 The Scalable Vector Extension (SVE) is an extension to the AArch64
1204 execution state which complements and extends the SIMD functionality
1205 of the base architecture to support much larger vectors and to enable
1206 additional vectorisation opportunities.
1208 To enable use of this extension on CPUs that implement it, say Y.
1210 Note that for architectural reasons, firmware _must_ implement SVE
1211 support when running on SVE capable hardware. The required support
1214 * version 1.5 and later of the ARM Trusted Firmware
1215 * the AArch64 boot wrapper since commit 5e1261e08abf
1216 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1218 For other firmware implementations, consult the firmware documentation
1221 If you need the kernel to boot on SVE-capable hardware with broken
1222 firmware, you may need to say N here until you get your firmware
1223 fixed. Otherwise, you may experience firmware panics or lockups when
1224 booting the kernel. If unsure and you are not observing these
1225 symptoms, you should assume that it is safe to say Y.
1227 CPUs that support SVE are architecturally required to support the
1228 Virtualization Host Extensions (VHE), so the kernel makes no
1229 provision for supporting SVE alongside KVM without VHE enabled.
1230 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1231 KVM in the same kernel image.
1233 config ARM64_MODULE_PLTS
1235 select HAVE_MOD_ARCH_SPECIFIC
1240 This builds the kernel as a Position Independent Executable (PIE),
1241 which retains all relocation metadata required to relocate the
1242 kernel binary at runtime to a different virtual address than the
1243 address it was linked at.
1244 Since AArch64 uses the RELA relocation format, this requires a
1245 relocation pass at runtime even if the kernel is loaded at the
1246 same address it was linked at.
1248 config RANDOMIZE_BASE
1249 bool "Randomize the address of the kernel image"
1250 select ARM64_MODULE_PLTS if MODULES
1253 Randomizes the virtual address at which the kernel image is
1254 loaded, as a security feature that deters exploit attempts
1255 relying on knowledge of the location of kernel internals.
1257 It is the bootloader's job to provide entropy, by passing a
1258 random u64 value in /chosen/kaslr-seed at kernel entry.
1260 When booting via the UEFI stub, it will invoke the firmware's
1261 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1262 to the kernel proper. In addition, it will randomise the physical
1263 location of the kernel Image as well.
1267 config RANDOMIZE_MODULE_REGION_FULL
1268 bool "Randomize the module region over a 4 GB range"
1269 depends on RANDOMIZE_BASE
1272 Randomizes the location of the module region inside a 4 GB window
1273 covering the core kernel. This way, it is less likely for modules
1274 to leak information about the location of core kernel data structures
1275 but it does imply that function calls between modules and the core
1276 kernel will need to be resolved via veneers in the module PLT.
1278 When this option is not set, the module region will be randomized over
1279 a limited range that contains the [_stext, _etext] interval of the
1280 core kernel, so branch relocations are always in range.
1286 config ARM64_ACPI_PARKING_PROTOCOL
1287 bool "Enable support for the ARM64 ACPI parking protocol"
1290 Enable support for the ARM64 ACPI parking protocol. If disabled
1291 the kernel will not allow booting through the ARM64 ACPI parking
1292 protocol even if the corresponding data is present in the ACPI
1296 string "Default kernel command string"
1299 Provide a set of default command-line options at build time by
1300 entering them here. As a minimum, you should specify the the
1301 root device (e.g. root=/dev/nfs).
1303 config CMDLINE_FORCE
1304 bool "Always use the default kernel command string"
1306 Always use the default kernel command string, even if the boot
1307 loader passes other arguments to the kernel.
1308 This is useful if you cannot or don't want to change the
1309 command-line options your boot loader passes to the kernel.
1315 bool "UEFI runtime support"
1316 depends on OF && !CPU_BIG_ENDIAN
1317 depends on KERNEL_MODE_NEON
1318 select ARCH_SUPPORTS_ACPI
1321 select EFI_PARAMS_FROM_FDT
1322 select EFI_RUNTIME_WRAPPERS
1327 This option provides support for runtime services provided
1328 by UEFI firmware (such as non-volatile variables, realtime
1329 clock, and platform reset). A UEFI stub is also provided to
1330 allow the kernel to be booted as an EFI application. This
1331 is only useful on systems that have UEFI firmware.
1334 bool "Enable support for SMBIOS (DMI) tables"
1338 This enables SMBIOS/DMI feature for systems.
1340 This option is only useful on systems that have UEFI firmware.
1341 However, even with this option, the resultant kernel should
1342 continue to boot on existing non-UEFI platforms.
1347 bool "Kernel support for 32-bit EL0"
1348 depends on ARM64_4K_PAGES || EXPERT
1349 select COMPAT_BINFMT_ELF if BINFMT_ELF
1351 select OLD_SIGSUSPEND3
1352 select COMPAT_OLD_SIGACTION
1354 This option enables support for a 32-bit EL0 running under a 64-bit
1355 kernel at EL1. AArch32-specific components such as system calls,
1356 the user helper functions, VFP support and the ptrace interface are
1357 handled appropriately by the kernel.
1359 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1360 that you will only be able to execute AArch32 binaries that were compiled
1361 with page size aligned segments.
1363 If you want to execute 32-bit userspace applications, say Y.
1365 config SYSVIPC_COMPAT
1367 depends on COMPAT && SYSVIPC
1369 menu "Power management options"
1371 source "kernel/power/Kconfig"
1373 config ARCH_HIBERNATION_POSSIBLE
1377 config ARCH_HIBERNATION_HEADER
1379 depends on HIBERNATION
1381 config ARCH_SUSPEND_POSSIBLE
1386 menu "CPU Power Management"
1388 source "drivers/cpuidle/Kconfig"
1390 source "drivers/cpufreq/Kconfig"
1394 source "drivers/firmware/Kconfig"
1396 source "drivers/acpi/Kconfig"
1398 source "arch/arm64/kvm/Kconfig"
1401 source "arch/arm64/crypto/Kconfig"