3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
24 select BUILDTIME_EXTABLE_SORT
25 select CLONE_BACKWARDS
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS
31 select GENERIC_ALLOCATOR
32 select GENERIC_CLOCKEVENTS
33 select GENERIC_CLOCKEVENTS_BROADCAST
34 select GENERIC_CPU_AUTOPROBE
35 select GENERIC_EARLY_IOREMAP
36 select GENERIC_IDLE_POLL_SETUP
37 select GENERIC_IRQ_PROBE
38 select GENERIC_IRQ_SHOW
39 select GENERIC_IRQ_SHOW_LEVEL
40 select GENERIC_PCI_IOMAP
41 select GENERIC_SCHED_CLOCK
42 select GENERIC_SMP_IDLE_THREAD
43 select GENERIC_STRNCPY_FROM_USER
44 select GENERIC_STRNLEN_USER
45 select GENERIC_TIME_VSYSCALL
46 select HANDLE_DOMAIN_IRQ
47 select HARDIRQS_SW_RESEND
48 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
49 select HAVE_ARCH_AUDITSYSCALL
50 select HAVE_ARCH_BITREVERSE
51 select HAVE_ARCH_JUMP_LABEL
52 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
54 select HAVE_ARCH_SECCOMP_FILTER
55 select HAVE_ARCH_TRACEHOOK
58 select HAVE_C_RECORDMCOUNT
59 select HAVE_CC_STACKPROTECTOR
60 select HAVE_CMPXCHG_DOUBLE
61 select HAVE_CMPXCHG_LOCAL
62 select HAVE_DEBUG_BUGVERBOSE
63 select HAVE_DEBUG_KMEMLEAK
64 select HAVE_DMA_API_DEBUG
66 select HAVE_DMA_CONTIGUOUS
67 select HAVE_DYNAMIC_FTRACE
68 select HAVE_EFFICIENT_UNALIGNED_ACCESS
69 select HAVE_FTRACE_MCOUNT_RECORD
70 select HAVE_FUNCTION_TRACER
71 select HAVE_FUNCTION_GRAPH_TRACER
72 select HAVE_GENERIC_DMA_COHERENT
73 select HAVE_HW_BREAKPOINT if PERF_EVENTS
75 select HAVE_PATA_PLATFORM
76 select HAVE_PERF_EVENTS
78 select HAVE_PERF_USER_STACK_DUMP
79 select HAVE_RCU_TABLE_FREE
80 select HAVE_SYSCALL_TRACEPOINTS
81 select IOMMU_DMA if IOMMU_SUPPORT
83 select IRQ_FORCED_THREADING
84 select MODULES_USE_ELF_RELA
87 select OF_EARLY_FLATTREE
88 select OF_RESERVED_MEM
89 select PERF_USE_VMALLOC
93 select SYSCTL_EXCEPTION_TRACE
94 select HAVE_CONTEXT_TRACKING
97 ARM 64-bit (AArch64) Linux support.
102 config ARCH_PHYS_ADDR_T_64BIT
111 config STACKTRACE_SUPPORT
114 config ILLEGAL_POINTER_VALUE
116 default 0xdead000000000000
118 config LOCKDEP_SUPPORT
121 config TRACE_IRQFLAGS_SUPPORT
124 config RWSEM_XCHGADD_ALGORITHM
131 config GENERIC_BUG_RELATIVE_POINTERS
133 depends on GENERIC_BUG
135 config GENERIC_HWEIGHT
141 config GENERIC_CALIBRATE_DELAY
147 config HAVE_GENERIC_RCU_GUP
150 config ARCH_DMA_ADDR_T_64BIT
153 config NEED_DMA_MAP_STATE
156 config NEED_SG_DMA_LENGTH
168 config KERNEL_MODE_NEON
171 config FIX_EARLYCON_MEM
174 config PGTABLE_LEVELS
176 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
177 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
178 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
179 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
180 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
181 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
183 source "init/Kconfig"
185 source "kernel/Kconfig.freezer"
187 source "arch/arm64/Kconfig.platforms"
194 This feature enables support for PCI bus system. If you say Y
195 here, the kernel will include drivers and infrastructure code
196 to support PCI bus devices.
201 config PCI_DOMAINS_GENERIC
207 source "drivers/pci/Kconfig"
208 source "drivers/pci/pcie/Kconfig"
209 source "drivers/pci/hotplug/Kconfig"
213 menu "Kernel Features"
215 menu "ARM errata workarounds via the alternatives framework"
217 config ARM64_ERRATUM_826319
218 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
221 This option adds an alternative code sequence to work around ARM
222 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
223 AXI master interface and an L2 cache.
225 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
226 and is unable to accept a certain write via this interface, it will
227 not progress on read data presented on the read data channel and the
230 The workaround promotes data cache clean instructions to
231 data cache clean-and-invalidate.
232 Please note that this does not necessarily enable the workaround,
233 as it depends on the alternative framework, which will only patch
234 the kernel if an affected CPU is detected.
238 config ARM64_ERRATUM_827319
239 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
242 This option adds an alternative code sequence to work around ARM
243 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
244 master interface and an L2 cache.
246 Under certain conditions this erratum can cause a clean line eviction
247 to occur at the same time as another transaction to the same address
248 on the AMBA 5 CHI interface, which can cause data corruption if the
249 interconnect reorders the two transactions.
251 The workaround promotes data cache clean instructions to
252 data cache clean-and-invalidate.
253 Please note that this does not necessarily enable the workaround,
254 as it depends on the alternative framework, which will only patch
255 the kernel if an affected CPU is detected.
259 config ARM64_ERRATUM_824069
260 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
263 This option adds an alternative code sequence to work around ARM
264 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
265 to a coherent interconnect.
267 If a Cortex-A53 processor is executing a store or prefetch for
268 write instruction at the same time as a processor in another
269 cluster is executing a cache maintenance operation to the same
270 address, then this erratum might cause a clean cache line to be
271 incorrectly marked as dirty.
273 The workaround promotes data cache clean instructions to
274 data cache clean-and-invalidate.
275 Please note that this option does not necessarily enable the
276 workaround, as it depends on the alternative framework, which will
277 only patch the kernel if an affected CPU is detected.
281 config ARM64_ERRATUM_819472
282 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
285 This option adds an alternative code sequence to work around ARM
286 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
287 present when it is connected to a coherent interconnect.
289 If the processor is executing a load and store exclusive sequence at
290 the same time as a processor in another cluster is executing a cache
291 maintenance operation to the same address, then this erratum might
292 cause data corruption.
294 The workaround promotes data cache clean instructions to
295 data cache clean-and-invalidate.
296 Please note that this does not necessarily enable the workaround,
297 as it depends on the alternative framework, which will only patch
298 the kernel if an affected CPU is detected.
302 config ARM64_ERRATUM_832075
303 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
306 This option adds an alternative code sequence to work around ARM
307 erratum 832075 on Cortex-A57 parts up to r1p2.
309 Affected Cortex-A57 parts might deadlock when exclusive load/store
310 instructions to Write-Back memory are mixed with Device loads.
312 The workaround is to promote device loads to use Load-Acquire
314 Please note that this does not necessarily enable the workaround,
315 as it depends on the alternative framework, which will only patch
316 the kernel if an affected CPU is detected.
320 config ARM64_ERRATUM_834220
321 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
325 This option adds an alternative code sequence to work around ARM
326 erratum 834220 on Cortex-A57 parts up to r1p2.
328 Affected Cortex-A57 parts might report a Stage 2 translation
329 fault as the result of a Stage 1 fault for load crossing a
330 page boundary when there is a permission or device memory
331 alignment fault at Stage 1 and a translation fault at Stage 2.
333 The workaround is to verify that the Stage 1 translation
334 doesn't generate a fault before handling the Stage 2 fault.
335 Please note that this does not necessarily enable the workaround,
336 as it depends on the alternative framework, which will only patch
337 the kernel if an affected CPU is detected.
341 config ARM64_ERRATUM_845719
342 bool "Cortex-A53: 845719: a load might read incorrect data"
346 This option adds an alternative code sequence to work around ARM
347 erratum 845719 on Cortex-A53 parts up to r0p4.
349 When running a compat (AArch32) userspace on an affected Cortex-A53
350 part, a load at EL0 from a virtual address that matches the bottom 32
351 bits of the virtual address used by a recent load at (AArch64) EL1
352 might return incorrect data.
354 The workaround is to write the contextidr_el1 register on exception
355 return to a 32-bit task.
356 Please note that this does not necessarily enable the workaround,
357 as it depends on the alternative framework, which will only patch
358 the kernel if an affected CPU is detected.
362 config ARM64_ERRATUM_843419
363 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
367 This option builds kernel modules using the large memory model in
368 order to avoid the use of the ADRP instruction, which can cause
369 a subsequent memory access to use an incorrect address on Cortex-A53
372 Note that the kernel itself must be linked with a version of ld
373 which fixes potentially affected ADRP instructions through the
378 config ARM64_ERRATUM_1024718
379 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
382 This option adds work around for Arm Cortex-A55 Erratum 1024718.
384 Affected Cortex-A55 cores (all revisions) could cause incorrect
385 update of the hardware dirty bit when the DBM/AP bits are updated
386 without a break-before-make. The work around is to disable the usage
387 of hardware DBM locally on the affected cores. CPUs not affected by
388 erratum will continue to use the feature.
392 config CAVIUM_ERRATUM_22375
393 bool "Cavium erratum 22375, 24313"
396 Enable workaround for erratum 22375, 24313.
398 This implements two gicv3-its errata workarounds for ThunderX. Both
399 with small impact affecting only ITS table allocation.
401 erratum 22375: only alloc 8MB table size
402 erratum 24313: ignore memory access type
404 The fixes are in ITS initialization and basically ignore memory access
405 type and table size provided by the TYPER and BASER registers.
409 config CAVIUM_ERRATUM_23144
410 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
414 ITS SYNC command hang for cross node io and collections/cpu mapping.
418 config CAVIUM_ERRATUM_23154
419 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
422 The gicv3 of ThunderX requires a modified version for
423 reading the IAR status to ensure data synchronization
424 (access to icc_iar1_el1 is not sync'ed before and after).
428 config CAVIUM_ERRATUM_27456
429 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
432 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
433 instructions may cause the icache to become corrupted if it
434 contains data for a non-current ASID. The fix is to
435 invalidate the icache when changing the mm context.
444 default ARM64_4K_PAGES
446 Page size (translation granule) configuration.
448 config ARM64_4K_PAGES
451 This feature enables 4KB pages support.
453 config ARM64_16K_PAGES
456 The system will use 16KB pages support. AArch32 emulation
457 requires applications compiled with 16K (or a multiple of 16K)
460 config ARM64_64K_PAGES
463 This feature enables 64KB pages support (4KB by default)
464 allowing only two levels of page tables and faster TLB
465 look-up. AArch32 emulation requires applications compiled
466 with 64K aligned segments.
471 prompt "Virtual address space size"
472 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
473 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
474 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
476 Allows choosing one of multiple possible virtual address
477 space sizes. The level of translation table is determined by
478 a combination of page size and virtual address space size.
480 config ARM64_VA_BITS_36
481 bool "36-bit" if EXPERT
482 depends on ARM64_16K_PAGES
484 config ARM64_VA_BITS_39
486 depends on ARM64_4K_PAGES
488 config ARM64_VA_BITS_42
490 depends on ARM64_64K_PAGES
492 config ARM64_VA_BITS_47
494 depends on ARM64_16K_PAGES
496 config ARM64_VA_BITS_48
503 default 36 if ARM64_VA_BITS_36
504 default 39 if ARM64_VA_BITS_39
505 default 42 if ARM64_VA_BITS_42
506 default 47 if ARM64_VA_BITS_47
507 default 48 if ARM64_VA_BITS_48
509 config CPU_BIG_ENDIAN
510 bool "Build big-endian kernel"
512 Say Y if you plan on running a kernel in big-endian mode.
515 bool "Multi-core scheduler support"
517 Multi-core scheduler support improves the CPU scheduler's decision
518 making when dealing with multi-core CPU chips at a cost of slightly
519 increased overhead in some places. If unsure say N here.
522 bool "SMT scheduler support"
524 Improves the CPU scheduler's decision making when dealing with
525 MultiThreading at a cost of slightly increased overhead in some
526 places. If unsure say N here.
529 int "Maximum number of CPUs (2-4096)"
531 # These have to remain sorted largest to smallest
535 bool "Support for hot-pluggable CPUs"
536 select GENERIC_IRQ_MIGRATION
538 Say Y here to experiment with turning CPUs off and on. CPUs
539 can be controlled through /sys/devices/system/cpu.
541 source kernel/Kconfig.preempt
542 source kernel/Kconfig.hz
544 config ARCH_HAS_HOLES_MEMORYMODEL
545 def_bool y if SPARSEMEM
547 config ARCH_SPARSEMEM_ENABLE
549 select SPARSEMEM_VMEMMAP_ENABLE
551 config ARCH_SPARSEMEM_DEFAULT
552 def_bool ARCH_SPARSEMEM_ENABLE
554 config ARCH_SELECT_MEMORY_MODEL
555 def_bool ARCH_SPARSEMEM_ENABLE
557 config HAVE_ARCH_PFN_VALID
558 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
560 config HW_PERF_EVENTS
564 config SYS_SUPPORTS_HUGETLBFS
567 config ARCH_WANT_GENERAL_HUGETLB
570 config ARCH_WANT_HUGE_PMD_SHARE
571 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
573 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
576 config ARCH_HAS_CACHE_LINE_SIZE
582 bool "Enable seccomp to safely compute untrusted bytecode"
584 This kernel feature is useful for number crunching applications
585 that may need to compute untrusted bytecode during their
586 execution. By using pipes or other transports made available to
587 the process as file descriptors supporting the read/write
588 syscalls, it's possible to isolate those applications in
589 their own address space using seccomp. Once seccomp is
590 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
591 and the task is only allowed to execute a few safe syscalls
592 defined by each seccomp mode.
599 bool "Xen guest support on ARM64"
600 depends on ARM64 && OF
603 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
605 config FORCE_MAX_ZONEORDER
607 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
608 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
611 The kernel memory allocator divides physically contiguous memory
612 blocks into "zones", where each zone is a power of two number of
613 pages. This option selects the largest power of two that the kernel
614 keeps in the memory allocator. If you need to allocate very large
615 blocks of physically contiguous memory, then you may need to
618 This config option is actually maximum order plus one. For example,
619 a value of 11 means that the largest free memory block is 2^10 pages.
621 We make sure that we can allocate upto a HugePage size for each configuration.
623 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
625 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
626 4M allocations matching the default size used by generic code.
628 menuconfig ARMV8_DEPRECATED
629 bool "Emulate deprecated/obsolete ARMv8 instructions"
632 Legacy software support may require certain instructions
633 that have been deprecated or obsoleted in the architecture.
635 Enable this config to enable selective emulation of these
643 bool "Emulate SWP/SWPB instructions"
645 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
646 they are always undefined. Say Y here to enable software
647 emulation of these instructions for userspace using LDXR/STXR.
649 In some older versions of glibc [<=2.8] SWP is used during futex
650 trylock() operations with the assumption that the code will not
651 be preempted. This invalid assumption may be more likely to fail
652 with SWP emulation enabled, leading to deadlock of the user
655 NOTE: when accessing uncached shared regions, LDXR/STXR rely
656 on an external transaction monitoring block called a global
657 monitor to maintain update atomicity. If your system does not
658 implement a global monitor, this option can cause programs that
659 perform SWP operations to uncached memory to deadlock.
663 config CP15_BARRIER_EMULATION
664 bool "Emulate CP15 Barrier instructions"
666 The CP15 barrier instructions - CP15ISB, CP15DSB, and
667 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
668 strongly recommended to use the ISB, DSB, and DMB
669 instructions instead.
671 Say Y here to enable software emulation of these
672 instructions for AArch32 userspace code. When this option is
673 enabled, CP15 barrier usage is traced which can help
674 identify software that needs updating.
678 config SETEND_EMULATION
679 bool "Emulate SETEND instruction"
681 The SETEND instruction alters the data-endianness of the
682 AArch32 EL0, and is deprecated in ARMv8.
684 Say Y here to enable software emulation of the instruction
685 for AArch32 userspace code.
687 Note: All the cpus on the system must have mixed endian support at EL0
688 for this feature to be enabled. If a new CPU - which doesn't support mixed
689 endian - is hotplugged in after this feature has been enabled, there could
690 be unexpected results in the applications.
695 menu "ARMv8.1 architectural features"
697 config ARM64_HW_AFDBM
698 bool "Support for hardware updates of the Access and Dirty page flags"
701 The ARMv8.1 architecture extensions introduce support for
702 hardware updates of the access and dirty information in page
703 table entries. When enabled in TCR_EL1 (HA and HD bits) on
704 capable processors, accesses to pages with PTE_AF cleared will
705 set this bit instead of raising an access flag fault.
706 Similarly, writes to read-only pages with the DBM bit set will
707 clear the read-only bit (AP[2]) instead of raising a
710 Kernels built with this configuration option enabled continue
711 to work on pre-ARMv8.1 hardware and the performance impact is
712 minimal. If unsure, say Y.
715 bool "Enable support for Privileged Access Never (PAN)"
718 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
719 prevents the kernel or hypervisor from accessing user-space (EL0)
722 Choosing this option will cause any unprotected (not using
723 copy_to_user et al) memory access to fail with a permission fault.
725 The feature is detected at runtime, and will remain as a 'nop'
726 instruction if the cpu does not implement the feature.
728 config ARM64_LSE_ATOMICS
729 bool "Atomic instructions"
731 As part of the Large System Extensions, ARMv8.1 introduces new
732 atomic instructions that are designed specifically to scale in
735 Say Y here to make use of these instructions for the in-kernel
736 atomic routines. This incurs a small overhead on CPUs that do
737 not support these instructions and requires the kernel to be
738 built with binutils >= 2.25.
747 string "Default kernel command string"
750 Provide a set of default command-line options at build time by
751 entering them here. As a minimum, you should specify the the
752 root device (e.g. root=/dev/nfs).
755 bool "Always use the default kernel command string"
757 Always use the default kernel command string, even if the boot
758 loader passes other arguments to the kernel.
759 This is useful if you cannot or don't want to change the
760 command-line options your boot loader passes to the kernel.
766 bool "UEFI runtime support"
767 depends on OF && !CPU_BIG_ENDIAN
770 select EFI_PARAMS_FROM_FDT
771 select EFI_RUNTIME_WRAPPERS
776 This option provides support for runtime services provided
777 by UEFI firmware (such as non-volatile variables, realtime
778 clock, and platform reset). A UEFI stub is also provided to
779 allow the kernel to be booted as an EFI application. This
780 is only useful on systems that have UEFI firmware.
783 bool "Enable support for SMBIOS (DMI) tables"
787 This enables SMBIOS/DMI feature for systems.
789 This option is only useful on systems that have UEFI firmware.
790 However, even with this option, the resultant kernel should
791 continue to boot on existing non-UEFI platforms.
795 menu "Userspace binary formats"
797 source "fs/Kconfig.binfmt"
800 bool "Kernel support for 32-bit EL0"
801 depends on ARM64_4K_PAGES || EXPERT
802 select COMPAT_BINFMT_ELF if BINFMT_ELF
804 select OLD_SIGSUSPEND3
805 select COMPAT_OLD_SIGACTION
807 This option enables support for a 32-bit EL0 running under a 64-bit
808 kernel at EL1. AArch32-specific components such as system calls,
809 the user helper functions, VFP support and the ptrace interface are
810 handled appropriately by the kernel.
812 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
813 that you will only be able to execute AArch32 binaries that were compiled
814 with page size aligned segments.
816 If you want to execute 32-bit userspace applications, say Y.
818 config SYSVIPC_COMPAT
820 depends on COMPAT && SYSVIPC
824 depends on COMPAT && KEYS
828 menu "Power management options"
830 source "kernel/power/Kconfig"
832 config ARCH_SUSPEND_POSSIBLE
837 menu "CPU Power Management"
839 source "drivers/cpuidle/Kconfig"
841 source "drivers/cpufreq/Kconfig"
847 source "drivers/Kconfig"
849 source "drivers/firmware/Kconfig"
851 source "drivers/acpi/Kconfig"
855 source "arch/arm64/kvm/Kconfig"
857 source "arch/arm64/Kconfig.debug"
859 source "security/Kconfig"
861 source "crypto/Kconfig"
863 source "arch/arm64/crypto/Kconfig"