1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_EXTRA_PHDRS
14 select ARCH_BINFMT_ELF_STATE
15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
17 select ARCH_ENABLE_MEMORY_HOTPLUG
18 select ARCH_ENABLE_MEMORY_HOTREMOVE
19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
21 select ARCH_HAS_CACHE_LINE_SIZE
22 select ARCH_HAS_CURRENT_STACK_POINTER
23 select ARCH_HAS_DEBUG_VIRTUAL
24 select ARCH_HAS_DEBUG_VM_PGTABLE
25 select ARCH_HAS_DMA_PREP_COHERENT
26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
27 select ARCH_HAS_FAST_MULTIPLIER
28 select ARCH_HAS_FORTIFY_SOURCE
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_HAS_GIGANTIC_PAGE
32 select ARCH_HAS_KEEPINITRD
33 select ARCH_HAS_MEMBARRIER_SYNC_CORE
34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
35 select ARCH_HAS_PTE_DEVMAP
36 select ARCH_HAS_PTE_SPECIAL
37 select ARCH_HAS_SETUP_DMA_OPS
38 select ARCH_HAS_SET_DIRECT_MAP
39 select ARCH_HAS_SET_MEMORY
41 select ARCH_HAS_STRICT_KERNEL_RWX
42 select ARCH_HAS_STRICT_MODULE_RWX
43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
44 select ARCH_HAS_SYNC_DMA_FOR_CPU
45 select ARCH_HAS_SYSCALL_WRAPPER
46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
48 select ARCH_HAS_ZONE_DMA_SET if EXPERT
49 select ARCH_HAVE_ELF_PROT
50 select ARCH_HAVE_NMI_SAFE_CMPXCHG
51 select ARCH_HAVE_TRACE_MMIO_ACCESS
52 select ARCH_INLINE_READ_LOCK if !PREEMPTION
53 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
54 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
56 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
57 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
60 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
61 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
64 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
65 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
68 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
69 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
70 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
74 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
75 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
78 select ARCH_KEEP_MEMBLOCK
79 select ARCH_USE_CMPXCHG_LOCKREF
80 select ARCH_USE_GNU_PROPERTY
81 select ARCH_USE_MEMTEST
82 select ARCH_USE_QUEUED_RWLOCKS
83 select ARCH_USE_QUEUED_SPINLOCKS
84 select ARCH_USE_SYM_ANNOTATIONS
85 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
86 select ARCH_SUPPORTS_HUGETLBFS
87 select ARCH_SUPPORTS_MEMORY_FAILURE
88 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
89 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
90 select ARCH_SUPPORTS_LTO_CLANG_THIN
91 select ARCH_SUPPORTS_CFI_CLANG
92 select ARCH_SUPPORTS_ATOMIC_RMW
93 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
94 select ARCH_SUPPORTS_NUMA_BALANCING
95 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
96 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
97 select ARCH_WANT_DEFAULT_BPF_JIT
98 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
99 select ARCH_WANT_FRAME_POINTERS
100 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
101 select ARCH_WANT_LD_ORPHAN_WARN
102 select ARCH_WANTS_NO_INSTR
103 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
104 select ARCH_HAS_UBSAN_SANITIZE_ALL
106 select ARM_ARCH_TIMER
108 select AUDIT_ARCH_COMPAT_GENERIC
109 select ARM_GIC_V2M if PCI
111 select ARM_GIC_V3_ITS if PCI
113 select BUILDTIME_TABLE_SORT
114 select CLONE_BACKWARDS
116 select CPU_PM if (SUSPEND || CPU_IDLE)
118 select DCACHE_WORD_ACCESS
119 select DMA_DIRECT_REMAP
122 select GENERIC_ALLOCATOR
123 select GENERIC_ARCH_TOPOLOGY
124 select GENERIC_CLOCKEVENTS_BROADCAST
125 select GENERIC_CPU_AUTOPROBE
126 select GENERIC_CPU_VULNERABILITIES
127 select GENERIC_EARLY_IOREMAP
128 select GENERIC_IDLE_POLL_SETUP
129 select GENERIC_IOREMAP
130 select GENERIC_IRQ_IPI
131 select GENERIC_IRQ_PROBE
132 select GENERIC_IRQ_SHOW
133 select GENERIC_IRQ_SHOW_LEVEL
134 select GENERIC_LIB_DEVMEM_IS_ALLOWED
135 select GENERIC_PCI_IOMAP
136 select GENERIC_PTDUMP
137 select GENERIC_SCHED_CLOCK
138 select GENERIC_SMP_IDLE_THREAD
139 select GENERIC_TIME_VSYSCALL
140 select GENERIC_GETTIMEOFDAY
141 select GENERIC_VDSO_TIME_NS
142 select HARDIRQS_SW_RESEND
146 select HAVE_ACPI_APEI if (ACPI && EFI)
147 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
148 select HAVE_ARCH_AUDITSYSCALL
149 select HAVE_ARCH_BITREVERSE
150 select HAVE_ARCH_COMPILER_H
151 select HAVE_ARCH_HUGE_VMALLOC
152 select HAVE_ARCH_HUGE_VMAP
153 select HAVE_ARCH_JUMP_LABEL
154 select HAVE_ARCH_JUMP_LABEL_RELATIVE
155 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
156 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
157 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
158 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
159 # Some instrumentation may be unsound, hence EXPERT
160 select HAVE_ARCH_KCSAN if EXPERT
161 select HAVE_ARCH_KFENCE
162 select HAVE_ARCH_KGDB
163 select HAVE_ARCH_MMAP_RND_BITS
164 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
165 select HAVE_ARCH_PREL32_RELOCATIONS
166 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
167 select HAVE_ARCH_SECCOMP_FILTER
168 select HAVE_ARCH_STACKLEAK
169 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
170 select HAVE_ARCH_TRACEHOOK
171 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
172 select HAVE_ARCH_VMAP_STACK
173 select HAVE_ARM_SMCCC
174 select HAVE_ASM_MODVERSIONS
176 select HAVE_C_RECORDMCOUNT
177 select HAVE_CMPXCHG_DOUBLE
178 select HAVE_CMPXCHG_LOCAL
179 select HAVE_CONTEXT_TRACKING_USER
180 select HAVE_DEBUG_KMEMLEAK
181 select HAVE_DMA_CONTIGUOUS
182 select HAVE_DYNAMIC_FTRACE
183 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
184 if DYNAMIC_FTRACE_WITH_REGS
185 select HAVE_EFFICIENT_UNALIGNED_ACCESS
187 select HAVE_FTRACE_MCOUNT_RECORD
188 select HAVE_FUNCTION_TRACER
189 select HAVE_FUNCTION_ERROR_INJECTION
190 select HAVE_FUNCTION_GRAPH_TRACER
191 select HAVE_GCC_PLUGINS
192 select HAVE_HW_BREAKPOINT if PERF_EVENTS
193 select HAVE_IOREMAP_PROT
194 select HAVE_IRQ_TIME_ACCOUNTING
197 select HAVE_PERF_EVENTS
198 select HAVE_PERF_REGS
199 select HAVE_PERF_USER_STACK_DUMP
200 select HAVE_PREEMPT_DYNAMIC_KEY
201 select HAVE_REGS_AND_STACK_ACCESS_API
202 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
203 select HAVE_FUNCTION_ARG_ACCESS_API
204 select MMU_GATHER_RCU_TABLE_FREE
206 select HAVE_STACKPROTECTOR
207 select HAVE_SYSCALL_TRACEPOINTS
209 select HAVE_KRETPROBES
210 select HAVE_GENERIC_VDSO
212 select IRQ_FORCED_THREADING
213 select KASAN_VMALLOC if KASAN
214 select LOCK_MM_AND_FIND_VMA
215 select MODULES_USE_ELF_RELA
216 select NEED_DMA_MAP_STATE
217 select NEED_SG_DMA_LENGTH
219 select OF_EARLY_FLATTREE
220 select PCI_DOMAINS_GENERIC if PCI
221 select PCI_ECAM if (ACPI && PCI)
222 select PCI_SYSCALL if PCI
227 select SYSCTL_EXCEPTION_TRACE
228 select THREAD_INFO_IN_TASK
229 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
230 select TRACE_IRQFLAGS_SUPPORT
231 select TRACE_IRQFLAGS_NMI_SUPPORT
232 select HAVE_SOFTIRQ_ON_OWN_STACK
234 ARM 64-bit (AArch64) Linux support.
236 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
238 # https://github.com/ClangBuiltLinux/linux/issues/1507
239 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
240 select HAVE_DYNAMIC_FTRACE_WITH_REGS
242 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
244 depends on $(cc-option,-fpatchable-function-entry=2)
245 select HAVE_DYNAMIC_FTRACE_WITH_REGS
253 config ARM64_PAGE_SHIFT
255 default 16 if ARM64_64K_PAGES
256 default 14 if ARM64_16K_PAGES
259 config ARM64_CONT_PTE_SHIFT
261 default 5 if ARM64_64K_PAGES
262 default 7 if ARM64_16K_PAGES
265 config ARM64_CONT_PMD_SHIFT
267 default 5 if ARM64_64K_PAGES
268 default 5 if ARM64_16K_PAGES
271 config ARCH_MMAP_RND_BITS_MIN
272 default 14 if ARM64_64K_PAGES
273 default 16 if ARM64_16K_PAGES
276 # max bits determined by the following formula:
277 # VA_BITS - PAGE_SHIFT - 3
278 config ARCH_MMAP_RND_BITS_MAX
279 default 19 if ARM64_VA_BITS=36
280 default 24 if ARM64_VA_BITS=39
281 default 27 if ARM64_VA_BITS=42
282 default 30 if ARM64_VA_BITS=47
283 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
284 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
285 default 33 if ARM64_VA_BITS=48
286 default 14 if ARM64_64K_PAGES
287 default 16 if ARM64_16K_PAGES
290 config ARCH_MMAP_RND_COMPAT_BITS_MIN
291 default 7 if ARM64_64K_PAGES
292 default 9 if ARM64_16K_PAGES
295 config ARCH_MMAP_RND_COMPAT_BITS_MAX
301 config STACKTRACE_SUPPORT
304 config ILLEGAL_POINTER_VALUE
306 default 0xdead000000000000
308 config LOCKDEP_SUPPORT
315 config GENERIC_BUG_RELATIVE_POINTERS
317 depends on GENERIC_BUG
319 config GENERIC_HWEIGHT
325 config GENERIC_CALIBRATE_DELAY
328 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
334 config KERNEL_MODE_NEON
337 config FIX_EARLYCON_MEM
340 config PGTABLE_LEVELS
342 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
343 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
344 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
345 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
346 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
347 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
349 config ARCH_SUPPORTS_UPROBES
352 config ARCH_PROC_KCORE_TEXT
355 config BROKEN_GAS_INST
356 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
358 config KASAN_SHADOW_OFFSET
360 depends on KASAN_GENERIC || KASAN_SW_TAGS
361 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
362 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
363 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
364 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
365 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
366 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
367 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
368 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
369 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
370 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
371 default 0xffffffffffffffff
373 source "arch/arm64/Kconfig.platforms"
375 menu "Kernel Features"
377 menu "ARM errata workarounds via the alternatives framework"
379 config AMPERE_ERRATUM_AC03_CPU_38
380 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics"
383 This option adds an alternative code sequence to work around Ampere
384 erratum AC03_CPU_38 on AmpereOne.
386 The affected design reports FEAT_HAFDBS as not implemented in
387 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0
388 as required by the architecture. The unadvertised HAFDBS
389 implementation suffers from an additional erratum where hardware
390 A/D updates can occur after a PTE has been marked invalid.
392 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
393 which avoids enabling unadvertised hardware Access Flag management
398 config ARM64_WORKAROUND_CLEAN_CACHE
401 config ARM64_ERRATUM_826319
402 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
404 select ARM64_WORKAROUND_CLEAN_CACHE
406 This option adds an alternative code sequence to work around ARM
407 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
408 AXI master interface and an L2 cache.
410 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
411 and is unable to accept a certain write via this interface, it will
412 not progress on read data presented on the read data channel and the
415 The workaround promotes data cache clean instructions to
416 data cache clean-and-invalidate.
417 Please note that this does not necessarily enable the workaround,
418 as it depends on the alternative framework, which will only patch
419 the kernel if an affected CPU is detected.
423 config ARM64_ERRATUM_827319
424 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
426 select ARM64_WORKAROUND_CLEAN_CACHE
428 This option adds an alternative code sequence to work around ARM
429 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
430 master interface and an L2 cache.
432 Under certain conditions this erratum can cause a clean line eviction
433 to occur at the same time as another transaction to the same address
434 on the AMBA 5 CHI interface, which can cause data corruption if the
435 interconnect reorders the two transactions.
437 The workaround promotes data cache clean instructions to
438 data cache clean-and-invalidate.
439 Please note that this does not necessarily enable the workaround,
440 as it depends on the alternative framework, which will only patch
441 the kernel if an affected CPU is detected.
445 config ARM64_ERRATUM_824069
446 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
448 select ARM64_WORKAROUND_CLEAN_CACHE
450 This option adds an alternative code sequence to work around ARM
451 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
452 to a coherent interconnect.
454 If a Cortex-A53 processor is executing a store or prefetch for
455 write instruction at the same time as a processor in another
456 cluster is executing a cache maintenance operation to the same
457 address, then this erratum might cause a clean cache line to be
458 incorrectly marked as dirty.
460 The workaround promotes data cache clean instructions to
461 data cache clean-and-invalidate.
462 Please note that this option does not necessarily enable the
463 workaround, as it depends on the alternative framework, which will
464 only patch the kernel if an affected CPU is detected.
468 config ARM64_ERRATUM_819472
469 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
471 select ARM64_WORKAROUND_CLEAN_CACHE
473 This option adds an alternative code sequence to work around ARM
474 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
475 present when it is connected to a coherent interconnect.
477 If the processor is executing a load and store exclusive sequence at
478 the same time as a processor in another cluster is executing a cache
479 maintenance operation to the same address, then this erratum might
480 cause data corruption.
482 The workaround promotes data cache clean instructions to
483 data cache clean-and-invalidate.
484 Please note that this does not necessarily enable the workaround,
485 as it depends on the alternative framework, which will only patch
486 the kernel if an affected CPU is detected.
490 config ARM64_ERRATUM_832075
491 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
494 This option adds an alternative code sequence to work around ARM
495 erratum 832075 on Cortex-A57 parts up to r1p2.
497 Affected Cortex-A57 parts might deadlock when exclusive load/store
498 instructions to Write-Back memory are mixed with Device loads.
500 The workaround is to promote device loads to use Load-Acquire
502 Please note that this does not necessarily enable the workaround,
503 as it depends on the alternative framework, which will only patch
504 the kernel if an affected CPU is detected.
508 config ARM64_ERRATUM_834220
509 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
513 This option adds an alternative code sequence to work around ARM
514 erratum 834220 on Cortex-A57 parts up to r1p2.
516 Affected Cortex-A57 parts might report a Stage 2 translation
517 fault as the result of a Stage 1 fault for load crossing a
518 page boundary when there is a permission or device memory
519 alignment fault at Stage 1 and a translation fault at Stage 2.
521 The workaround is to verify that the Stage 1 translation
522 doesn't generate a fault before handling the Stage 2 fault.
523 Please note that this does not necessarily enable the workaround,
524 as it depends on the alternative framework, which will only patch
525 the kernel if an affected CPU is detected.
529 config ARM64_ERRATUM_1742098
530 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
534 This option removes the AES hwcap for aarch32 user-space to
535 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
537 Affected parts may corrupt the AES state if an interrupt is
538 taken between a pair of AES instructions. These instructions
539 are only present if the cryptography extensions are present.
540 All software should have a fallback implementation for CPUs
541 that don't implement the cryptography extensions.
545 config ARM64_ERRATUM_845719
546 bool "Cortex-A53: 845719: a load might read incorrect data"
550 This option adds an alternative code sequence to work around ARM
551 erratum 845719 on Cortex-A53 parts up to r0p4.
553 When running a compat (AArch32) userspace on an affected Cortex-A53
554 part, a load at EL0 from a virtual address that matches the bottom 32
555 bits of the virtual address used by a recent load at (AArch64) EL1
556 might return incorrect data.
558 The workaround is to write the contextidr_el1 register on exception
559 return to a 32-bit task.
560 Please note that this does not necessarily enable the workaround,
561 as it depends on the alternative framework, which will only patch
562 the kernel if an affected CPU is detected.
566 config ARM64_ERRATUM_843419
567 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
569 select ARM64_MODULE_PLTS if MODULES
571 This option links the kernel with '--fix-cortex-a53-843419' and
572 enables PLT support to replace certain ADRP instructions, which can
573 cause subsequent memory accesses to use an incorrect address on
574 Cortex-A53 parts up to r0p4.
578 config ARM64_LD_HAS_FIX_ERRATUM_843419
579 def_bool $(ld-option,--fix-cortex-a53-843419)
581 config ARM64_ERRATUM_1024718
582 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
585 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
587 Affected Cortex-A55 cores (all revisions) could cause incorrect
588 update of the hardware dirty bit when the DBM/AP bits are updated
589 without a break-before-make. The workaround is to disable the usage
590 of hardware DBM locally on the affected cores. CPUs not affected by
591 this erratum will continue to use the feature.
595 config ARM64_ERRATUM_1418040
596 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
600 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
601 errata 1188873 and 1418040.
603 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
604 cause register corruption when accessing the timer registers
605 from AArch32 userspace.
609 config ARM64_WORKAROUND_SPECULATIVE_AT
612 config ARM64_ERRATUM_1165522
613 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
615 select ARM64_WORKAROUND_SPECULATIVE_AT
617 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
619 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
620 corrupted TLBs by speculating an AT instruction during a guest
625 config ARM64_ERRATUM_1319367
626 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
628 select ARM64_WORKAROUND_SPECULATIVE_AT
630 This option adds work arounds for ARM Cortex-A57 erratum 1319537
631 and A72 erratum 1319367
633 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
634 speculating an AT instruction during a guest context switch.
638 config ARM64_ERRATUM_1530923
639 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
641 select ARM64_WORKAROUND_SPECULATIVE_AT
643 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
645 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
646 corrupted TLBs by speculating an AT instruction during a guest
651 config ARM64_WORKAROUND_REPEAT_TLBI
654 config ARM64_ERRATUM_2441007
655 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
657 select ARM64_WORKAROUND_REPEAT_TLBI
659 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
661 Under very rare circumstances, affected Cortex-A55 CPUs
662 may not handle a race between a break-before-make sequence on one
663 CPU, and another CPU accessing the same page. This could allow a
664 store to a page that has been unmapped.
666 Work around this by adding the affected CPUs to the list that needs
667 TLB sequences to be done twice.
671 config ARM64_ERRATUM_1286807
672 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
674 select ARM64_WORKAROUND_REPEAT_TLBI
676 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
678 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
679 address for a cacheable mapping of a location is being
680 accessed by a core while another core is remapping the virtual
681 address to a new physical page using the recommended
682 break-before-make sequence, then under very rare circumstances
683 TLBI+DSB completes before a read using the translation being
684 invalidated has been observed by other observers. The
685 workaround repeats the TLBI+DSB operation.
687 config ARM64_ERRATUM_1463225
688 bool "Cortex-A76: Software Step might prevent interrupt recognition"
691 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
693 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
694 of a system call instruction (SVC) can prevent recognition of
695 subsequent interrupts when software stepping is disabled in the
696 exception handler of the system call and either kernel debugging
697 is enabled or VHE is in use.
699 Work around the erratum by triggering a dummy step exception
700 when handling a system call from a task that is being stepped
701 in a VHE configuration of the kernel.
705 config ARM64_ERRATUM_1542419
706 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
709 This option adds a workaround for ARM Neoverse-N1 erratum
712 Affected Neoverse-N1 cores could execute a stale instruction when
713 modified by another CPU. The workaround depends on a firmware
716 Workaround the issue by hiding the DIC feature from EL0. This
717 forces user-space to perform cache maintenance.
721 config ARM64_ERRATUM_1508412
722 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
725 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
727 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
728 of a store-exclusive or read of PAR_EL1 and a load with device or
729 non-cacheable memory attributes. The workaround depends on a firmware
732 KVM guests must also have the workaround implemented or they can
735 Work around the issue by inserting DMB SY barriers around PAR_EL1
736 register reads and warning KVM users. The DMB barrier is sufficient
737 to prevent a speculative PAR_EL1 read.
741 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
744 config ARM64_ERRATUM_2051678
745 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
748 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
749 Affected Cortex-A510 might not respect the ordering rules for
750 hardware update of the page table's dirty bit. The workaround
751 is to not enable the feature on affected CPUs.
755 config ARM64_ERRATUM_2077057
756 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
759 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
760 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
761 expected, but a Pointer Authentication trap is taken instead. The
762 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
763 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
765 This can only happen when EL2 is stepping EL1.
767 When these conditions occur, the SPSR_EL2 value is unchanged from the
768 previous guest entry, and can be restored from the in-memory copy.
772 config ARM64_ERRATUM_2658417
773 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
776 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
777 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
778 BFMMLA or VMMLA instructions in rare circumstances when a pair of
779 A510 CPUs are using shared neon hardware. As the sharing is not
780 discoverable by the kernel, hide the BF16 HWCAP to indicate that
781 user-space should not be using these instructions.
785 config ARM64_ERRATUM_2119858
786 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
788 depends on CORESIGHT_TRBE
789 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
791 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
793 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
794 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
795 the event of a WRAP event.
797 Work around the issue by always making sure we move the TRBPTR_EL1 by
798 256 bytes before enabling the buffer and filling the first 256 bytes of
799 the buffer with ETM ignore packets upon disabling.
803 config ARM64_ERRATUM_2139208
804 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
806 depends on CORESIGHT_TRBE
807 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
809 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
811 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
812 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
813 the event of a WRAP event.
815 Work around the issue by always making sure we move the TRBPTR_EL1 by
816 256 bytes before enabling the buffer and filling the first 256 bytes of
817 the buffer with ETM ignore packets upon disabling.
821 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
824 config ARM64_ERRATUM_2054223
825 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
827 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
829 Enable workaround for ARM Cortex-A710 erratum 2054223
831 Affected cores may fail to flush the trace data on a TSB instruction, when
832 the PE is in trace prohibited state. This will cause losing a few bytes
835 Workaround is to issue two TSB consecutively on affected cores.
839 config ARM64_ERRATUM_2067961
840 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
842 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
844 Enable workaround for ARM Neoverse-N2 erratum 2067961
846 Affected cores may fail to flush the trace data on a TSB instruction, when
847 the PE is in trace prohibited state. This will cause losing a few bytes
850 Workaround is to issue two TSB consecutively on affected cores.
854 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
857 config ARM64_ERRATUM_2253138
858 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
859 depends on CORESIGHT_TRBE
861 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
863 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
865 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
866 for TRBE. Under some conditions, the TRBE might generate a write to the next
867 virtually addressed page following the last page of the TRBE address space
868 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
870 Work around this in the driver by always making sure that there is a
871 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
875 config ARM64_ERRATUM_2224489
876 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
877 depends on CORESIGHT_TRBE
879 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
881 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
883 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
884 for TRBE. Under some conditions, the TRBE might generate a write to the next
885 virtually addressed page following the last page of the TRBE address space
886 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
888 Work around this in the driver by always making sure that there is a
889 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
893 config ARM64_ERRATUM_2441009
894 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
896 select ARM64_WORKAROUND_REPEAT_TLBI
898 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
900 Under very rare circumstances, affected Cortex-A510 CPUs
901 may not handle a race between a break-before-make sequence on one
902 CPU, and another CPU accessing the same page. This could allow a
903 store to a page that has been unmapped.
905 Work around this by adding the affected CPUs to the list that needs
906 TLB sequences to be done twice.
910 config ARM64_ERRATUM_2064142
911 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
912 depends on CORESIGHT_TRBE
915 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
917 Affected Cortex-A510 core might fail to write into system registers after the
918 TRBE has been disabled. Under some conditions after the TRBE has been disabled
919 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
920 and TRBTRG_EL1 will be ignored and will not be effected.
922 Work around this in the driver by executing TSB CSYNC and DSB after collection
923 is stopped and before performing a system register write to one of the affected
928 config ARM64_ERRATUM_2038923
929 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
930 depends on CORESIGHT_TRBE
933 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
935 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
936 prohibited within the CPU. As a result, the trace buffer or trace buffer state
937 might be corrupted. This happens after TRBE buffer has been enabled by setting
938 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
939 execution changes from a context, in which trace is prohibited to one where it
940 isn't, or vice versa. In these mentioned conditions, the view of whether trace
941 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
942 the trace buffer state might be corrupted.
944 Work around this in the driver by preventing an inconsistent view of whether the
945 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
946 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
947 two ISB instructions if no ERET is to take place.
951 config ARM64_ERRATUM_1902691
952 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
953 depends on CORESIGHT_TRBE
956 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
958 Affected Cortex-A510 core might cause trace data corruption, when being written
959 into the memory. Effectively TRBE is broken and hence cannot be used to capture
962 Work around this problem in the driver by just preventing TRBE initialization on
963 affected cpus. The firmware must have disabled the access to TRBE for the kernel
964 on such implementations. This will cover the kernel for any firmware that doesn't
969 config ARM64_ERRATUM_2457168
970 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
971 depends on ARM64_AMU_EXTN
974 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
976 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
977 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
978 incorrectly giving a significantly higher output value.
980 Work around this problem by returning 0 when reading the affected counter in
981 key locations that results in disabling all users of this counter. This effect
982 is the same to firmware disabling affected counters.
986 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
989 config ARM64_ERRATUM_2966298
990 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
991 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
994 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
996 On an affected Cortex-A520 core, a speculatively executed unprivileged
997 load might leak data from a privileged level via a cache side channel.
999 Work around this problem by executing a TLBI before returning to EL0.
1003 config CAVIUM_ERRATUM_22375
1004 bool "Cavium erratum 22375, 24313"
1007 Enable workaround for errata 22375 and 24313.
1009 This implements two gicv3-its errata workarounds for ThunderX. Both
1010 with a small impact affecting only ITS table allocation.
1012 erratum 22375: only alloc 8MB table size
1013 erratum 24313: ignore memory access type
1015 The fixes are in ITS initialization and basically ignore memory access
1016 type and table size provided by the TYPER and BASER registers.
1020 config CAVIUM_ERRATUM_23144
1021 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1025 ITS SYNC command hang for cross node io and collections/cpu mapping.
1029 config CAVIUM_ERRATUM_23154
1030 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1033 The ThunderX GICv3 implementation requires a modified version for
1034 reading the IAR status to ensure data synchronization
1035 (access to icc_iar1_el1 is not sync'ed before and after).
1037 It also suffers from erratum 38545 (also present on Marvell's
1038 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1039 spuriously presented to the CPU interface.
1043 config CAVIUM_ERRATUM_27456
1044 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1047 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1048 instructions may cause the icache to become corrupted if it
1049 contains data for a non-current ASID. The fix is to
1050 invalidate the icache when changing the mm context.
1054 config CAVIUM_ERRATUM_30115
1055 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1058 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1059 1.2, and T83 Pass 1.0, KVM guest execution may disable
1060 interrupts in host. Trapping both GICv3 group-0 and group-1
1061 accesses sidesteps the issue.
1065 config CAVIUM_TX2_ERRATUM_219
1066 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1069 On Cavium ThunderX2, a load, store or prefetch instruction between a
1070 TTBR update and the corresponding context synchronizing operation can
1071 cause a spurious Data Abort to be delivered to any hardware thread in
1074 Work around the issue by avoiding the problematic code sequence and
1075 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1076 trap handler performs the corresponding register access, skips the
1077 instruction and ensures context synchronization by virtue of the
1082 config FUJITSU_ERRATUM_010001
1083 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1086 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1087 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1088 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1089 This fault occurs under a specific hardware condition when a
1090 load/store instruction performs an address translation using:
1091 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1092 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1093 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1094 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1096 The workaround is to ensure these bits are clear in TCR_ELx.
1097 The workaround only affects the Fujitsu-A64FX.
1101 config HISILICON_ERRATUM_161600802
1102 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1105 The HiSilicon Hip07 SoC uses the wrong redistributor base
1106 when issued ITS commands such as VMOVP and VMAPP, and requires
1107 a 128kB offset to be applied to the target address in this commands.
1111 config QCOM_FALKOR_ERRATUM_1003
1112 bool "Falkor E1003: Incorrect translation due to ASID change"
1115 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1116 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1117 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1118 then only for entries in the walk cache, since the leaf translation
1119 is unchanged. Work around the erratum by invalidating the walk cache
1120 entries for the trampoline before entering the kernel proper.
1122 config QCOM_FALKOR_ERRATUM_1009
1123 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1125 select ARM64_WORKAROUND_REPEAT_TLBI
1127 On Falkor v1, the CPU may prematurely complete a DSB following a
1128 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1129 one more time to fix the issue.
1133 config QCOM_QDF2400_ERRATUM_0065
1134 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1137 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1138 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1139 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1143 config QCOM_FALKOR_ERRATUM_E1041
1144 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1147 Falkor CPU may speculatively fetch instructions from an improper
1148 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1149 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1153 config NVIDIA_CARMEL_CNP_ERRATUM
1154 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1157 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1158 invalidate shared TLB entries installed by a different core, as it would
1159 on standard ARM cores.
1163 config SOCIONEXT_SYNQUACER_PREITS
1164 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1167 Socionext Synquacer SoCs implement a separate h/w block to generate
1168 MSI doorbell writes with non-zero values for the device ID.
1172 endmenu # "ARM errata workarounds via the alternatives framework"
1176 default ARM64_4K_PAGES
1178 Page size (translation granule) configuration.
1180 config ARM64_4K_PAGES
1183 This feature enables 4KB pages support.
1185 config ARM64_16K_PAGES
1188 The system will use 16KB pages support. AArch32 emulation
1189 requires applications compiled with 16K (or a multiple of 16K)
1192 config ARM64_64K_PAGES
1195 This feature enables 64KB pages support (4KB by default)
1196 allowing only two levels of page tables and faster TLB
1197 look-up. AArch32 emulation requires applications compiled
1198 with 64K aligned segments.
1203 prompt "Virtual address space size"
1204 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1205 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1206 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1208 Allows choosing one of multiple possible virtual address
1209 space sizes. The level of translation table is determined by
1210 a combination of page size and virtual address space size.
1212 config ARM64_VA_BITS_36
1213 bool "36-bit" if EXPERT
1214 depends on ARM64_16K_PAGES
1216 config ARM64_VA_BITS_39
1218 depends on ARM64_4K_PAGES
1220 config ARM64_VA_BITS_42
1222 depends on ARM64_64K_PAGES
1224 config ARM64_VA_BITS_47
1226 depends on ARM64_16K_PAGES
1228 config ARM64_VA_BITS_48
1231 config ARM64_VA_BITS_52
1233 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1235 Enable 52-bit virtual addressing for userspace when explicitly
1236 requested via a hint to mmap(). The kernel will also use 52-bit
1237 virtual addresses for its own mappings (provided HW support for
1238 this feature is available, otherwise it reverts to 48-bit).
1240 NOTE: Enabling 52-bit virtual addressing in conjunction with
1241 ARMv8.3 Pointer Authentication will result in the PAC being
1242 reduced from 7 bits to 3 bits, which may have a significant
1243 impact on its susceptibility to brute-force attacks.
1245 If unsure, select 48-bit virtual addressing instead.
1249 config ARM64_FORCE_52BIT
1250 bool "Force 52-bit virtual addresses for userspace"
1251 depends on ARM64_VA_BITS_52 && EXPERT
1253 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1254 to maintain compatibility with older software by providing 48-bit VAs
1255 unless a hint is supplied to mmap.
1257 This configuration option disables the 48-bit compatibility logic, and
1258 forces all userspace addresses to be 52-bit on HW that supports it. One
1259 should only enable this configuration option for stress testing userspace
1260 memory management code. If unsure say N here.
1262 config ARM64_VA_BITS
1264 default 36 if ARM64_VA_BITS_36
1265 default 39 if ARM64_VA_BITS_39
1266 default 42 if ARM64_VA_BITS_42
1267 default 47 if ARM64_VA_BITS_47
1268 default 48 if ARM64_VA_BITS_48
1269 default 52 if ARM64_VA_BITS_52
1272 prompt "Physical address space size"
1273 default ARM64_PA_BITS_48
1275 Choose the maximum physical address range that the kernel will
1278 config ARM64_PA_BITS_48
1281 config ARM64_PA_BITS_52
1282 bool "52-bit (ARMv8.2)"
1283 depends on ARM64_64K_PAGES
1284 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1286 Enable support for a 52-bit physical address space, introduced as
1287 part of the ARMv8.2-LPA extension.
1289 With this enabled, the kernel will also continue to work on CPUs that
1290 do not support ARMv8.2-LPA, but with some added memory overhead (and
1291 minor performance overhead).
1295 config ARM64_PA_BITS
1297 default 48 if ARM64_PA_BITS_48
1298 default 52 if ARM64_PA_BITS_52
1302 default CPU_LITTLE_ENDIAN
1304 Select the endianness of data accesses performed by the CPU. Userspace
1305 applications will need to be compiled and linked for the endianness
1306 that is selected here.
1308 config CPU_BIG_ENDIAN
1309 bool "Build big-endian kernel"
1310 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1311 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1312 depends on AS_IS_GNU || AS_VERSION >= 150000
1314 Say Y if you plan on running a kernel with a big-endian userspace.
1316 config CPU_LITTLE_ENDIAN
1317 bool "Build little-endian kernel"
1319 Say Y if you plan on running a kernel with a little-endian userspace.
1320 This is usually the case for distributions targeting arm64.
1325 bool "Multi-core scheduler support"
1327 Multi-core scheduler support improves the CPU scheduler's decision
1328 making when dealing with multi-core CPU chips at a cost of slightly
1329 increased overhead in some places. If unsure say N here.
1331 config SCHED_CLUSTER
1332 bool "Cluster scheduler support"
1334 Cluster scheduler support improves the CPU scheduler's decision
1335 making when dealing with machines that have clusters of CPUs.
1336 Cluster usually means a couple of CPUs which are placed closely
1337 by sharing mid-level caches, last-level cache tags or internal
1341 bool "SMT scheduler support"
1343 Improves the CPU scheduler's decision making when dealing with
1344 MultiThreading at a cost of slightly increased overhead in some
1345 places. If unsure say N here.
1348 int "Maximum number of CPUs (2-4096)"
1353 bool "Support for hot-pluggable CPUs"
1354 select GENERIC_IRQ_MIGRATION
1356 Say Y here to experiment with turning CPUs off and on. CPUs
1357 can be controlled through /sys/devices/system/cpu.
1359 # Common NUMA Features
1361 bool "NUMA Memory Allocation and Scheduler Support"
1362 select GENERIC_ARCH_NUMA
1363 select ACPI_NUMA if ACPI
1365 select HAVE_SETUP_PER_CPU_AREA
1366 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1367 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1368 select USE_PERCPU_NUMA_NODE_ID
1370 Enable NUMA (Non-Uniform Memory Access) support.
1372 The kernel will try to allocate memory used by a CPU on the
1373 local memory of the CPU and add some more
1374 NUMA awareness to the kernel.
1377 int "Maximum NUMA Nodes (as a power of 2)"
1382 Specify the maximum number of NUMA Nodes available on the target
1383 system. Increases memory reserved to accommodate various tables.
1385 source "kernel/Kconfig.hz"
1387 config ARCH_SPARSEMEM_ENABLE
1389 select SPARSEMEM_VMEMMAP_ENABLE
1390 select SPARSEMEM_VMEMMAP
1392 config HW_PERF_EVENTS
1396 # Supported by clang >= 7.0 or GCC >= 12.0.0
1397 config CC_HAVE_SHADOW_CALL_STACK
1398 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1401 bool "Enable paravirtualization code"
1403 This changes the kernel so it can modify itself when it is run
1404 under a hypervisor, potentially improving performance significantly
1405 over full virtualization.
1407 config PARAVIRT_TIME_ACCOUNTING
1408 bool "Paravirtual steal time accounting"
1411 Select this option to enable fine granularity task steal time
1412 accounting. Time spent executing other tasks in parallel with
1413 the current vCPU is discounted from the vCPU power. To account for
1414 that, there can be a small performance impact.
1416 If in doubt, say N here.
1419 depends on PM_SLEEP_SMP
1421 bool "kexec system call"
1423 kexec is a system call that implements the ability to shutdown your
1424 current kernel, and to start another kernel. It is like a reboot
1425 but it is independent of the system firmware. And like a reboot
1426 you can start any kernel with it, not just Linux.
1429 bool "kexec file based system call"
1431 select HAVE_IMA_KEXEC if IMA
1433 This is new version of kexec system call. This system call is
1434 file based and takes file descriptors as system call argument
1435 for kernel and initramfs as opposed to list of segments as
1436 accepted by previous system call.
1439 bool "Verify kernel signature during kexec_file_load() syscall"
1440 depends on KEXEC_FILE
1442 Select this option to verify a signature with loaded kernel
1443 image. If configured, any attempt of loading a image without
1444 valid signature will fail.
1446 In addition to that option, you need to enable signature
1447 verification for the corresponding kernel image type being
1448 loaded in order for this to work.
1450 config KEXEC_IMAGE_VERIFY_SIG
1451 bool "Enable Image signature verification support"
1453 depends on KEXEC_SIG
1454 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1456 Enable Image signature verification support.
1458 comment "Support for PE file signature verification disabled"
1459 depends on KEXEC_SIG
1460 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1463 bool "Build kdump crash kernel"
1465 Generate crash dump after being started by kexec. This should
1466 be normally only set in special crash dump kernels which are
1467 loaded in the main kernel with kexec-tools into a specially
1468 reserved region and then later executed after a crash by
1471 For more details see Documentation/admin-guide/kdump/kdump.rst
1475 depends on HIBERNATION || KEXEC_CORE
1482 bool "Xen guest support on ARM64"
1483 depends on ARM64 && OF
1487 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1489 config ARCH_FORCE_MAX_ORDER
1491 default "14" if ARM64_64K_PAGES
1492 default "12" if ARM64_16K_PAGES
1495 The kernel memory allocator divides physically contiguous memory
1496 blocks into "zones", where each zone is a power of two number of
1497 pages. This option selects the largest power of two that the kernel
1498 keeps in the memory allocator. If you need to allocate very large
1499 blocks of physically contiguous memory, then you may need to
1500 increase this value.
1502 This config option is actually maximum order plus one. For example,
1503 a value of 11 means that the largest free memory block is 2^10 pages.
1505 We make sure that we can allocate upto a HugePage size for each configuration.
1507 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1509 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1510 4M allocations matching the default size used by generic code.
1512 config UNMAP_KERNEL_AT_EL0
1513 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1516 Speculation attacks against some high-performance processors can
1517 be used to bypass MMU permission checks and leak kernel data to
1518 userspace. This can be defended against by unmapping the kernel
1519 when running in userspace, mapping it back in on exception entry
1520 via a trampoline page in the vector table.
1524 config MITIGATE_SPECTRE_BRANCH_HISTORY
1525 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1528 Speculation attacks against some high-performance processors can
1529 make use of branch history to influence future speculation.
1530 When taking an exception from user-space, a sequence of branches
1531 or a firmware call overwrites the branch history.
1533 config RODATA_FULL_DEFAULT_ENABLED
1534 bool "Apply r/o permissions of VM areas also to their linear aliases"
1537 Apply read-only attributes of VM areas to the linear alias of
1538 the backing pages as well. This prevents code or read-only data
1539 from being modified (inadvertently or intentionally) via another
1540 mapping of the same memory page. This additional enhancement can
1541 be turned off at runtime by passing rodata=[off|on] (and turned on
1542 with rodata=full if this option is set to 'n')
1544 This requires the linear region to be mapped down to pages,
1545 which may adversely affect performance in some cases.
1547 config ARM64_SW_TTBR0_PAN
1548 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1550 Enabling this option prevents the kernel from accessing
1551 user-space memory directly by pointing TTBR0_EL1 to a reserved
1552 zeroed area and reserved ASID. The user access routines
1553 restore the valid TTBR0_EL1 temporarily.
1555 config ARM64_TAGGED_ADDR_ABI
1556 bool "Enable the tagged user addresses syscall ABI"
1559 When this option is enabled, user applications can opt in to a
1560 relaxed ABI via prctl() allowing tagged addresses to be passed
1561 to system calls as pointer arguments. For details, see
1562 Documentation/arm64/tagged-address-abi.rst.
1565 bool "Kernel support for 32-bit EL0"
1566 depends on ARM64_4K_PAGES || EXPERT
1568 select OLD_SIGSUSPEND3
1569 select COMPAT_OLD_SIGACTION
1571 This option enables support for a 32-bit EL0 running under a 64-bit
1572 kernel at EL1. AArch32-specific components such as system calls,
1573 the user helper functions, VFP support and the ptrace interface are
1574 handled appropriately by the kernel.
1576 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1577 that you will only be able to execute AArch32 binaries that were compiled
1578 with page size aligned segments.
1580 If you want to execute 32-bit userspace applications, say Y.
1584 config KUSER_HELPERS
1585 bool "Enable kuser helpers page for 32-bit applications"
1588 Warning: disabling this option may break 32-bit user programs.
1590 Provide kuser helpers to compat tasks. The kernel provides
1591 helper code to userspace in read only form at a fixed location
1592 to allow userspace to be independent of the CPU type fitted to
1593 the system. This permits binaries to be run on ARMv4 through
1594 to ARMv8 without modification.
1596 See Documentation/arm/kernel_user_helpers.rst for details.
1598 However, the fixed address nature of these helpers can be used
1599 by ROP (return orientated programming) authors when creating
1602 If all of the binaries and libraries which run on your platform
1603 are built specifically for your platform, and make no use of
1604 these helpers, then you can turn this option off to hinder
1605 such exploits. However, in that case, if a binary or library
1606 relying on those helpers is run, it will not function correctly.
1608 Say N here only if you are absolutely certain that you do not
1609 need these helpers; otherwise, the safe option is to say Y.
1612 bool "Enable vDSO for 32-bit applications"
1613 depends on !CPU_BIG_ENDIAN
1614 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1615 select GENERIC_COMPAT_VDSO
1618 Place in the process address space of 32-bit applications an
1619 ELF shared object providing fast implementations of gettimeofday
1622 You must have a 32-bit build of glibc 2.22 or later for programs
1623 to seamlessly take advantage of this.
1625 config THUMB2_COMPAT_VDSO
1626 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1627 depends on COMPAT_VDSO
1630 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1631 otherwise with '-marm'.
1633 config COMPAT_ALIGNMENT_FIXUPS
1634 bool "Fix up misaligned multi-word loads and stores in user space"
1636 menuconfig ARMV8_DEPRECATED
1637 bool "Emulate deprecated/obsolete ARMv8 instructions"
1640 Legacy software support may require certain instructions
1641 that have been deprecated or obsoleted in the architecture.
1643 Enable this config to enable selective emulation of these
1650 config SWP_EMULATION
1651 bool "Emulate SWP/SWPB instructions"
1653 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1654 they are always undefined. Say Y here to enable software
1655 emulation of these instructions for userspace using LDXR/STXR.
1656 This feature can be controlled at runtime with the abi.swp
1657 sysctl which is disabled by default.
1659 In some older versions of glibc [<=2.8] SWP is used during futex
1660 trylock() operations with the assumption that the code will not
1661 be preempted. This invalid assumption may be more likely to fail
1662 with SWP emulation enabled, leading to deadlock of the user
1665 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1666 on an external transaction monitoring block called a global
1667 monitor to maintain update atomicity. If your system does not
1668 implement a global monitor, this option can cause programs that
1669 perform SWP operations to uncached memory to deadlock.
1673 config CP15_BARRIER_EMULATION
1674 bool "Emulate CP15 Barrier instructions"
1676 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1677 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1678 strongly recommended to use the ISB, DSB, and DMB
1679 instructions instead.
1681 Say Y here to enable software emulation of these
1682 instructions for AArch32 userspace code. When this option is
1683 enabled, CP15 barrier usage is traced which can help
1684 identify software that needs updating. This feature can be
1685 controlled at runtime with the abi.cp15_barrier sysctl.
1689 config SETEND_EMULATION
1690 bool "Emulate SETEND instruction"
1692 The SETEND instruction alters the data-endianness of the
1693 AArch32 EL0, and is deprecated in ARMv8.
1695 Say Y here to enable software emulation of the instruction
1696 for AArch32 userspace code. This feature can be controlled
1697 at runtime with the abi.setend sysctl.
1699 Note: All the cpus on the system must have mixed endian support at EL0
1700 for this feature to be enabled. If a new CPU - which doesn't support mixed
1701 endian - is hotplugged in after this feature has been enabled, there could
1702 be unexpected results in the applications.
1705 endif # ARMV8_DEPRECATED
1709 menu "ARMv8.1 architectural features"
1711 config ARM64_HW_AFDBM
1712 bool "Support for hardware updates of the Access and Dirty page flags"
1715 The ARMv8.1 architecture extensions introduce support for
1716 hardware updates of the access and dirty information in page
1717 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1718 capable processors, accesses to pages with PTE_AF cleared will
1719 set this bit instead of raising an access flag fault.
1720 Similarly, writes to read-only pages with the DBM bit set will
1721 clear the read-only bit (AP[2]) instead of raising a
1724 Kernels built with this configuration option enabled continue
1725 to work on pre-ARMv8.1 hardware and the performance impact is
1726 minimal. If unsure, say Y.
1729 bool "Enable support for Privileged Access Never (PAN)"
1732 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1733 prevents the kernel or hypervisor from accessing user-space (EL0)
1736 Choosing this option will cause any unprotected (not using
1737 copy_to_user et al) memory access to fail with a permission fault.
1739 The feature is detected at runtime, and will remain as a 'nop'
1740 instruction if the cpu does not implement the feature.
1743 def_bool $(as-instr,.arch_extension rcpc)
1745 config AS_HAS_LSE_ATOMICS
1746 def_bool $(as-instr,.arch_extension lse)
1748 config ARM64_LSE_ATOMICS
1750 default ARM64_USE_LSE_ATOMICS
1751 depends on AS_HAS_LSE_ATOMICS
1753 config ARM64_USE_LSE_ATOMICS
1754 bool "Atomic instructions"
1755 depends on JUMP_LABEL
1758 As part of the Large System Extensions, ARMv8.1 introduces new
1759 atomic instructions that are designed specifically to scale in
1762 Say Y here to make use of these instructions for the in-kernel
1763 atomic routines. This incurs a small overhead on CPUs that do
1764 not support these instructions and requires the kernel to be
1765 built with binutils >= 2.25 in order for the new instructions
1768 endmenu # "ARMv8.1 architectural features"
1770 menu "ARMv8.2 architectural features"
1772 config AS_HAS_ARMV8_2
1773 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1776 def_bool $(as-instr,.arch armv8.2-a+sha3)
1779 bool "Enable support for persistent memory"
1780 select ARCH_HAS_PMEM_API
1781 select ARCH_HAS_UACCESS_FLUSHCACHE
1783 Say Y to enable support for the persistent memory API based on the
1784 ARMv8.2 DCPoP feature.
1786 The feature is detected at runtime, and the kernel will use DC CVAC
1787 operations if DC CVAP is not supported (following the behaviour of
1788 DC CVAP itself if the system does not define a point of persistence).
1790 config ARM64_RAS_EXTN
1791 bool "Enable support for RAS CPU Extensions"
1794 CPUs that support the Reliability, Availability and Serviceability
1795 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1796 errors, classify them and report them to software.
1798 On CPUs with these extensions system software can use additional
1799 barriers to determine if faults are pending and read the
1800 classification from a new set of registers.
1802 Selecting this feature will allow the kernel to use these barriers
1803 and access the new registers if the system supports the extension.
1804 Platform RAS features may additionally depend on firmware support.
1807 bool "Enable support for Common Not Private (CNP) translations"
1809 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1811 Common Not Private (CNP) allows translation table entries to
1812 be shared between different PEs in the same inner shareable
1813 domain, so the hardware can use this fact to optimise the
1814 caching of such entries in the TLB.
1816 Selecting this option allows the CNP feature to be detected
1817 at runtime, and does not affect PEs that do not implement
1820 endmenu # "ARMv8.2 architectural features"
1822 menu "ARMv8.3 architectural features"
1824 config ARM64_PTR_AUTH
1825 bool "Enable support for pointer authentication"
1828 Pointer authentication (part of the ARMv8.3 Extensions) provides
1829 instructions for signing and authenticating pointers against secret
1830 keys, which can be used to mitigate Return Oriented Programming (ROP)
1833 This option enables these instructions at EL0 (i.e. for userspace).
1834 Choosing this option will cause the kernel to initialise secret keys
1835 for each process at exec() time, with these keys being
1836 context-switched along with the process.
1838 The feature is detected at runtime. If the feature is not present in
1839 hardware it will not be advertised to userspace/KVM guest nor will it
1842 If the feature is present on the boot CPU but not on a late CPU, then
1843 the late CPU will be parked. Also, if the boot CPU does not have
1844 address auth and the late CPU has then the late CPU will still boot
1845 but with the feature disabled. On such a system, this option should
1848 config ARM64_PTR_AUTH_KERNEL
1849 bool "Use pointer authentication for kernel"
1851 depends on ARM64_PTR_AUTH
1852 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1853 # Modern compilers insert a .note.gnu.property section note for PAC
1854 # which is only understood by binutils starting with version 2.33.1.
1855 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1856 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1857 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1859 If the compiler supports the -mbranch-protection or
1860 -msign-return-address flag (e.g. GCC 7 or later), then this option
1861 will cause the kernel itself to be compiled with return address
1862 protection. In this case, and if the target hardware is known to
1863 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1864 disabled with minimal loss of protection.
1866 This feature works with FUNCTION_GRAPH_TRACER option only if
1867 DYNAMIC_FTRACE_WITH_REGS is enabled.
1869 config CC_HAS_BRANCH_PROT_PAC_RET
1870 # GCC 9 or later, clang 8 or later
1871 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1873 config CC_HAS_SIGN_RETURN_ADDRESS
1875 def_bool $(cc-option,-msign-return-address=all)
1878 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1880 config AS_HAS_CFI_NEGATE_RA_STATE
1881 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1883 endmenu # "ARMv8.3 architectural features"
1885 menu "ARMv8.4 architectural features"
1887 config ARM64_AMU_EXTN
1888 bool "Enable support for the Activity Monitors Unit CPU extension"
1891 The activity monitors extension is an optional extension introduced
1892 by the ARMv8.4 CPU architecture. This enables support for version 1
1893 of the activity monitors architecture, AMUv1.
1895 To enable the use of this extension on CPUs that implement it, say Y.
1897 Note that for architectural reasons, firmware _must_ implement AMU
1898 support when running on CPUs that present the activity monitors
1899 extension. The required support is present in:
1900 * Version 1.5 and later of the ARM Trusted Firmware
1902 For kernels that have this configuration enabled but boot with broken
1903 firmware, you may need to say N here until the firmware is fixed.
1904 Otherwise you may experience firmware panics or lockups when
1905 accessing the counter registers. Even if you are not observing these
1906 symptoms, the values returned by the register reads might not
1907 correctly reflect reality. Most commonly, the value read will be 0,
1908 indicating that the counter is not enabled.
1910 config AS_HAS_ARMV8_4
1911 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1913 config ARM64_TLB_RANGE
1914 bool "Enable support for tlbi range feature"
1916 depends on AS_HAS_ARMV8_4
1918 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1919 range of input addresses.
1921 The feature introduces new assembly instructions, and they were
1922 support when binutils >= 2.30.
1924 endmenu # "ARMv8.4 architectural features"
1926 menu "ARMv8.5 architectural features"
1928 config AS_HAS_ARMV8_5
1929 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1932 bool "Branch Target Identification support"
1935 Branch Target Identification (part of the ARMv8.5 Extensions)
1936 provides a mechanism to limit the set of locations to which computed
1937 branch instructions such as BR or BLR can jump.
1939 To make use of BTI on CPUs that support it, say Y.
1941 BTI is intended to provide complementary protection to other control
1942 flow integrity protection mechanisms, such as the Pointer
1943 authentication mechanism provided as part of the ARMv8.3 Extensions.
1944 For this reason, it does not make sense to enable this option without
1945 also enabling support for pointer authentication. Thus, when
1946 enabling this option you should also select ARM64_PTR_AUTH=y.
1948 Userspace binaries must also be specifically compiled to make use of
1949 this mechanism. If you say N here or the hardware does not support
1950 BTI, such binaries can still run, but you get no additional
1951 enforcement of branch destinations.
1953 config ARM64_BTI_KERNEL
1954 bool "Use Branch Target Identification for kernel"
1956 depends on ARM64_BTI
1957 depends on ARM64_PTR_AUTH_KERNEL
1958 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1959 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1960 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1961 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1962 depends on !CC_IS_GCC
1963 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1964 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1965 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1967 Build the kernel with Branch Target Identification annotations
1968 and enable enforcement of this for kernel code. When this option
1969 is enabled and the system supports BTI all kernel code including
1970 modular code must have BTI enabled.
1972 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1973 # GCC 9 or later, clang 8 or later
1974 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1977 bool "Enable support for E0PD"
1980 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1981 that EL0 accesses made via TTBR1 always fault in constant time,
1982 providing similar benefits to KASLR as those provided by KPTI, but
1983 with lower overhead and without disrupting legitimate access to
1984 kernel memory such as SPE.
1986 This option enables E0PD for TTBR1 where available.
1988 config ARM64_AS_HAS_MTE
1989 # Initial support for MTE went in binutils 2.32.0, checked with
1990 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1991 # as a late addition to the final architecture spec (LDGM/STGM)
1992 # is only supported in the newer 2.32.x and 2.33 binutils
1993 # versions, hence the extra "stgm" instruction check below.
1994 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1997 bool "Memory Tagging Extension support"
1999 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
2000 depends on AS_HAS_ARMV8_5
2001 depends on AS_HAS_LSE_ATOMICS
2002 # Required for tag checking in the uaccess routines
2003 depends on ARM64_PAN
2004 select ARCH_HAS_SUBPAGE_FAULTS
2005 select ARCH_USES_HIGH_VMA_FLAGS
2007 Memory Tagging (part of the ARMv8.5 Extensions) provides
2008 architectural support for run-time, always-on detection of
2009 various classes of memory error to aid with software debugging
2010 to eliminate vulnerabilities arising from memory-unsafe
2013 This option enables the support for the Memory Tagging
2014 Extension at EL0 (i.e. for userspace).
2016 Selecting this option allows the feature to be detected at
2017 runtime. Any secondary CPU not implementing this feature will
2018 not be allowed a late bring-up.
2020 Userspace binaries that want to use this feature must
2021 explicitly opt in. The mechanism for the userspace is
2024 Documentation/arm64/memory-tagging-extension.rst.
2026 endmenu # "ARMv8.5 architectural features"
2028 menu "ARMv8.7 architectural features"
2031 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2033 depends on ARM64_PAN
2035 Enhanced Privileged Access Never (EPAN) allows Privileged
2036 Access Never to be used with Execute-only mappings.
2038 The feature is detected at runtime, and will remain disabled
2039 if the cpu does not implement the feature.
2040 endmenu # "ARMv8.7 architectural features"
2043 bool "ARM Scalable Vector Extension support"
2046 The Scalable Vector Extension (SVE) is an extension to the AArch64
2047 execution state which complements and extends the SIMD functionality
2048 of the base architecture to support much larger vectors and to enable
2049 additional vectorisation opportunities.
2051 To enable use of this extension on CPUs that implement it, say Y.
2053 On CPUs that support the SVE2 extensions, this option will enable
2056 Note that for architectural reasons, firmware _must_ implement SVE
2057 support when running on SVE capable hardware. The required support
2060 * version 1.5 and later of the ARM Trusted Firmware
2061 * the AArch64 boot wrapper since commit 5e1261e08abf
2062 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2064 For other firmware implementations, consult the firmware documentation
2067 If you need the kernel to boot on SVE-capable hardware with broken
2068 firmware, you may need to say N here until you get your firmware
2069 fixed. Otherwise, you may experience firmware panics or lockups when
2070 booting the kernel. If unsure and you are not observing these
2071 symptoms, you should assume that it is safe to say Y.
2074 bool "ARM Scalable Matrix Extension support"
2076 depends on ARM64_SVE
2078 The Scalable Matrix Extension (SME) is an extension to the AArch64
2079 execution state which utilises a substantial subset of the SVE
2080 instruction set, together with the addition of new architectural
2081 register state capable of holding two dimensional matrix tiles to
2082 enable various matrix operations.
2084 config ARM64_MODULE_PLTS
2085 bool "Use PLTs to allow module memory to spill over into vmalloc area"
2087 select HAVE_MOD_ARCH_SPECIFIC
2089 Allocate PLTs when loading modules so that jumps and calls whose
2090 targets are too far away for their relative offsets to be encoded
2091 in the instructions themselves can be bounced via veneers in the
2092 module's PLT. This allows modules to be allocated in the generic
2093 vmalloc area after the dedicated module memory area has been
2096 When running with address space randomization (KASLR), the module
2097 region itself may be too far away for ordinary relative jumps and
2098 calls, and so in that case, module PLTs are required and cannot be
2101 Specific errata workaround(s) might also force module PLTs to be
2102 enabled (ARM64_ERRATUM_843419).
2104 config ARM64_PSEUDO_NMI
2105 bool "Support for NMI-like interrupts"
2108 Adds support for mimicking Non-Maskable Interrupts through the use of
2109 GIC interrupt priority. This support requires version 3 or later of
2112 This high priority configuration for interrupts needs to be
2113 explicitly enabled by setting the kernel parameter
2114 "irqchip.gicv3_pseudo_nmi" to 1.
2119 config ARM64_DEBUG_PRIORITY_MASKING
2120 bool "Debug interrupt priority masking"
2122 This adds runtime checks to functions enabling/disabling
2123 interrupts when using priority masking. The additional checks verify
2124 the validity of ICC_PMR_EL1 when calling concerned functions.
2127 endif # ARM64_PSEUDO_NMI
2130 bool "Build a relocatable kernel image" if EXPERT
2131 select ARCH_HAS_RELR
2134 This builds the kernel as a Position Independent Executable (PIE),
2135 which retains all relocation metadata required to relocate the
2136 kernel binary at runtime to a different virtual address than the
2137 address it was linked at.
2138 Since AArch64 uses the RELA relocation format, this requires a
2139 relocation pass at runtime even if the kernel is loaded at the
2140 same address it was linked at.
2142 config RANDOMIZE_BASE
2143 bool "Randomize the address of the kernel image"
2144 select ARM64_MODULE_PLTS if MODULES
2147 Randomizes the virtual address at which the kernel image is
2148 loaded, as a security feature that deters exploit attempts
2149 relying on knowledge of the location of kernel internals.
2151 It is the bootloader's job to provide entropy, by passing a
2152 random u64 value in /chosen/kaslr-seed at kernel entry.
2154 When booting via the UEFI stub, it will invoke the firmware's
2155 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2156 to the kernel proper. In addition, it will randomise the physical
2157 location of the kernel Image as well.
2161 config RANDOMIZE_MODULE_REGION_FULL
2162 bool "Randomize the module region over a 2 GB range"
2163 depends on RANDOMIZE_BASE
2166 Randomizes the location of the module region inside a 2 GB window
2167 covering the core kernel. This way, it is less likely for modules
2168 to leak information about the location of core kernel data structures
2169 but it does imply that function calls between modules and the core
2170 kernel will need to be resolved via veneers in the module PLT.
2172 When this option is not set, the module region will be randomized over
2173 a limited range that contains the [_stext, _etext] interval of the
2174 core kernel, so branch relocations are almost always in range unless
2175 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2176 particular case of region exhaustion, modules might be able to fall
2177 back to a larger 2GB area.
2179 config CC_HAVE_STACKPROTECTOR_SYSREG
2180 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2182 config STACKPROTECTOR_PER_TASK
2184 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2186 # The GPIO number here must be sorted by descending number. In case of
2187 # a multiplatform kernel, we just want the highest value required by the
2188 # selected platforms.
2191 default 2048 if ARCH_APPLE
2194 Maximum number of GPIOs in the system.
2196 If unsure, leave the default value.
2198 endmenu # "Kernel Features"
2202 config ARM64_ACPI_PARKING_PROTOCOL
2203 bool "Enable support for the ARM64 ACPI parking protocol"
2206 Enable support for the ARM64 ACPI parking protocol. If disabled
2207 the kernel will not allow booting through the ARM64 ACPI parking
2208 protocol even if the corresponding data is present in the ACPI
2212 string "Default kernel command string"
2215 Provide a set of default command-line options at build time by
2216 entering them here. As a minimum, you should specify the the
2217 root device (e.g. root=/dev/nfs).
2220 prompt "Kernel command line type" if CMDLINE != ""
2221 default CMDLINE_FROM_BOOTLOADER
2223 Choose how the kernel will handle the provided default kernel
2224 command line string.
2226 config CMDLINE_FROM_BOOTLOADER
2227 bool "Use bootloader kernel arguments if available"
2229 Uses the command-line options passed by the boot loader. If
2230 the boot loader doesn't provide any, the default kernel command
2231 string provided in CMDLINE will be used.
2233 config CMDLINE_FORCE
2234 bool "Always use the default kernel command string"
2236 Always use the default kernel command string, even if the boot
2237 loader passes other arguments to the kernel.
2238 This is useful if you cannot or don't want to change the
2239 command-line options your boot loader passes to the kernel.
2247 bool "UEFI runtime support"
2248 depends on OF && !CPU_BIG_ENDIAN
2249 depends on KERNEL_MODE_NEON
2250 select ARCH_SUPPORTS_ACPI
2253 select EFI_PARAMS_FROM_FDT
2254 select EFI_RUNTIME_WRAPPERS
2256 select EFI_GENERIC_STUB
2257 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2260 This option provides support for runtime services provided
2261 by UEFI firmware (such as non-volatile variables, realtime
2262 clock, and platform reset). A UEFI stub is also provided to
2263 allow the kernel to be booted as an EFI application. This
2264 is only useful on systems that have UEFI firmware.
2267 bool "Enable support for SMBIOS (DMI) tables"
2271 This enables SMBIOS/DMI feature for systems.
2273 This option is only useful on systems that have UEFI firmware.
2274 However, even with this option, the resultant kernel should
2275 continue to boot on existing non-UEFI platforms.
2277 endmenu # "Boot options"
2279 menu "Power management options"
2281 source "kernel/power/Kconfig"
2283 config ARCH_HIBERNATION_POSSIBLE
2287 config ARCH_HIBERNATION_HEADER
2289 depends on HIBERNATION
2291 config ARCH_SUSPEND_POSSIBLE
2294 endmenu # "Power management options"
2296 menu "CPU Power Management"
2298 source "drivers/cpuidle/Kconfig"
2300 source "drivers/cpufreq/Kconfig"
2302 endmenu # "CPU Power Management"
2304 source "drivers/acpi/Kconfig"
2306 source "arch/arm64/kvm/Kconfig"