1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_COHERENT_TO_PFN
16 select ARCH_HAS_DMA_PREP_COHERENT
17 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE
23 select ARCH_HAS_KEEPINITRD
24 select ARCH_HAS_MEMBARRIER_SYNC_CORE
25 select ARCH_HAS_PTE_DEVMAP
26 select ARCH_HAS_PTE_SPECIAL
27 select ARCH_HAS_SETUP_DMA_OPS
28 select ARCH_HAS_SET_DIRECT_MAP
29 select ARCH_HAS_SET_MEMORY
30 select ARCH_HAS_STRICT_KERNEL_RWX
31 select ARCH_HAS_STRICT_MODULE_RWX
32 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
33 select ARCH_HAS_SYNC_DMA_FOR_CPU
34 select ARCH_HAS_SYSCALL_WRAPPER
35 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
36 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
37 select ARCH_HAVE_NMI_SAFE_CMPXCHG
38 select ARCH_INLINE_READ_LOCK if !PREEMPT
39 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
40 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
43 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
47 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
49 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
51 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
53 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
54 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
55 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
59 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
61 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
63 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
64 select ARCH_KEEP_MEMBLOCK
65 select ARCH_USE_CMPXCHG_LOCKREF
66 select ARCH_USE_QUEUED_RWLOCKS
67 select ARCH_USE_QUEUED_SPINLOCKS
68 select ARCH_SUPPORTS_MEMORY_FAILURE
69 select ARCH_SUPPORTS_ATOMIC_RMW
70 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
71 select ARCH_SUPPORTS_NUMA_BALANCING
72 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
73 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
74 select ARCH_WANT_FRAME_POINTERS
75 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
76 select ARCH_HAS_UBSAN_SANITIZE_ALL
80 select AUDIT_ARCH_COMPAT_GENERIC
81 select ARM_GIC_V2M if PCI
83 select ARM_GIC_V3_ITS if PCI
85 select BUILDTIME_EXTABLE_SORT
86 select CLONE_BACKWARDS
88 select CPU_PM if (SUSPEND || CPU_IDLE)
90 select DCACHE_WORD_ACCESS
91 select DMA_DIRECT_REMAP
94 select GENERIC_ALLOCATOR
95 select GENERIC_ARCH_TOPOLOGY
96 select GENERIC_CLOCKEVENTS
97 select GENERIC_CLOCKEVENTS_BROADCAST
98 select GENERIC_CPU_AUTOPROBE
99 select GENERIC_CPU_VULNERABILITIES
100 select GENERIC_EARLY_IOREMAP
101 select GENERIC_IDLE_POLL_SETUP
102 select GENERIC_IRQ_MULTI_HANDLER
103 select GENERIC_IRQ_PROBE
104 select GENERIC_IRQ_SHOW
105 select GENERIC_IRQ_SHOW_LEVEL
106 select GENERIC_PCI_IOMAP
107 select GENERIC_SCHED_CLOCK
108 select GENERIC_SMP_IDLE_THREAD
109 select GENERIC_STRNCPY_FROM_USER
110 select GENERIC_STRNLEN_USER
111 select GENERIC_TIME_VSYSCALL
112 select GENERIC_GETTIMEOFDAY
113 select HANDLE_DOMAIN_IRQ
114 select HARDIRQS_SW_RESEND
116 select HAVE_ACPI_APEI if (ACPI && EFI)
117 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
118 select HAVE_ARCH_AUDITSYSCALL
119 select HAVE_ARCH_BITREVERSE
120 select HAVE_ARCH_HUGE_VMAP
121 select HAVE_ARCH_JUMP_LABEL
122 select HAVE_ARCH_JUMP_LABEL_RELATIVE
123 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
124 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
125 select HAVE_ARCH_KGDB
126 select HAVE_ARCH_MMAP_RND_BITS
127 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
128 select HAVE_ARCH_PREL32_RELOCATIONS
129 select HAVE_ARCH_SECCOMP_FILTER
130 select HAVE_ARCH_STACKLEAK
131 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
132 select HAVE_ARCH_TRACEHOOK
133 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
134 select HAVE_ARCH_VMAP_STACK
135 select HAVE_ARM_SMCCC
136 select HAVE_ASM_MODVERSIONS
138 select HAVE_C_RECORDMCOUNT
139 select HAVE_CMPXCHG_DOUBLE
140 select HAVE_CMPXCHG_LOCAL
141 select HAVE_CONTEXT_TRACKING
142 select HAVE_COPY_THREAD_TLS
143 select HAVE_DEBUG_BUGVERBOSE
144 select HAVE_DEBUG_KMEMLEAK
145 select HAVE_DMA_CONTIGUOUS
146 select HAVE_DYNAMIC_FTRACE
147 select HAVE_EFFICIENT_UNALIGNED_ACCESS
149 select HAVE_FTRACE_MCOUNT_RECORD
150 select HAVE_FUNCTION_TRACER
151 select HAVE_FUNCTION_ERROR_INJECTION
152 select HAVE_FUNCTION_GRAPH_TRACER
153 select HAVE_GCC_PLUGINS
154 select HAVE_HW_BREAKPOINT if PERF_EVENTS
155 select HAVE_IRQ_TIME_ACCOUNTING
156 select HAVE_MEMBLOCK_NODE_MAP if NUMA
158 select HAVE_PATA_PLATFORM
159 select HAVE_PERF_EVENTS
160 select HAVE_PERF_REGS
161 select HAVE_PERF_USER_STACK_DUMP
162 select HAVE_REGS_AND_STACK_ACCESS_API
163 select HAVE_FUNCTION_ARG_ACCESS_API
164 select HAVE_RCU_TABLE_FREE
166 select HAVE_STACKPROTECTOR
167 select HAVE_SYSCALL_TRACEPOINTS
169 select HAVE_KRETPROBES
170 select HAVE_GENERIC_VDSO
171 select IOMMU_DMA if IOMMU_SUPPORT
173 select IRQ_FORCED_THREADING
174 select MODULES_USE_ELF_RELA
175 select NEED_DMA_MAP_STATE
176 select NEED_SG_DMA_LENGTH
178 select OF_EARLY_FLATTREE
179 select PCI_DOMAINS_GENERIC if PCI
180 select PCI_ECAM if (ACPI && PCI)
181 select PCI_SYSCALL if PCI
187 select SYSCTL_EXCEPTION_TRACE
188 select THREAD_INFO_IN_TASK
190 ARM 64-bit (AArch64) Linux support.
198 config ARM64_PAGE_SHIFT
200 default 16 if ARM64_64K_PAGES
201 default 14 if ARM64_16K_PAGES
204 config ARM64_CONT_SHIFT
206 default 5 if ARM64_64K_PAGES
207 default 7 if ARM64_16K_PAGES
210 config ARCH_MMAP_RND_BITS_MIN
211 default 14 if ARM64_64K_PAGES
212 default 16 if ARM64_16K_PAGES
215 # max bits determined by the following formula:
216 # VA_BITS - PAGE_SHIFT - 3
217 config ARCH_MMAP_RND_BITS_MAX
218 default 19 if ARM64_VA_BITS=36
219 default 24 if ARM64_VA_BITS=39
220 default 27 if ARM64_VA_BITS=42
221 default 30 if ARM64_VA_BITS=47
222 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
223 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
224 default 33 if ARM64_VA_BITS=48
225 default 14 if ARM64_64K_PAGES
226 default 16 if ARM64_16K_PAGES
229 config ARCH_MMAP_RND_COMPAT_BITS_MIN
230 default 7 if ARM64_64K_PAGES
231 default 9 if ARM64_16K_PAGES
234 config ARCH_MMAP_RND_COMPAT_BITS_MAX
240 config STACKTRACE_SUPPORT
243 config ILLEGAL_POINTER_VALUE
245 default 0xdead000000000000
247 config LOCKDEP_SUPPORT
250 config TRACE_IRQFLAGS_SUPPORT
257 config GENERIC_BUG_RELATIVE_POINTERS
259 depends on GENERIC_BUG
261 config GENERIC_HWEIGHT
267 config GENERIC_CALIBRATE_DELAY
271 bool "Support DMA32 zone" if EXPERT
274 config ARCH_ENABLE_MEMORY_HOTPLUG
280 config KERNEL_MODE_NEON
283 config FIX_EARLYCON_MEM
286 config PGTABLE_LEVELS
288 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
289 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
290 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
291 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
292 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
293 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
295 config ARCH_SUPPORTS_UPROBES
298 config ARCH_PROC_KCORE_TEXT
301 config KASAN_SHADOW_OFFSET
304 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
305 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
306 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
307 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
308 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
309 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
310 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
311 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
312 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
313 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
314 default 0xffffffffffffffff
316 source "arch/arm64/Kconfig.platforms"
318 menu "Kernel Features"
320 menu "ARM errata workarounds via the alternatives framework"
322 config ARM64_WORKAROUND_CLEAN_CACHE
325 config ARM64_ERRATUM_826319
326 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
328 select ARM64_WORKAROUND_CLEAN_CACHE
330 This option adds an alternative code sequence to work around ARM
331 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
332 AXI master interface and an L2 cache.
334 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
335 and is unable to accept a certain write via this interface, it will
336 not progress on read data presented on the read data channel and the
339 The workaround promotes data cache clean instructions to
340 data cache clean-and-invalidate.
341 Please note that this does not necessarily enable the workaround,
342 as it depends on the alternative framework, which will only patch
343 the kernel if an affected CPU is detected.
347 config ARM64_ERRATUM_827319
348 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
350 select ARM64_WORKAROUND_CLEAN_CACHE
352 This option adds an alternative code sequence to work around ARM
353 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
354 master interface and an L2 cache.
356 Under certain conditions this erratum can cause a clean line eviction
357 to occur at the same time as another transaction to the same address
358 on the AMBA 5 CHI interface, which can cause data corruption if the
359 interconnect reorders the two transactions.
361 The workaround promotes data cache clean instructions to
362 data cache clean-and-invalidate.
363 Please note that this does not necessarily enable the workaround,
364 as it depends on the alternative framework, which will only patch
365 the kernel if an affected CPU is detected.
369 config ARM64_ERRATUM_824069
370 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
372 select ARM64_WORKAROUND_CLEAN_CACHE
374 This option adds an alternative code sequence to work around ARM
375 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
376 to a coherent interconnect.
378 If a Cortex-A53 processor is executing a store or prefetch for
379 write instruction at the same time as a processor in another
380 cluster is executing a cache maintenance operation to the same
381 address, then this erratum might cause a clean cache line to be
382 incorrectly marked as dirty.
384 The workaround promotes data cache clean instructions to
385 data cache clean-and-invalidate.
386 Please note that this option does not necessarily enable the
387 workaround, as it depends on the alternative framework, which will
388 only patch the kernel if an affected CPU is detected.
392 config ARM64_ERRATUM_819472
393 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
395 select ARM64_WORKAROUND_CLEAN_CACHE
397 This option adds an alternative code sequence to work around ARM
398 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
399 present when it is connected to a coherent interconnect.
401 If the processor is executing a load and store exclusive sequence at
402 the same time as a processor in another cluster is executing a cache
403 maintenance operation to the same address, then this erratum might
404 cause data corruption.
406 The workaround promotes data cache clean instructions to
407 data cache clean-and-invalidate.
408 Please note that this does not necessarily enable the workaround,
409 as it depends on the alternative framework, which will only patch
410 the kernel if an affected CPU is detected.
414 config ARM64_ERRATUM_832075
415 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
418 This option adds an alternative code sequence to work around ARM
419 erratum 832075 on Cortex-A57 parts up to r1p2.
421 Affected Cortex-A57 parts might deadlock when exclusive load/store
422 instructions to Write-Back memory are mixed with Device loads.
424 The workaround is to promote device loads to use Load-Acquire
426 Please note that this does not necessarily enable the workaround,
427 as it depends on the alternative framework, which will only patch
428 the kernel if an affected CPU is detected.
432 config ARM64_ERRATUM_834220
433 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
437 This option adds an alternative code sequence to work around ARM
438 erratum 834220 on Cortex-A57 parts up to r1p2.
440 Affected Cortex-A57 parts might report a Stage 2 translation
441 fault as the result of a Stage 1 fault for load crossing a
442 page boundary when there is a permission or device memory
443 alignment fault at Stage 1 and a translation fault at Stage 2.
445 The workaround is to verify that the Stage 1 translation
446 doesn't generate a fault before handling the Stage 2 fault.
447 Please note that this does not necessarily enable the workaround,
448 as it depends on the alternative framework, which will only patch
449 the kernel if an affected CPU is detected.
453 config ARM64_ERRATUM_845719
454 bool "Cortex-A53: 845719: a load might read incorrect data"
458 This option adds an alternative code sequence to work around ARM
459 erratum 845719 on Cortex-A53 parts up to r0p4.
461 When running a compat (AArch32) userspace on an affected Cortex-A53
462 part, a load at EL0 from a virtual address that matches the bottom 32
463 bits of the virtual address used by a recent load at (AArch64) EL1
464 might return incorrect data.
466 The workaround is to write the contextidr_el1 register on exception
467 return to a 32-bit task.
468 Please note that this does not necessarily enable the workaround,
469 as it depends on the alternative framework, which will only patch
470 the kernel if an affected CPU is detected.
474 config ARM64_ERRATUM_843419
475 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
477 select ARM64_MODULE_PLTS if MODULES
479 This option links the kernel with '--fix-cortex-a53-843419' and
480 enables PLT support to replace certain ADRP instructions, which can
481 cause subsequent memory accesses to use an incorrect address on
482 Cortex-A53 parts up to r0p4.
486 config ARM64_ERRATUM_1024718
487 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
490 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
492 Affected Cortex-A55 cores (all revisions) could cause incorrect
493 update of the hardware dirty bit when the DBM/AP bits are updated
494 without a break-before-make. The workaround is to disable the usage
495 of hardware DBM locally on the affected cores. CPUs not affected by
496 this erratum will continue to use the feature.
500 config ARM64_ERRATUM_1418040
501 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
505 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
506 errata 1188873 and 1418040.
508 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
509 cause register corruption when accessing the timer registers
510 from AArch32 userspace.
514 config ARM64_ERRATUM_1165522
515 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
518 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
520 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
521 corrupted TLBs by speculating an AT instruction during a guest
526 config ARM64_ERRATUM_1286807
527 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
529 select ARM64_WORKAROUND_REPEAT_TLBI
531 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
533 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
534 address for a cacheable mapping of a location is being
535 accessed by a core while another core is remapping the virtual
536 address to a new physical page using the recommended
537 break-before-make sequence, then under very rare circumstances
538 TLBI+DSB completes before a read using the translation being
539 invalidated has been observed by other observers. The
540 workaround repeats the TLBI+DSB operation.
544 config ARM64_ERRATUM_1463225
545 bool "Cortex-A76: Software Step might prevent interrupt recognition"
548 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
550 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
551 of a system call instruction (SVC) can prevent recognition of
552 subsequent interrupts when software stepping is disabled in the
553 exception handler of the system call and either kernel debugging
554 is enabled or VHE is in use.
556 Work around the erratum by triggering a dummy step exception
557 when handling a system call from a task that is being stepped
558 in a VHE configuration of the kernel.
562 config ARM64_ERRATUM_1542419
563 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
566 This option adds a workaround for ARM Neoverse-N1 erratum
569 Affected Neoverse-N1 cores could execute a stale instruction when
570 modified by another CPU. The workaround depends on a firmware
573 Workaround the issue by hiding the DIC feature from EL0. This
574 forces user-space to perform cache maintenance.
578 config CAVIUM_ERRATUM_22375
579 bool "Cavium erratum 22375, 24313"
582 Enable workaround for errata 22375 and 24313.
584 This implements two gicv3-its errata workarounds for ThunderX. Both
585 with a small impact affecting only ITS table allocation.
587 erratum 22375: only alloc 8MB table size
588 erratum 24313: ignore memory access type
590 The fixes are in ITS initialization and basically ignore memory access
591 type and table size provided by the TYPER and BASER registers.
595 config CAVIUM_ERRATUM_23144
596 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
600 ITS SYNC command hang for cross node io and collections/cpu mapping.
604 config CAVIUM_ERRATUM_23154
605 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
608 The gicv3 of ThunderX requires a modified version for
609 reading the IAR status to ensure data synchronization
610 (access to icc_iar1_el1 is not sync'ed before and after).
614 config CAVIUM_ERRATUM_27456
615 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
618 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
619 instructions may cause the icache to become corrupted if it
620 contains data for a non-current ASID. The fix is to
621 invalidate the icache when changing the mm context.
625 config CAVIUM_ERRATUM_30115
626 bool "Cavium erratum 30115: Guest may disable interrupts in host"
629 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
630 1.2, and T83 Pass 1.0, KVM guest execution may disable
631 interrupts in host. Trapping both GICv3 group-0 and group-1
632 accesses sidesteps the issue.
636 config CAVIUM_TX2_ERRATUM_219
637 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
640 On Cavium ThunderX2, a load, store or prefetch instruction between a
641 TTBR update and the corresponding context synchronizing operation can
642 cause a spurious Data Abort to be delivered to any hardware thread in
645 Work around the issue by avoiding the problematic code sequence and
646 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
647 trap handler performs the corresponding register access, skips the
648 instruction and ensures context synchronization by virtue of the
653 config QCOM_FALKOR_ERRATUM_1003
654 bool "Falkor E1003: Incorrect translation due to ASID change"
657 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
658 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
659 in TTBR1_EL1, this situation only occurs in the entry trampoline and
660 then only for entries in the walk cache, since the leaf translation
661 is unchanged. Work around the erratum by invalidating the walk cache
662 entries for the trampoline before entering the kernel proper.
664 config ARM64_WORKAROUND_REPEAT_TLBI
667 config QCOM_FALKOR_ERRATUM_1009
668 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
670 select ARM64_WORKAROUND_REPEAT_TLBI
672 On Falkor v1, the CPU may prematurely complete a DSB following a
673 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
674 one more time to fix the issue.
678 config QCOM_QDF2400_ERRATUM_0065
679 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
682 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
683 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
684 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
688 config SOCIONEXT_SYNQUACER_PREITS
689 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
692 Socionext Synquacer SoCs implement a separate h/w block to generate
693 MSI doorbell writes with non-zero values for the device ID.
697 config HISILICON_ERRATUM_161600802
698 bool "Hip07 161600802: Erroneous redistributor VLPI base"
701 The HiSilicon Hip07 SoC uses the wrong redistributor base
702 when issued ITS commands such as VMOVP and VMAPP, and requires
703 a 128kB offset to be applied to the target address in this commands.
707 config QCOM_FALKOR_ERRATUM_E1041
708 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
711 Falkor CPU may speculatively fetch instructions from an improper
712 memory location when MMU translation is changed from SCTLR_ELn[M]=1
713 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
717 config FUJITSU_ERRATUM_010001
718 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
721 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
722 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
723 accesses may cause undefined fault (Data abort, DFSC=0b111111).
724 This fault occurs under a specific hardware condition when a
725 load/store instruction performs an address translation using:
726 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
727 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
728 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
729 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
731 The workaround is to ensure these bits are clear in TCR_ELx.
732 The workaround only affects the Fujitsu-A64FX.
741 default ARM64_4K_PAGES
743 Page size (translation granule) configuration.
745 config ARM64_4K_PAGES
748 This feature enables 4KB pages support.
750 config ARM64_16K_PAGES
753 The system will use 16KB pages support. AArch32 emulation
754 requires applications compiled with 16K (or a multiple of 16K)
757 config ARM64_64K_PAGES
760 This feature enables 64KB pages support (4KB by default)
761 allowing only two levels of page tables and faster TLB
762 look-up. AArch32 emulation requires applications compiled
763 with 64K aligned segments.
768 prompt "Virtual address space size"
769 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
770 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
771 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
773 Allows choosing one of multiple possible virtual address
774 space sizes. The level of translation table is determined by
775 a combination of page size and virtual address space size.
777 config ARM64_VA_BITS_36
778 bool "36-bit" if EXPERT
779 depends on ARM64_16K_PAGES
781 config ARM64_VA_BITS_39
783 depends on ARM64_4K_PAGES
785 config ARM64_VA_BITS_42
787 depends on ARM64_64K_PAGES
789 config ARM64_VA_BITS_47
791 depends on ARM64_16K_PAGES
793 config ARM64_VA_BITS_48
796 config ARM64_VA_BITS_52
798 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
800 Enable 52-bit virtual addressing for userspace when explicitly
801 requested via a hint to mmap(). The kernel will also use 52-bit
802 virtual addresses for its own mappings (provided HW support for
803 this feature is available, otherwise it reverts to 48-bit).
805 NOTE: Enabling 52-bit virtual addressing in conjunction with
806 ARMv8.3 Pointer Authentication will result in the PAC being
807 reduced from 7 bits to 3 bits, which may have a significant
808 impact on its susceptibility to brute-force attacks.
810 If unsure, select 48-bit virtual addressing instead.
814 config ARM64_FORCE_52BIT
815 bool "Force 52-bit virtual addresses for userspace"
816 depends on ARM64_VA_BITS_52 && EXPERT
818 For systems with 52-bit userspace VAs enabled, the kernel will attempt
819 to maintain compatibility with older software by providing 48-bit VAs
820 unless a hint is supplied to mmap.
822 This configuration option disables the 48-bit compatibility logic, and
823 forces all userspace addresses to be 52-bit on HW that supports it. One
824 should only enable this configuration option for stress testing userspace
825 memory management code. If unsure say N here.
829 default 36 if ARM64_VA_BITS_36
830 default 39 if ARM64_VA_BITS_39
831 default 42 if ARM64_VA_BITS_42
832 default 47 if ARM64_VA_BITS_47
833 default 48 if ARM64_VA_BITS_48
834 default 52 if ARM64_VA_BITS_52
837 prompt "Physical address space size"
838 default ARM64_PA_BITS_48
840 Choose the maximum physical address range that the kernel will
843 config ARM64_PA_BITS_48
846 config ARM64_PA_BITS_52
847 bool "52-bit (ARMv8.2)"
848 depends on ARM64_64K_PAGES
849 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
851 Enable support for a 52-bit physical address space, introduced as
852 part of the ARMv8.2-LPA extension.
854 With this enabled, the kernel will also continue to work on CPUs that
855 do not support ARMv8.2-LPA, but with some added memory overhead (and
856 minor performance overhead).
862 default 48 if ARM64_PA_BITS_48
863 default 52 if ARM64_PA_BITS_52
865 config CPU_BIG_ENDIAN
866 bool "Build big-endian kernel"
868 Say Y if you plan on running a kernel in big-endian mode.
871 bool "Multi-core scheduler support"
873 Multi-core scheduler support improves the CPU scheduler's decision
874 making when dealing with multi-core CPU chips at a cost of slightly
875 increased overhead in some places. If unsure say N here.
878 bool "SMT scheduler support"
880 Improves the CPU scheduler's decision making when dealing with
881 MultiThreading at a cost of slightly increased overhead in some
882 places. If unsure say N here.
885 int "Maximum number of CPUs (2-4096)"
890 bool "Support for hot-pluggable CPUs"
891 select GENERIC_IRQ_MIGRATION
893 Say Y here to experiment with turning CPUs off and on. CPUs
894 can be controlled through /sys/devices/system/cpu.
896 # Common NUMA Features
898 bool "Numa Memory Allocation and Scheduler Support"
899 select ACPI_NUMA if ACPI
902 Enable NUMA (Non Uniform Memory Access) support.
904 The kernel will try to allocate memory used by a CPU on the
905 local memory of the CPU and add some more
906 NUMA awareness to the kernel.
909 int "Maximum NUMA Nodes (as a power of 2)"
912 depends on NEED_MULTIPLE_NODES
914 Specify the maximum number of NUMA Nodes available on the target
915 system. Increases memory reserved to accommodate various tables.
917 config USE_PERCPU_NUMA_NODE_ID
921 config HAVE_SETUP_PER_CPU_AREA
925 config NEED_PER_CPU_EMBED_FIRST_CHUNK
932 source "kernel/Kconfig.hz"
934 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
937 config ARCH_SPARSEMEM_ENABLE
939 select SPARSEMEM_VMEMMAP_ENABLE
941 config ARCH_SPARSEMEM_DEFAULT
942 def_bool ARCH_SPARSEMEM_ENABLE
944 config ARCH_SELECT_MEMORY_MODEL
945 def_bool ARCH_SPARSEMEM_ENABLE
947 config ARCH_FLATMEM_ENABLE
950 config HAVE_ARCH_PFN_VALID
953 config HW_PERF_EVENTS
957 config SYS_SUPPORTS_HUGETLBFS
960 config ARCH_WANT_HUGE_PMD_SHARE
962 config ARCH_HAS_CACHE_LINE_SIZE
965 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
966 def_bool y if PGTABLE_LEVELS > 2
969 bool "Enable seccomp to safely compute untrusted bytecode"
971 This kernel feature is useful for number crunching applications
972 that may need to compute untrusted bytecode during their
973 execution. By using pipes or other transports made available to
974 the process as file descriptors supporting the read/write
975 syscalls, it's possible to isolate those applications in
976 their own address space using seccomp. Once seccomp is
977 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
978 and the task is only allowed to execute a few safe syscalls
979 defined by each seccomp mode.
982 bool "Enable paravirtualization code"
984 This changes the kernel so it can modify itself when it is run
985 under a hypervisor, potentially improving performance significantly
986 over full virtualization.
988 config PARAVIRT_TIME_ACCOUNTING
989 bool "Paravirtual steal time accounting"
992 Select this option to enable fine granularity task steal time
993 accounting. Time spent executing other tasks in parallel with
994 the current vCPU is discounted from the vCPU power. To account for
995 that, there can be a small performance impact.
997 If in doubt, say N here.
1000 depends on PM_SLEEP_SMP
1002 bool "kexec system call"
1004 kexec is a system call that implements the ability to shutdown your
1005 current kernel, and to start another kernel. It is like a reboot
1006 but it is independent of the system firmware. And like a reboot
1007 you can start any kernel with it, not just Linux.
1010 bool "kexec file based system call"
1013 This is new version of kexec system call. This system call is
1014 file based and takes file descriptors as system call argument
1015 for kernel and initramfs as opposed to list of segments as
1016 accepted by previous system call.
1019 bool "Verify kernel signature during kexec_file_load() syscall"
1020 depends on KEXEC_FILE
1022 Select this option to verify a signature with loaded kernel
1023 image. If configured, any attempt of loading a image without
1024 valid signature will fail.
1026 In addition to that option, you need to enable signature
1027 verification for the corresponding kernel image type being
1028 loaded in order for this to work.
1030 config KEXEC_IMAGE_VERIFY_SIG
1031 bool "Enable Image signature verification support"
1033 depends on KEXEC_SIG
1034 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1036 Enable Image signature verification support.
1038 comment "Support for PE file signature verification disabled"
1039 depends on KEXEC_SIG
1040 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1043 bool "Build kdump crash kernel"
1045 Generate crash dump after being started by kexec. This should
1046 be normally only set in special crash dump kernels which are
1047 loaded in the main kernel with kexec-tools into a specially
1048 reserved region and then later executed after a crash by
1051 For more details see Documentation/admin-guide/kdump/kdump.rst
1058 bool "Xen guest support on ARM64"
1059 depends on ARM64 && OF
1063 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1065 config FORCE_MAX_ZONEORDER
1067 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1068 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1071 The kernel memory allocator divides physically contiguous memory
1072 blocks into "zones", where each zone is a power of two number of
1073 pages. This option selects the largest power of two that the kernel
1074 keeps in the memory allocator. If you need to allocate very large
1075 blocks of physically contiguous memory, then you may need to
1076 increase this value.
1078 This config option is actually maximum order plus one. For example,
1079 a value of 11 means that the largest free memory block is 2^10 pages.
1081 We make sure that we can allocate upto a HugePage size for each configuration.
1083 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1085 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1086 4M allocations matching the default size used by generic code.
1088 config UNMAP_KERNEL_AT_EL0
1089 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1092 Speculation attacks against some high-performance processors can
1093 be used to bypass MMU permission checks and leak kernel data to
1094 userspace. This can be defended against by unmapping the kernel
1095 when running in userspace, mapping it back in on exception entry
1096 via a trampoline page in the vector table.
1100 config HARDEN_BRANCH_PREDICTOR
1101 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1104 Speculation attacks against some high-performance processors rely on
1105 being able to manipulate the branch predictor for a victim context by
1106 executing aliasing branches in the attacker context. Such attacks
1107 can be partially mitigated against by clearing internal branch
1108 predictor state and limiting the prediction logic in some situations.
1110 This config option will take CPU-specific actions to harden the
1111 branch predictor against aliasing attacks and may rely on specific
1112 instruction sequences or control bits being set by the system
1117 config HARDEN_EL2_VECTORS
1118 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1121 Speculation attacks against some high-performance processors can
1122 be used to leak privileged information such as the vector base
1123 register, resulting in a potential defeat of the EL2 layout
1126 This config option will map the vectors to a fixed location,
1127 independent of the EL2 code mapping, so that revealing VBAR_EL2
1128 to an attacker does not give away any extra information. This
1129 only gets enabled on affected CPUs.
1134 bool "Speculative Store Bypass Disable" if EXPERT
1137 This enables mitigation of the bypassing of previous stores
1138 by speculative loads.
1142 config MITIGATE_SPECTRE_BRANCH_HISTORY
1143 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1146 Speculation attacks against some high-performance processors can
1147 make use of branch history to influence future speculation.
1148 When taking an exception from user-space, a sequence of branches
1149 or a firmware call overwrites the branch history.
1151 config RODATA_FULL_DEFAULT_ENABLED
1152 bool "Apply r/o permissions of VM areas also to their linear aliases"
1155 Apply read-only attributes of VM areas to the linear alias of
1156 the backing pages as well. This prevents code or read-only data
1157 from being modified (inadvertently or intentionally) via another
1158 mapping of the same memory page. This additional enhancement can
1159 be turned off at runtime by passing rodata=[off|on] (and turned on
1160 with rodata=full if this option is set to 'n')
1162 This requires the linear region to be mapped down to pages,
1163 which may adversely affect performance in some cases.
1165 config ARM64_SW_TTBR0_PAN
1166 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1168 Enabling this option prevents the kernel from accessing
1169 user-space memory directly by pointing TTBR0_EL1 to a reserved
1170 zeroed area and reserved ASID. The user access routines
1171 restore the valid TTBR0_EL1 temporarily.
1173 config ARM64_TAGGED_ADDR_ABI
1174 bool "Enable the tagged user addresses syscall ABI"
1177 When this option is enabled, user applications can opt in to a
1178 relaxed ABI via prctl() allowing tagged addresses to be passed
1179 to system calls as pointer arguments. For details, see
1180 Documentation/arm64/tagged-address-abi.rst.
1183 bool "Kernel support for 32-bit EL0"
1184 depends on ARM64_4K_PAGES || EXPERT
1185 select COMPAT_BINFMT_ELF if BINFMT_ELF
1187 select OLD_SIGSUSPEND3
1188 select COMPAT_OLD_SIGACTION
1190 This option enables support for a 32-bit EL0 running under a 64-bit
1191 kernel at EL1. AArch32-specific components such as system calls,
1192 the user helper functions, VFP support and the ptrace interface are
1193 handled appropriately by the kernel.
1195 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1196 that you will only be able to execute AArch32 binaries that were compiled
1197 with page size aligned segments.
1199 If you want to execute 32-bit userspace applications, say Y.
1203 config KUSER_HELPERS
1204 bool "Enable kuser helpers page for 32-bit applications"
1207 Warning: disabling this option may break 32-bit user programs.
1209 Provide kuser helpers to compat tasks. The kernel provides
1210 helper code to userspace in read only form at a fixed location
1211 to allow userspace to be independent of the CPU type fitted to
1212 the system. This permits binaries to be run on ARMv4 through
1213 to ARMv8 without modification.
1215 See Documentation/arm/kernel_user_helpers.rst for details.
1217 However, the fixed address nature of these helpers can be used
1218 by ROP (return orientated programming) authors when creating
1221 If all of the binaries and libraries which run on your platform
1222 are built specifically for your platform, and make no use of
1223 these helpers, then you can turn this option off to hinder
1224 such exploits. However, in that case, if a binary or library
1225 relying on those helpers is run, it will not function correctly.
1227 Say N here only if you are absolutely certain that you do not
1228 need these helpers; otherwise, the safe option is to say Y.
1231 bool "Enable vDSO for 32-bit applications"
1232 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1233 select GENERIC_COMPAT_VDSO
1236 Place in the process address space of 32-bit applications an
1237 ELF shared object providing fast implementations of gettimeofday
1240 You must have a 32-bit build of glibc 2.22 or later for programs
1241 to seamlessly take advantage of this.
1243 menuconfig ARMV8_DEPRECATED
1244 bool "Emulate deprecated/obsolete ARMv8 instructions"
1247 Legacy software support may require certain instructions
1248 that have been deprecated or obsoleted in the architecture.
1250 Enable this config to enable selective emulation of these
1257 config SWP_EMULATION
1258 bool "Emulate SWP/SWPB instructions"
1260 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1261 they are always undefined. Say Y here to enable software
1262 emulation of these instructions for userspace using LDXR/STXR.
1264 In some older versions of glibc [<=2.8] SWP is used during futex
1265 trylock() operations with the assumption that the code will not
1266 be preempted. This invalid assumption may be more likely to fail
1267 with SWP emulation enabled, leading to deadlock of the user
1270 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1271 on an external transaction monitoring block called a global
1272 monitor to maintain update atomicity. If your system does not
1273 implement a global monitor, this option can cause programs that
1274 perform SWP operations to uncached memory to deadlock.
1278 config CP15_BARRIER_EMULATION
1279 bool "Emulate CP15 Barrier instructions"
1281 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1282 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1283 strongly recommended to use the ISB, DSB, and DMB
1284 instructions instead.
1286 Say Y here to enable software emulation of these
1287 instructions for AArch32 userspace code. When this option is
1288 enabled, CP15 barrier usage is traced which can help
1289 identify software that needs updating.
1293 config SETEND_EMULATION
1294 bool "Emulate SETEND instruction"
1296 The SETEND instruction alters the data-endianness of the
1297 AArch32 EL0, and is deprecated in ARMv8.
1299 Say Y here to enable software emulation of the instruction
1300 for AArch32 userspace code.
1302 Note: All the cpus on the system must have mixed endian support at EL0
1303 for this feature to be enabled. If a new CPU - which doesn't support mixed
1304 endian - is hotplugged in after this feature has been enabled, there could
1305 be unexpected results in the applications.
1312 menu "ARMv8.1 architectural features"
1314 config ARM64_HW_AFDBM
1315 bool "Support for hardware updates of the Access and Dirty page flags"
1318 The ARMv8.1 architecture extensions introduce support for
1319 hardware updates of the access and dirty information in page
1320 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1321 capable processors, accesses to pages with PTE_AF cleared will
1322 set this bit instead of raising an access flag fault.
1323 Similarly, writes to read-only pages with the DBM bit set will
1324 clear the read-only bit (AP[2]) instead of raising a
1327 Kernels built with this configuration option enabled continue
1328 to work on pre-ARMv8.1 hardware and the performance impact is
1329 minimal. If unsure, say Y.
1332 bool "Enable support for Privileged Access Never (PAN)"
1335 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1336 prevents the kernel or hypervisor from accessing user-space (EL0)
1339 Choosing this option will cause any unprotected (not using
1340 copy_to_user et al) memory access to fail with a permission fault.
1342 The feature is detected at runtime, and will remain as a 'nop'
1343 instruction if the cpu does not implement the feature.
1345 config ARM64_LSE_ATOMICS
1346 bool "Atomic instructions"
1347 depends on JUMP_LABEL
1350 As part of the Large System Extensions, ARMv8.1 introduces new
1351 atomic instructions that are designed specifically to scale in
1354 Say Y here to make use of these instructions for the in-kernel
1355 atomic routines. This incurs a small overhead on CPUs that do
1356 not support these instructions and requires the kernel to be
1357 built with binutils >= 2.25 in order for the new instructions
1361 bool "Enable support for Virtualization Host Extensions (VHE)"
1364 Virtualization Host Extensions (VHE) allow the kernel to run
1365 directly at EL2 (instead of EL1) on processors that support
1366 it. This leads to better performance for KVM, as they reduce
1367 the cost of the world switch.
1369 Selecting this option allows the VHE feature to be detected
1370 at runtime, and does not affect processors that do not
1371 implement this feature.
1375 menu "ARMv8.2 architectural features"
1378 bool "Enable support for User Access Override (UAO)"
1381 User Access Override (UAO; part of the ARMv8.2 Extensions)
1382 causes the 'unprivileged' variant of the load/store instructions to
1383 be overridden to be privileged.
1385 This option changes get_user() and friends to use the 'unprivileged'
1386 variant of the load/store instructions. This ensures that user-space
1387 really did have access to the supplied memory. When addr_limit is
1388 set to kernel memory the UAO bit will be set, allowing privileged
1389 access to kernel memory.
1391 Choosing this option will cause copy_to_user() et al to use user-space
1394 The feature is detected at runtime, the kernel will use the
1395 regular load/store instructions if the cpu does not implement the
1399 bool "Enable support for persistent memory"
1400 select ARCH_HAS_PMEM_API
1401 select ARCH_HAS_UACCESS_FLUSHCACHE
1403 Say Y to enable support for the persistent memory API based on the
1404 ARMv8.2 DCPoP feature.
1406 The feature is detected at runtime, and the kernel will use DC CVAC
1407 operations if DC CVAP is not supported (following the behaviour of
1408 DC CVAP itself if the system does not define a point of persistence).
1410 config ARM64_RAS_EXTN
1411 bool "Enable support for RAS CPU Extensions"
1414 CPUs that support the Reliability, Availability and Serviceability
1415 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1416 errors, classify them and report them to software.
1418 On CPUs with these extensions system software can use additional
1419 barriers to determine if faults are pending and read the
1420 classification from a new set of registers.
1422 Selecting this feature will allow the kernel to use these barriers
1423 and access the new registers if the system supports the extension.
1424 Platform RAS features may additionally depend on firmware support.
1427 bool "Enable support for Common Not Private (CNP) translations"
1429 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1431 Common Not Private (CNP) allows translation table entries to
1432 be shared between different PEs in the same inner shareable
1433 domain, so the hardware can use this fact to optimise the
1434 caching of such entries in the TLB.
1436 Selecting this option allows the CNP feature to be detected
1437 at runtime, and does not affect PEs that do not implement
1442 menu "ARMv8.3 architectural features"
1444 config ARM64_PTR_AUTH
1445 bool "Enable support for pointer authentication"
1447 depends on !KVM || ARM64_VHE
1449 Pointer authentication (part of the ARMv8.3 Extensions) provides
1450 instructions for signing and authenticating pointers against secret
1451 keys, which can be used to mitigate Return Oriented Programming (ROP)
1454 This option enables these instructions at EL0 (i.e. for userspace).
1456 Choosing this option will cause the kernel to initialise secret keys
1457 for each process at exec() time, with these keys being
1458 context-switched along with the process.
1460 The feature is detected at runtime. If the feature is not present in
1461 hardware it will not be advertised to userspace/KVM guest nor will it
1462 be enabled. However, KVM guest also require VHE mode and hence
1463 CONFIG_ARM64_VHE=y option to use this feature.
1468 bool "ARM Scalable Vector Extension support"
1470 depends on !KVM || ARM64_VHE
1472 The Scalable Vector Extension (SVE) is an extension to the AArch64
1473 execution state which complements and extends the SIMD functionality
1474 of the base architecture to support much larger vectors and to enable
1475 additional vectorisation opportunities.
1477 To enable use of this extension on CPUs that implement it, say Y.
1479 On CPUs that support the SVE2 extensions, this option will enable
1482 Note that for architectural reasons, firmware _must_ implement SVE
1483 support when running on SVE capable hardware. The required support
1486 * version 1.5 and later of the ARM Trusted Firmware
1487 * the AArch64 boot wrapper since commit 5e1261e08abf
1488 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1490 For other firmware implementations, consult the firmware documentation
1493 If you need the kernel to boot on SVE-capable hardware with broken
1494 firmware, you may need to say N here until you get your firmware
1495 fixed. Otherwise, you may experience firmware panics or lockups when
1496 booting the kernel. If unsure and you are not observing these
1497 symptoms, you should assume that it is safe to say Y.
1499 CPUs that support SVE are architecturally required to support the
1500 Virtualization Host Extensions (VHE), so the kernel makes no
1501 provision for supporting SVE alongside KVM without VHE enabled.
1502 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1503 KVM in the same kernel image.
1505 config ARM64_MODULE_PLTS
1506 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1508 select HAVE_MOD_ARCH_SPECIFIC
1510 Allocate PLTs when loading modules so that jumps and calls whose
1511 targets are too far away for their relative offsets to be encoded
1512 in the instructions themselves can be bounced via veneers in the
1513 module's PLT. This allows modules to be allocated in the generic
1514 vmalloc area after the dedicated module memory area has been
1517 When running with address space randomization (KASLR), the module
1518 region itself may be too far away for ordinary relative jumps and
1519 calls, and so in that case, module PLTs are required and cannot be
1522 Specific errata workaround(s) might also force module PLTs to be
1523 enabled (ARM64_ERRATUM_843419).
1525 config ARM64_PSEUDO_NMI
1526 bool "Support for NMI-like interrupts"
1527 select CONFIG_ARM_GIC_V3
1529 Adds support for mimicking Non-Maskable Interrupts through the use of
1530 GIC interrupt priority. This support requires version 3 or later of
1533 This high priority configuration for interrupts needs to be
1534 explicitly enabled by setting the kernel parameter
1535 "irqchip.gicv3_pseudo_nmi" to 1.
1540 config ARM64_DEBUG_PRIORITY_MASKING
1541 bool "Debug interrupt priority masking"
1543 This adds runtime checks to functions enabling/disabling
1544 interrupts when using priority masking. The additional checks verify
1545 the validity of ICC_PMR_EL1 when calling concerned functions.
1552 select ARCH_HAS_RELR
1554 This builds the kernel as a Position Independent Executable (PIE),
1555 which retains all relocation metadata required to relocate the
1556 kernel binary at runtime to a different virtual address than the
1557 address it was linked at.
1558 Since AArch64 uses the RELA relocation format, this requires a
1559 relocation pass at runtime even if the kernel is loaded at the
1560 same address it was linked at.
1562 config RANDOMIZE_BASE
1563 bool "Randomize the address of the kernel image"
1564 select ARM64_MODULE_PLTS if MODULES
1567 Randomizes the virtual address at which the kernel image is
1568 loaded, as a security feature that deters exploit attempts
1569 relying on knowledge of the location of kernel internals.
1571 It is the bootloader's job to provide entropy, by passing a
1572 random u64 value in /chosen/kaslr-seed at kernel entry.
1574 When booting via the UEFI stub, it will invoke the firmware's
1575 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1576 to the kernel proper. In addition, it will randomise the physical
1577 location of the kernel Image as well.
1581 config RANDOMIZE_MODULE_REGION_FULL
1582 bool "Randomize the module region over a 4 GB range"
1583 depends on RANDOMIZE_BASE
1586 Randomizes the location of the module region inside a 4 GB window
1587 covering the core kernel. This way, it is less likely for modules
1588 to leak information about the location of core kernel data structures
1589 but it does imply that function calls between modules and the core
1590 kernel will need to be resolved via veneers in the module PLT.
1592 When this option is not set, the module region will be randomized over
1593 a limited range that contains the [_stext, _etext] interval of the
1594 core kernel, so branch relocations are always in range.
1596 config CC_HAVE_STACKPROTECTOR_SYSREG
1597 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1599 config STACKPROTECTOR_PER_TASK
1601 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1607 config ARM64_ACPI_PARKING_PROTOCOL
1608 bool "Enable support for the ARM64 ACPI parking protocol"
1611 Enable support for the ARM64 ACPI parking protocol. If disabled
1612 the kernel will not allow booting through the ARM64 ACPI parking
1613 protocol even if the corresponding data is present in the ACPI
1617 string "Default kernel command string"
1620 Provide a set of default command-line options at build time by
1621 entering them here. As a minimum, you should specify the the
1622 root device (e.g. root=/dev/nfs).
1624 config CMDLINE_FORCE
1625 bool "Always use the default kernel command string"
1627 Always use the default kernel command string, even if the boot
1628 loader passes other arguments to the kernel.
1629 This is useful if you cannot or don't want to change the
1630 command-line options your boot loader passes to the kernel.
1636 bool "UEFI runtime support"
1637 depends on OF && !CPU_BIG_ENDIAN
1638 depends on KERNEL_MODE_NEON
1639 select ARCH_SUPPORTS_ACPI
1642 select EFI_PARAMS_FROM_FDT
1643 select EFI_RUNTIME_WRAPPERS
1648 This option provides support for runtime services provided
1649 by UEFI firmware (such as non-volatile variables, realtime
1650 clock, and platform reset). A UEFI stub is also provided to
1651 allow the kernel to be booted as an EFI application. This
1652 is only useful on systems that have UEFI firmware.
1655 bool "Enable support for SMBIOS (DMI) tables"
1659 This enables SMBIOS/DMI feature for systems.
1661 This option is only useful on systems that have UEFI firmware.
1662 However, even with this option, the resultant kernel should
1663 continue to boot on existing non-UEFI platforms.
1667 config SYSVIPC_COMPAT
1669 depends on COMPAT && SYSVIPC
1671 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1673 depends on HUGETLB_PAGE && MIGRATION
1675 menu "Power management options"
1677 source "kernel/power/Kconfig"
1679 config ARCH_HIBERNATION_POSSIBLE
1683 config ARCH_HIBERNATION_HEADER
1685 depends on HIBERNATION
1687 config ARCH_SUSPEND_POSSIBLE
1692 menu "CPU Power Management"
1694 source "drivers/cpuidle/Kconfig"
1696 source "drivers/cpufreq/Kconfig"
1700 source "drivers/firmware/Kconfig"
1702 source "drivers/acpi/Kconfig"
1704 source "arch/arm64/kvm/Kconfig"
1707 source "arch/arm64/crypto/Kconfig"