1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_EXTRA_PHDRS
14 select ARCH_BINFMT_ELF_STATE
15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
17 select ARCH_ENABLE_MEMORY_HOTPLUG
18 select ARCH_ENABLE_MEMORY_HOTREMOVE
19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
21 select ARCH_HAS_CACHE_LINE_SIZE
22 select ARCH_HAS_CURRENT_STACK_POINTER
23 select ARCH_HAS_DEBUG_VIRTUAL
24 select ARCH_HAS_DEBUG_VM_PGTABLE
25 select ARCH_HAS_DMA_PREP_COHERENT
26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
27 select ARCH_HAS_FAST_MULTIPLIER
28 select ARCH_HAS_FORTIFY_SOURCE
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_HAS_GIGANTIC_PAGE
32 select ARCH_HAS_KEEPINITRD
33 select ARCH_HAS_MEMBARRIER_SYNC_CORE
34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
35 select ARCH_HAS_PTE_DEVMAP
36 select ARCH_HAS_PTE_SPECIAL
37 select ARCH_HAS_SETUP_DMA_OPS
38 select ARCH_HAS_SET_DIRECT_MAP
39 select ARCH_HAS_SET_MEMORY
41 select ARCH_HAS_STRICT_KERNEL_RWX
42 select ARCH_HAS_STRICT_MODULE_RWX
43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
44 select ARCH_HAS_SYNC_DMA_FOR_CPU
45 select ARCH_HAS_SYSCALL_WRAPPER
46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
48 select ARCH_HAS_VM_GET_PAGE_PROT
49 select ARCH_HAS_ZONE_DMA_SET if EXPERT
50 select ARCH_HAVE_ELF_PROT
51 select ARCH_HAVE_NMI_SAFE_CMPXCHG
52 select ARCH_INLINE_READ_LOCK if !PREEMPTION
53 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
54 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
56 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
57 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
60 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
61 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
64 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
65 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
68 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
69 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
70 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
74 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
75 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
78 select ARCH_KEEP_MEMBLOCK
79 select ARCH_USE_CMPXCHG_LOCKREF
80 select ARCH_USE_GNU_PROPERTY
81 select ARCH_USE_MEMTEST
82 select ARCH_USE_QUEUED_RWLOCKS
83 select ARCH_USE_QUEUED_SPINLOCKS
84 select ARCH_USE_SYM_ANNOTATIONS
85 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
86 select ARCH_SUPPORTS_HUGETLBFS
87 select ARCH_SUPPORTS_MEMORY_FAILURE
88 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
89 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
90 select ARCH_SUPPORTS_LTO_CLANG_THIN
91 select ARCH_SUPPORTS_CFI_CLANG
92 select ARCH_SUPPORTS_ATOMIC_RMW
93 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
94 select ARCH_SUPPORTS_NUMA_BALANCING
95 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
96 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
97 select ARCH_WANT_DEFAULT_BPF_JIT
98 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
99 select ARCH_WANT_FRAME_POINTERS
100 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
101 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
102 select ARCH_WANT_LD_ORPHAN_WARN
103 select ARCH_WANTS_NO_INSTR
104 select ARCH_HAS_UBSAN_SANITIZE_ALL
106 select ARM_ARCH_TIMER
108 select AUDIT_ARCH_COMPAT_GENERIC
109 select ARM_GIC_V2M if PCI
111 select ARM_GIC_V3_ITS if PCI
113 select BUILDTIME_TABLE_SORT
114 select CLONE_BACKWARDS
116 select CPU_PM if (SUSPEND || CPU_IDLE)
118 select DCACHE_WORD_ACCESS
119 select DMA_DIRECT_REMAP
122 select GENERIC_ALLOCATOR
123 select GENERIC_ARCH_TOPOLOGY
124 select GENERIC_CLOCKEVENTS_BROADCAST
125 select GENERIC_CPU_AUTOPROBE
126 select GENERIC_CPU_VULNERABILITIES
127 select GENERIC_EARLY_IOREMAP
128 select GENERIC_IDLE_POLL_SETUP
129 select GENERIC_IRQ_IPI
130 select GENERIC_IRQ_PROBE
131 select GENERIC_IRQ_SHOW
132 select GENERIC_IRQ_SHOW_LEVEL
133 select GENERIC_LIB_DEVMEM_IS_ALLOWED
134 select GENERIC_PCI_IOMAP
135 select GENERIC_PTDUMP
136 select GENERIC_SCHED_CLOCK
137 select GENERIC_SMP_IDLE_THREAD
138 select GENERIC_TIME_VSYSCALL
139 select GENERIC_GETTIMEOFDAY
140 select GENERIC_VDSO_TIME_NS
141 select HARDIRQS_SW_RESEND
145 select HAVE_ACPI_APEI if (ACPI && EFI)
146 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
147 select HAVE_ARCH_AUDITSYSCALL
148 select HAVE_ARCH_BITREVERSE
149 select HAVE_ARCH_COMPILER_H
150 select HAVE_ARCH_HUGE_VMAP
151 select HAVE_ARCH_JUMP_LABEL
152 select HAVE_ARCH_JUMP_LABEL_RELATIVE
153 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
154 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
155 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
156 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
157 # Some instrumentation may be unsound, hence EXPERT
158 select HAVE_ARCH_KCSAN if EXPERT
159 select HAVE_ARCH_KFENCE
160 select HAVE_ARCH_KGDB
161 select HAVE_ARCH_MMAP_RND_BITS
162 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
163 select HAVE_ARCH_PREL32_RELOCATIONS
164 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
165 select HAVE_ARCH_SECCOMP_FILTER
166 select HAVE_ARCH_STACKLEAK
167 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
168 select HAVE_ARCH_TRACEHOOK
169 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
170 select HAVE_ARCH_VMAP_STACK
171 select HAVE_ARM_SMCCC
172 select HAVE_ASM_MODVERSIONS
174 select HAVE_C_RECORDMCOUNT
175 select HAVE_CMPXCHG_DOUBLE
176 select HAVE_CMPXCHG_LOCAL
177 select HAVE_CONTEXT_TRACKING
178 select HAVE_DEBUG_KMEMLEAK
179 select HAVE_DMA_CONTIGUOUS
180 select HAVE_DYNAMIC_FTRACE
181 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
182 if DYNAMIC_FTRACE_WITH_REGS
183 select HAVE_EFFICIENT_UNALIGNED_ACCESS
185 select HAVE_FTRACE_MCOUNT_RECORD
186 select HAVE_FUNCTION_TRACER
187 select HAVE_FUNCTION_ERROR_INJECTION
188 select HAVE_FUNCTION_GRAPH_TRACER
189 select HAVE_GCC_PLUGINS
190 select HAVE_HW_BREAKPOINT if PERF_EVENTS
191 select HAVE_IRQ_TIME_ACCOUNTING
194 select HAVE_PATA_PLATFORM
195 select HAVE_PERF_EVENTS
196 select HAVE_PERF_REGS
197 select HAVE_PERF_USER_STACK_DUMP
198 select HAVE_PREEMPT_DYNAMIC_KEY
199 select HAVE_REGS_AND_STACK_ACCESS_API
200 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
201 select HAVE_FUNCTION_ARG_ACCESS_API
202 select MMU_GATHER_RCU_TABLE_FREE
204 select HAVE_STACKPROTECTOR
205 select HAVE_SYSCALL_TRACEPOINTS
207 select HAVE_KRETPROBES
208 select HAVE_GENERIC_VDSO
209 select IOMMU_DMA if IOMMU_SUPPORT
211 select IRQ_FORCED_THREADING
212 select KASAN_VMALLOC if KASAN
213 select MODULES_USE_ELF_RELA
214 select NEED_DMA_MAP_STATE
215 select NEED_SG_DMA_LENGTH
217 select OF_EARLY_FLATTREE
218 select PCI_DOMAINS_GENERIC if PCI
219 select PCI_ECAM if (ACPI && PCI)
220 select PCI_SYSCALL if PCI
225 select SYSCTL_EXCEPTION_TRACE
226 select THREAD_INFO_IN_TASK
227 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
228 select TRACE_IRQFLAGS_SUPPORT
230 ARM 64-bit (AArch64) Linux support.
232 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
234 # https://github.com/ClangBuiltLinux/linux/issues/1507
235 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
236 select HAVE_DYNAMIC_FTRACE_WITH_REGS
238 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
240 depends on $(cc-option,-fpatchable-function-entry=2)
241 select HAVE_DYNAMIC_FTRACE_WITH_REGS
249 config ARM64_PAGE_SHIFT
251 default 16 if ARM64_64K_PAGES
252 default 14 if ARM64_16K_PAGES
255 config ARM64_CONT_PTE_SHIFT
257 default 5 if ARM64_64K_PAGES
258 default 7 if ARM64_16K_PAGES
261 config ARM64_CONT_PMD_SHIFT
263 default 5 if ARM64_64K_PAGES
264 default 5 if ARM64_16K_PAGES
267 config ARCH_MMAP_RND_BITS_MIN
268 default 14 if ARM64_64K_PAGES
269 default 16 if ARM64_16K_PAGES
272 # max bits determined by the following formula:
273 # VA_BITS - PAGE_SHIFT - 3
274 config ARCH_MMAP_RND_BITS_MAX
275 default 19 if ARM64_VA_BITS=36
276 default 24 if ARM64_VA_BITS=39
277 default 27 if ARM64_VA_BITS=42
278 default 30 if ARM64_VA_BITS=47
279 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
280 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
281 default 33 if ARM64_VA_BITS=48
282 default 14 if ARM64_64K_PAGES
283 default 16 if ARM64_16K_PAGES
286 config ARCH_MMAP_RND_COMPAT_BITS_MIN
287 default 7 if ARM64_64K_PAGES
288 default 9 if ARM64_16K_PAGES
291 config ARCH_MMAP_RND_COMPAT_BITS_MAX
297 config STACKTRACE_SUPPORT
300 config ILLEGAL_POINTER_VALUE
302 default 0xdead000000000000
304 config LOCKDEP_SUPPORT
311 config GENERIC_BUG_RELATIVE_POINTERS
313 depends on GENERIC_BUG
315 config GENERIC_HWEIGHT
321 config GENERIC_CALIBRATE_DELAY
324 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
330 config KERNEL_MODE_NEON
333 config FIX_EARLYCON_MEM
336 config PGTABLE_LEVELS
338 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
339 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
340 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
341 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
342 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
343 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
345 config ARCH_SUPPORTS_UPROBES
348 config ARCH_PROC_KCORE_TEXT
351 config BROKEN_GAS_INST
352 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
354 config KASAN_SHADOW_OFFSET
356 depends on KASAN_GENERIC || KASAN_SW_TAGS
357 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
358 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
359 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
360 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
361 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
362 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
363 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
364 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
365 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
366 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
367 default 0xffffffffffffffff
369 source "arch/arm64/Kconfig.platforms"
371 menu "Kernel Features"
373 menu "ARM errata workarounds via the alternatives framework"
375 config ARM64_WORKAROUND_CLEAN_CACHE
378 config ARM64_ERRATUM_826319
379 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
381 select ARM64_WORKAROUND_CLEAN_CACHE
383 This option adds an alternative code sequence to work around ARM
384 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
385 AXI master interface and an L2 cache.
387 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
388 and is unable to accept a certain write via this interface, it will
389 not progress on read data presented on the read data channel and the
392 The workaround promotes data cache clean instructions to
393 data cache clean-and-invalidate.
394 Please note that this does not necessarily enable the workaround,
395 as it depends on the alternative framework, which will only patch
396 the kernel if an affected CPU is detected.
400 config ARM64_ERRATUM_827319
401 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
403 select ARM64_WORKAROUND_CLEAN_CACHE
405 This option adds an alternative code sequence to work around ARM
406 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
407 master interface and an L2 cache.
409 Under certain conditions this erratum can cause a clean line eviction
410 to occur at the same time as another transaction to the same address
411 on the AMBA 5 CHI interface, which can cause data corruption if the
412 interconnect reorders the two transactions.
414 The workaround promotes data cache clean instructions to
415 data cache clean-and-invalidate.
416 Please note that this does not necessarily enable the workaround,
417 as it depends on the alternative framework, which will only patch
418 the kernel if an affected CPU is detected.
422 config ARM64_ERRATUM_824069
423 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
425 select ARM64_WORKAROUND_CLEAN_CACHE
427 This option adds an alternative code sequence to work around ARM
428 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
429 to a coherent interconnect.
431 If a Cortex-A53 processor is executing a store or prefetch for
432 write instruction at the same time as a processor in another
433 cluster is executing a cache maintenance operation to the same
434 address, then this erratum might cause a clean cache line to be
435 incorrectly marked as dirty.
437 The workaround promotes data cache clean instructions to
438 data cache clean-and-invalidate.
439 Please note that this option does not necessarily enable the
440 workaround, as it depends on the alternative framework, which will
441 only patch the kernel if an affected CPU is detected.
445 config ARM64_ERRATUM_819472
446 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
448 select ARM64_WORKAROUND_CLEAN_CACHE
450 This option adds an alternative code sequence to work around ARM
451 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
452 present when it is connected to a coherent interconnect.
454 If the processor is executing a load and store exclusive sequence at
455 the same time as a processor in another cluster is executing a cache
456 maintenance operation to the same address, then this erratum might
457 cause data corruption.
459 The workaround promotes data cache clean instructions to
460 data cache clean-and-invalidate.
461 Please note that this does not necessarily enable the workaround,
462 as it depends on the alternative framework, which will only patch
463 the kernel if an affected CPU is detected.
467 config ARM64_ERRATUM_832075
468 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
471 This option adds an alternative code sequence to work around ARM
472 erratum 832075 on Cortex-A57 parts up to r1p2.
474 Affected Cortex-A57 parts might deadlock when exclusive load/store
475 instructions to Write-Back memory are mixed with Device loads.
477 The workaround is to promote device loads to use Load-Acquire
479 Please note that this does not necessarily enable the workaround,
480 as it depends on the alternative framework, which will only patch
481 the kernel if an affected CPU is detected.
485 config ARM64_ERRATUM_834220
486 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
490 This option adds an alternative code sequence to work around ARM
491 erratum 834220 on Cortex-A57 parts up to r1p2.
493 Affected Cortex-A57 parts might report a Stage 2 translation
494 fault as the result of a Stage 1 fault for load crossing a
495 page boundary when there is a permission or device memory
496 alignment fault at Stage 1 and a translation fault at Stage 2.
498 The workaround is to verify that the Stage 1 translation
499 doesn't generate a fault before handling the Stage 2 fault.
500 Please note that this does not necessarily enable the workaround,
501 as it depends on the alternative framework, which will only patch
502 the kernel if an affected CPU is detected.
506 config ARM64_ERRATUM_845719
507 bool "Cortex-A53: 845719: a load might read incorrect data"
511 This option adds an alternative code sequence to work around ARM
512 erratum 845719 on Cortex-A53 parts up to r0p4.
514 When running a compat (AArch32) userspace on an affected Cortex-A53
515 part, a load at EL0 from a virtual address that matches the bottom 32
516 bits of the virtual address used by a recent load at (AArch64) EL1
517 might return incorrect data.
519 The workaround is to write the contextidr_el1 register on exception
520 return to a 32-bit task.
521 Please note that this does not necessarily enable the workaround,
522 as it depends on the alternative framework, which will only patch
523 the kernel if an affected CPU is detected.
527 config ARM64_ERRATUM_843419
528 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
530 select ARM64_MODULE_PLTS if MODULES
532 This option links the kernel with '--fix-cortex-a53-843419' and
533 enables PLT support to replace certain ADRP instructions, which can
534 cause subsequent memory accesses to use an incorrect address on
535 Cortex-A53 parts up to r0p4.
539 config ARM64_LD_HAS_FIX_ERRATUM_843419
540 def_bool $(ld-option,--fix-cortex-a53-843419)
542 config ARM64_ERRATUM_1024718
543 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
546 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
548 Affected Cortex-A55 cores (all revisions) could cause incorrect
549 update of the hardware dirty bit when the DBM/AP bits are updated
550 without a break-before-make. The workaround is to disable the usage
551 of hardware DBM locally on the affected cores. CPUs not affected by
552 this erratum will continue to use the feature.
556 config ARM64_ERRATUM_1418040
557 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
561 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
562 errata 1188873 and 1418040.
564 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
565 cause register corruption when accessing the timer registers
566 from AArch32 userspace.
570 config ARM64_WORKAROUND_SPECULATIVE_AT
573 config ARM64_ERRATUM_1165522
574 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
576 select ARM64_WORKAROUND_SPECULATIVE_AT
578 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
580 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
581 corrupted TLBs by speculating an AT instruction during a guest
586 config ARM64_ERRATUM_1319367
587 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
589 select ARM64_WORKAROUND_SPECULATIVE_AT
591 This option adds work arounds for ARM Cortex-A57 erratum 1319537
592 and A72 erratum 1319367
594 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
595 speculating an AT instruction during a guest context switch.
599 config ARM64_ERRATUM_1530923
600 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
602 select ARM64_WORKAROUND_SPECULATIVE_AT
604 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
606 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
607 corrupted TLBs by speculating an AT instruction during a guest
612 config ARM64_WORKAROUND_REPEAT_TLBI
615 config ARM64_ERRATUM_1286807
616 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
618 select ARM64_WORKAROUND_REPEAT_TLBI
620 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
622 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
623 address for a cacheable mapping of a location is being
624 accessed by a core while another core is remapping the virtual
625 address to a new physical page using the recommended
626 break-before-make sequence, then under very rare circumstances
627 TLBI+DSB completes before a read using the translation being
628 invalidated has been observed by other observers. The
629 workaround repeats the TLBI+DSB operation.
631 config ARM64_ERRATUM_1463225
632 bool "Cortex-A76: Software Step might prevent interrupt recognition"
635 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
637 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
638 of a system call instruction (SVC) can prevent recognition of
639 subsequent interrupts when software stepping is disabled in the
640 exception handler of the system call and either kernel debugging
641 is enabled or VHE is in use.
643 Work around the erratum by triggering a dummy step exception
644 when handling a system call from a task that is being stepped
645 in a VHE configuration of the kernel.
649 config ARM64_ERRATUM_1542419
650 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
653 This option adds a workaround for ARM Neoverse-N1 erratum
656 Affected Neoverse-N1 cores could execute a stale instruction when
657 modified by another CPU. The workaround depends on a firmware
660 Workaround the issue by hiding the DIC feature from EL0. This
661 forces user-space to perform cache maintenance.
665 config ARM64_ERRATUM_1508412
666 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
669 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
671 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
672 of a store-exclusive or read of PAR_EL1 and a load with device or
673 non-cacheable memory attributes. The workaround depends on a firmware
676 KVM guests must also have the workaround implemented or they can
679 Work around the issue by inserting DMB SY barriers around PAR_EL1
680 register reads and warning KVM users. The DMB barrier is sufficient
681 to prevent a speculative PAR_EL1 read.
685 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
688 config ARM64_ERRATUM_2051678
689 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
692 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
693 Affected Cortex-A510 might not respect the ordering rules for
694 hardware update of the page table's dirty bit. The workaround
695 is to not enable the feature on affected CPUs.
699 config ARM64_ERRATUM_2077057
700 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
703 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
704 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
705 expected, but a Pointer Authentication trap is taken instead. The
706 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
707 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
709 This can only happen when EL2 is stepping EL1.
711 When these conditions occur, the SPSR_EL2 value is unchanged from the
712 previous guest entry, and can be restored from the in-memory copy.
716 config ARM64_ERRATUM_2119858
717 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
719 depends on CORESIGHT_TRBE
720 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
722 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
724 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
725 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
726 the event of a WRAP event.
728 Work around the issue by always making sure we move the TRBPTR_EL1 by
729 256 bytes before enabling the buffer and filling the first 256 bytes of
730 the buffer with ETM ignore packets upon disabling.
734 config ARM64_ERRATUM_2139208
735 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
737 depends on CORESIGHT_TRBE
738 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
740 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
742 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
743 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
744 the event of a WRAP event.
746 Work around the issue by always making sure we move the TRBPTR_EL1 by
747 256 bytes before enabling the buffer and filling the first 256 bytes of
748 the buffer with ETM ignore packets upon disabling.
752 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
755 config ARM64_ERRATUM_2054223
756 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
758 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
760 Enable workaround for ARM Cortex-A710 erratum 2054223
762 Affected cores may fail to flush the trace data on a TSB instruction, when
763 the PE is in trace prohibited state. This will cause losing a few bytes
766 Workaround is to issue two TSB consecutively on affected cores.
770 config ARM64_ERRATUM_2067961
771 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
773 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
775 Enable workaround for ARM Neoverse-N2 erratum 2067961
777 Affected cores may fail to flush the trace data on a TSB instruction, when
778 the PE is in trace prohibited state. This will cause losing a few bytes
781 Workaround is to issue two TSB consecutively on affected cores.
785 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
788 config ARM64_ERRATUM_2253138
789 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
790 depends on CORESIGHT_TRBE
792 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
794 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
796 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
797 for TRBE. Under some conditions, the TRBE might generate a write to the next
798 virtually addressed page following the last page of the TRBE address space
799 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
801 Work around this in the driver by always making sure that there is a
802 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
806 config ARM64_ERRATUM_2224489
807 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
808 depends on CORESIGHT_TRBE
810 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
812 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
814 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
815 for TRBE. Under some conditions, the TRBE might generate a write to the next
816 virtually addressed page following the last page of the TRBE address space
817 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
819 Work around this in the driver by always making sure that there is a
820 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
824 config ARM64_ERRATUM_2064142
825 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
826 depends on CORESIGHT_TRBE
829 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
831 Affected Cortex-A510 core might fail to write into system registers after the
832 TRBE has been disabled. Under some conditions after the TRBE has been disabled
833 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
834 and TRBTRG_EL1 will be ignored and will not be effected.
836 Work around this in the driver by executing TSB CSYNC and DSB after collection
837 is stopped and before performing a system register write to one of the affected
842 config ARM64_ERRATUM_2038923
843 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
844 depends on CORESIGHT_TRBE
847 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
849 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
850 prohibited within the CPU. As a result, the trace buffer or trace buffer state
851 might be corrupted. This happens after TRBE buffer has been enabled by setting
852 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
853 execution changes from a context, in which trace is prohibited to one where it
854 isn't, or vice versa. In these mentioned conditions, the view of whether trace
855 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
856 the trace buffer state might be corrupted.
858 Work around this in the driver by preventing an inconsistent view of whether the
859 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
860 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
861 two ISB instructions if no ERET is to take place.
865 config ARM64_ERRATUM_1902691
866 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
867 depends on CORESIGHT_TRBE
870 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
872 Affected Cortex-A510 core might cause trace data corruption, when being written
873 into the memory. Effectively TRBE is broken and hence cannot be used to capture
876 Work around this problem in the driver by just preventing TRBE initialization on
877 affected cpus. The firmware must have disabled the access to TRBE for the kernel
878 on such implementations. This will cover the kernel for any firmware that doesn't
883 config CAVIUM_ERRATUM_22375
884 bool "Cavium erratum 22375, 24313"
887 Enable workaround for errata 22375 and 24313.
889 This implements two gicv3-its errata workarounds for ThunderX. Both
890 with a small impact affecting only ITS table allocation.
892 erratum 22375: only alloc 8MB table size
893 erratum 24313: ignore memory access type
895 The fixes are in ITS initialization and basically ignore memory access
896 type and table size provided by the TYPER and BASER registers.
900 config CAVIUM_ERRATUM_23144
901 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
905 ITS SYNC command hang for cross node io and collections/cpu mapping.
909 config CAVIUM_ERRATUM_23154
910 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
913 The ThunderX GICv3 implementation requires a modified version for
914 reading the IAR status to ensure data synchronization
915 (access to icc_iar1_el1 is not sync'ed before and after).
917 It also suffers from erratum 38545 (also present on Marvell's
918 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
919 spuriously presented to the CPU interface.
923 config CAVIUM_ERRATUM_27456
924 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
927 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
928 instructions may cause the icache to become corrupted if it
929 contains data for a non-current ASID. The fix is to
930 invalidate the icache when changing the mm context.
934 config CAVIUM_ERRATUM_30115
935 bool "Cavium erratum 30115: Guest may disable interrupts in host"
938 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
939 1.2, and T83 Pass 1.0, KVM guest execution may disable
940 interrupts in host. Trapping both GICv3 group-0 and group-1
941 accesses sidesteps the issue.
945 config CAVIUM_TX2_ERRATUM_219
946 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
949 On Cavium ThunderX2, a load, store or prefetch instruction between a
950 TTBR update and the corresponding context synchronizing operation can
951 cause a spurious Data Abort to be delivered to any hardware thread in
954 Work around the issue by avoiding the problematic code sequence and
955 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
956 trap handler performs the corresponding register access, skips the
957 instruction and ensures context synchronization by virtue of the
962 config FUJITSU_ERRATUM_010001
963 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
966 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
967 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
968 accesses may cause undefined fault (Data abort, DFSC=0b111111).
969 This fault occurs under a specific hardware condition when a
970 load/store instruction performs an address translation using:
971 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
972 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
973 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
974 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
976 The workaround is to ensure these bits are clear in TCR_ELx.
977 The workaround only affects the Fujitsu-A64FX.
981 config HISILICON_ERRATUM_161600802
982 bool "Hip07 161600802: Erroneous redistributor VLPI base"
985 The HiSilicon Hip07 SoC uses the wrong redistributor base
986 when issued ITS commands such as VMOVP and VMAPP, and requires
987 a 128kB offset to be applied to the target address in this commands.
991 config QCOM_FALKOR_ERRATUM_1003
992 bool "Falkor E1003: Incorrect translation due to ASID change"
995 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
996 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
997 in TTBR1_EL1, this situation only occurs in the entry trampoline and
998 then only for entries in the walk cache, since the leaf translation
999 is unchanged. Work around the erratum by invalidating the walk cache
1000 entries for the trampoline before entering the kernel proper.
1002 config QCOM_FALKOR_ERRATUM_1009
1003 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1005 select ARM64_WORKAROUND_REPEAT_TLBI
1007 On Falkor v1, the CPU may prematurely complete a DSB following a
1008 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1009 one more time to fix the issue.
1013 config QCOM_QDF2400_ERRATUM_0065
1014 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1017 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1018 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1019 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1023 config QCOM_FALKOR_ERRATUM_E1041
1024 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1027 Falkor CPU may speculatively fetch instructions from an improper
1028 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1029 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1033 config NVIDIA_CARMEL_CNP_ERRATUM
1034 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1037 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1038 invalidate shared TLB entries installed by a different core, as it would
1039 on standard ARM cores.
1043 config SOCIONEXT_SYNQUACER_PREITS
1044 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1047 Socionext Synquacer SoCs implement a separate h/w block to generate
1048 MSI doorbell writes with non-zero values for the device ID.
1052 endmenu # "ARM errata workarounds via the alternatives framework"
1056 default ARM64_4K_PAGES
1058 Page size (translation granule) configuration.
1060 config ARM64_4K_PAGES
1063 This feature enables 4KB pages support.
1065 config ARM64_16K_PAGES
1068 The system will use 16KB pages support. AArch32 emulation
1069 requires applications compiled with 16K (or a multiple of 16K)
1072 config ARM64_64K_PAGES
1075 This feature enables 64KB pages support (4KB by default)
1076 allowing only two levels of page tables and faster TLB
1077 look-up. AArch32 emulation requires applications compiled
1078 with 64K aligned segments.
1083 prompt "Virtual address space size"
1084 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1085 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1086 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1088 Allows choosing one of multiple possible virtual address
1089 space sizes. The level of translation table is determined by
1090 a combination of page size and virtual address space size.
1092 config ARM64_VA_BITS_36
1093 bool "36-bit" if EXPERT
1094 depends on ARM64_16K_PAGES
1096 config ARM64_VA_BITS_39
1098 depends on ARM64_4K_PAGES
1100 config ARM64_VA_BITS_42
1102 depends on ARM64_64K_PAGES
1104 config ARM64_VA_BITS_47
1106 depends on ARM64_16K_PAGES
1108 config ARM64_VA_BITS_48
1111 config ARM64_VA_BITS_52
1113 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1115 Enable 52-bit virtual addressing for userspace when explicitly
1116 requested via a hint to mmap(). The kernel will also use 52-bit
1117 virtual addresses for its own mappings (provided HW support for
1118 this feature is available, otherwise it reverts to 48-bit).
1120 NOTE: Enabling 52-bit virtual addressing in conjunction with
1121 ARMv8.3 Pointer Authentication will result in the PAC being
1122 reduced from 7 bits to 3 bits, which may have a significant
1123 impact on its susceptibility to brute-force attacks.
1125 If unsure, select 48-bit virtual addressing instead.
1129 config ARM64_FORCE_52BIT
1130 bool "Force 52-bit virtual addresses for userspace"
1131 depends on ARM64_VA_BITS_52 && EXPERT
1133 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1134 to maintain compatibility with older software by providing 48-bit VAs
1135 unless a hint is supplied to mmap.
1137 This configuration option disables the 48-bit compatibility logic, and
1138 forces all userspace addresses to be 52-bit on HW that supports it. One
1139 should only enable this configuration option for stress testing userspace
1140 memory management code. If unsure say N here.
1142 config ARM64_VA_BITS
1144 default 36 if ARM64_VA_BITS_36
1145 default 39 if ARM64_VA_BITS_39
1146 default 42 if ARM64_VA_BITS_42
1147 default 47 if ARM64_VA_BITS_47
1148 default 48 if ARM64_VA_BITS_48
1149 default 52 if ARM64_VA_BITS_52
1152 prompt "Physical address space size"
1153 default ARM64_PA_BITS_48
1155 Choose the maximum physical address range that the kernel will
1158 config ARM64_PA_BITS_48
1161 config ARM64_PA_BITS_52
1162 bool "52-bit (ARMv8.2)"
1163 depends on ARM64_64K_PAGES
1164 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1166 Enable support for a 52-bit physical address space, introduced as
1167 part of the ARMv8.2-LPA extension.
1169 With this enabled, the kernel will also continue to work on CPUs that
1170 do not support ARMv8.2-LPA, but with some added memory overhead (and
1171 minor performance overhead).
1175 config ARM64_PA_BITS
1177 default 48 if ARM64_PA_BITS_48
1178 default 52 if ARM64_PA_BITS_52
1182 default CPU_LITTLE_ENDIAN
1184 Select the endianness of data accesses performed by the CPU. Userspace
1185 applications will need to be compiled and linked for the endianness
1186 that is selected here.
1188 config CPU_BIG_ENDIAN
1189 bool "Build big-endian kernel"
1190 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1192 Say Y if you plan on running a kernel with a big-endian userspace.
1194 config CPU_LITTLE_ENDIAN
1195 bool "Build little-endian kernel"
1197 Say Y if you plan on running a kernel with a little-endian userspace.
1198 This is usually the case for distributions targeting arm64.
1203 bool "Multi-core scheduler support"
1205 Multi-core scheduler support improves the CPU scheduler's decision
1206 making when dealing with multi-core CPU chips at a cost of slightly
1207 increased overhead in some places. If unsure say N here.
1209 config SCHED_CLUSTER
1210 bool "Cluster scheduler support"
1212 Cluster scheduler support improves the CPU scheduler's decision
1213 making when dealing with machines that have clusters of CPUs.
1214 Cluster usually means a couple of CPUs which are placed closely
1215 by sharing mid-level caches, last-level cache tags or internal
1219 bool "SMT scheduler support"
1221 Improves the CPU scheduler's decision making when dealing with
1222 MultiThreading at a cost of slightly increased overhead in some
1223 places. If unsure say N here.
1226 int "Maximum number of CPUs (2-4096)"
1231 bool "Support for hot-pluggable CPUs"
1232 select GENERIC_IRQ_MIGRATION
1234 Say Y here to experiment with turning CPUs off and on. CPUs
1235 can be controlled through /sys/devices/system/cpu.
1237 # Common NUMA Features
1239 bool "NUMA Memory Allocation and Scheduler Support"
1240 select GENERIC_ARCH_NUMA
1241 select ACPI_NUMA if ACPI
1243 select HAVE_SETUP_PER_CPU_AREA
1244 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1245 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1246 select USE_PERCPU_NUMA_NODE_ID
1248 Enable NUMA (Non-Uniform Memory Access) support.
1250 The kernel will try to allocate memory used by a CPU on the
1251 local memory of the CPU and add some more
1252 NUMA awareness to the kernel.
1255 int "Maximum NUMA Nodes (as a power of 2)"
1260 Specify the maximum number of NUMA Nodes available on the target
1261 system. Increases memory reserved to accommodate various tables.
1263 source "kernel/Kconfig.hz"
1265 config ARCH_SPARSEMEM_ENABLE
1267 select SPARSEMEM_VMEMMAP_ENABLE
1268 select SPARSEMEM_VMEMMAP
1270 config HW_PERF_EVENTS
1274 # Supported by clang >= 7.0 or GCC >= 12.0.0
1275 config CC_HAVE_SHADOW_CALL_STACK
1276 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1279 bool "Enable paravirtualization code"
1281 This changes the kernel so it can modify itself when it is run
1282 under a hypervisor, potentially improving performance significantly
1283 over full virtualization.
1285 config PARAVIRT_TIME_ACCOUNTING
1286 bool "Paravirtual steal time accounting"
1289 Select this option to enable fine granularity task steal time
1290 accounting. Time spent executing other tasks in parallel with
1291 the current vCPU is discounted from the vCPU power. To account for
1292 that, there can be a small performance impact.
1294 If in doubt, say N here.
1297 depends on PM_SLEEP_SMP
1299 bool "kexec system call"
1301 kexec is a system call that implements the ability to shutdown your
1302 current kernel, and to start another kernel. It is like a reboot
1303 but it is independent of the system firmware. And like a reboot
1304 you can start any kernel with it, not just Linux.
1307 bool "kexec file based system call"
1309 select HAVE_IMA_KEXEC if IMA
1311 This is new version of kexec system call. This system call is
1312 file based and takes file descriptors as system call argument
1313 for kernel and initramfs as opposed to list of segments as
1314 accepted by previous system call.
1317 bool "Verify kernel signature during kexec_file_load() syscall"
1318 depends on KEXEC_FILE
1320 Select this option to verify a signature with loaded kernel
1321 image. If configured, any attempt of loading a image without
1322 valid signature will fail.
1324 In addition to that option, you need to enable signature
1325 verification for the corresponding kernel image type being
1326 loaded in order for this to work.
1328 config KEXEC_IMAGE_VERIFY_SIG
1329 bool "Enable Image signature verification support"
1331 depends on KEXEC_SIG
1332 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1334 Enable Image signature verification support.
1336 comment "Support for PE file signature verification disabled"
1337 depends on KEXEC_SIG
1338 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1341 bool "Build kdump crash kernel"
1343 Generate crash dump after being started by kexec. This should
1344 be normally only set in special crash dump kernels which are
1345 loaded in the main kernel with kexec-tools into a specially
1346 reserved region and then later executed after a crash by
1349 For more details see Documentation/admin-guide/kdump/kdump.rst
1353 depends on HIBERNATION || KEXEC_CORE
1360 bool "Xen guest support on ARM64"
1361 depends on ARM64 && OF
1365 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1367 config FORCE_MAX_ZONEORDER
1369 default "14" if ARM64_64K_PAGES
1370 default "12" if ARM64_16K_PAGES
1373 The kernel memory allocator divides physically contiguous memory
1374 blocks into "zones", where each zone is a power of two number of
1375 pages. This option selects the largest power of two that the kernel
1376 keeps in the memory allocator. If you need to allocate very large
1377 blocks of physically contiguous memory, then you may need to
1378 increase this value.
1380 This config option is actually maximum order plus one. For example,
1381 a value of 11 means that the largest free memory block is 2^10 pages.
1383 We make sure that we can allocate upto a HugePage size for each configuration.
1385 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1387 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1388 4M allocations matching the default size used by generic code.
1390 config UNMAP_KERNEL_AT_EL0
1391 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1394 Speculation attacks against some high-performance processors can
1395 be used to bypass MMU permission checks and leak kernel data to
1396 userspace. This can be defended against by unmapping the kernel
1397 when running in userspace, mapping it back in on exception entry
1398 via a trampoline page in the vector table.
1402 config MITIGATE_SPECTRE_BRANCH_HISTORY
1403 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1406 Speculation attacks against some high-performance processors can
1407 make use of branch history to influence future speculation.
1408 When taking an exception from user-space, a sequence of branches
1409 or a firmware call overwrites the branch history.
1411 config RODATA_FULL_DEFAULT_ENABLED
1412 bool "Apply r/o permissions of VM areas also to their linear aliases"
1415 Apply read-only attributes of VM areas to the linear alias of
1416 the backing pages as well. This prevents code or read-only data
1417 from being modified (inadvertently or intentionally) via another
1418 mapping of the same memory page. This additional enhancement can
1419 be turned off at runtime by passing rodata=[off|on] (and turned on
1420 with rodata=full if this option is set to 'n')
1422 This requires the linear region to be mapped down to pages,
1423 which may adversely affect performance in some cases.
1425 config ARM64_SW_TTBR0_PAN
1426 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1428 Enabling this option prevents the kernel from accessing
1429 user-space memory directly by pointing TTBR0_EL1 to a reserved
1430 zeroed area and reserved ASID. The user access routines
1431 restore the valid TTBR0_EL1 temporarily.
1433 config ARM64_TAGGED_ADDR_ABI
1434 bool "Enable the tagged user addresses syscall ABI"
1437 When this option is enabled, user applications can opt in to a
1438 relaxed ABI via prctl() allowing tagged addresses to be passed
1439 to system calls as pointer arguments. For details, see
1440 Documentation/arm64/tagged-address-abi.rst.
1443 bool "Kernel support for 32-bit EL0"
1444 depends on ARM64_4K_PAGES || EXPERT
1446 select OLD_SIGSUSPEND3
1447 select COMPAT_OLD_SIGACTION
1449 This option enables support for a 32-bit EL0 running under a 64-bit
1450 kernel at EL1. AArch32-specific components such as system calls,
1451 the user helper functions, VFP support and the ptrace interface are
1452 handled appropriately by the kernel.
1454 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1455 that you will only be able to execute AArch32 binaries that were compiled
1456 with page size aligned segments.
1458 If you want to execute 32-bit userspace applications, say Y.
1462 config KUSER_HELPERS
1463 bool "Enable kuser helpers page for 32-bit applications"
1466 Warning: disabling this option may break 32-bit user programs.
1468 Provide kuser helpers to compat tasks. The kernel provides
1469 helper code to userspace in read only form at a fixed location
1470 to allow userspace to be independent of the CPU type fitted to
1471 the system. This permits binaries to be run on ARMv4 through
1472 to ARMv8 without modification.
1474 See Documentation/arm/kernel_user_helpers.rst for details.
1476 However, the fixed address nature of these helpers can be used
1477 by ROP (return orientated programming) authors when creating
1480 If all of the binaries and libraries which run on your platform
1481 are built specifically for your platform, and make no use of
1482 these helpers, then you can turn this option off to hinder
1483 such exploits. However, in that case, if a binary or library
1484 relying on those helpers is run, it will not function correctly.
1486 Say N here only if you are absolutely certain that you do not
1487 need these helpers; otherwise, the safe option is to say Y.
1490 bool "Enable vDSO for 32-bit applications"
1491 depends on !CPU_BIG_ENDIAN
1492 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1493 select GENERIC_COMPAT_VDSO
1496 Place in the process address space of 32-bit applications an
1497 ELF shared object providing fast implementations of gettimeofday
1500 You must have a 32-bit build of glibc 2.22 or later for programs
1501 to seamlessly take advantage of this.
1503 config THUMB2_COMPAT_VDSO
1504 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1505 depends on COMPAT_VDSO
1508 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1509 otherwise with '-marm'.
1511 menuconfig ARMV8_DEPRECATED
1512 bool "Emulate deprecated/obsolete ARMv8 instructions"
1515 Legacy software support may require certain instructions
1516 that have been deprecated or obsoleted in the architecture.
1518 Enable this config to enable selective emulation of these
1525 config SWP_EMULATION
1526 bool "Emulate SWP/SWPB instructions"
1528 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1529 they are always undefined. Say Y here to enable software
1530 emulation of these instructions for userspace using LDXR/STXR.
1531 This feature can be controlled at runtime with the abi.swp
1532 sysctl which is disabled by default.
1534 In some older versions of glibc [<=2.8] SWP is used during futex
1535 trylock() operations with the assumption that the code will not
1536 be preempted. This invalid assumption may be more likely to fail
1537 with SWP emulation enabled, leading to deadlock of the user
1540 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1541 on an external transaction monitoring block called a global
1542 monitor to maintain update atomicity. If your system does not
1543 implement a global monitor, this option can cause programs that
1544 perform SWP operations to uncached memory to deadlock.
1548 config CP15_BARRIER_EMULATION
1549 bool "Emulate CP15 Barrier instructions"
1551 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1552 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1553 strongly recommended to use the ISB, DSB, and DMB
1554 instructions instead.
1556 Say Y here to enable software emulation of these
1557 instructions for AArch32 userspace code. When this option is
1558 enabled, CP15 barrier usage is traced which can help
1559 identify software that needs updating. This feature can be
1560 controlled at runtime with the abi.cp15_barrier sysctl.
1564 config SETEND_EMULATION
1565 bool "Emulate SETEND instruction"
1567 The SETEND instruction alters the data-endianness of the
1568 AArch32 EL0, and is deprecated in ARMv8.
1570 Say Y here to enable software emulation of the instruction
1571 for AArch32 userspace code. This feature can be controlled
1572 at runtime with the abi.setend sysctl.
1574 Note: All the cpus on the system must have mixed endian support at EL0
1575 for this feature to be enabled. If a new CPU - which doesn't support mixed
1576 endian - is hotplugged in after this feature has been enabled, there could
1577 be unexpected results in the applications.
1580 endif # ARMV8_DEPRECATED
1584 menu "ARMv8.1 architectural features"
1586 config ARM64_HW_AFDBM
1587 bool "Support for hardware updates of the Access and Dirty page flags"
1590 The ARMv8.1 architecture extensions introduce support for
1591 hardware updates of the access and dirty information in page
1592 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1593 capable processors, accesses to pages with PTE_AF cleared will
1594 set this bit instead of raising an access flag fault.
1595 Similarly, writes to read-only pages with the DBM bit set will
1596 clear the read-only bit (AP[2]) instead of raising a
1599 Kernels built with this configuration option enabled continue
1600 to work on pre-ARMv8.1 hardware and the performance impact is
1601 minimal. If unsure, say Y.
1604 bool "Enable support for Privileged Access Never (PAN)"
1607 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1608 prevents the kernel or hypervisor from accessing user-space (EL0)
1611 Choosing this option will cause any unprotected (not using
1612 copy_to_user et al) memory access to fail with a permission fault.
1614 The feature is detected at runtime, and will remain as a 'nop'
1615 instruction if the cpu does not implement the feature.
1618 def_bool $(as-instr,.arch_extension rcpc)
1620 config AS_HAS_LSE_ATOMICS
1621 def_bool $(as-instr,.arch_extension lse)
1623 config ARM64_LSE_ATOMICS
1625 default ARM64_USE_LSE_ATOMICS
1626 depends on AS_HAS_LSE_ATOMICS
1628 config ARM64_USE_LSE_ATOMICS
1629 bool "Atomic instructions"
1630 depends on JUMP_LABEL
1633 As part of the Large System Extensions, ARMv8.1 introduces new
1634 atomic instructions that are designed specifically to scale in
1637 Say Y here to make use of these instructions for the in-kernel
1638 atomic routines. This incurs a small overhead on CPUs that do
1639 not support these instructions and requires the kernel to be
1640 built with binutils >= 2.25 in order for the new instructions
1643 endmenu # "ARMv8.1 architectural features"
1645 menu "ARMv8.2 architectural features"
1647 config AS_HAS_ARMV8_2
1648 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1651 def_bool $(as-instr,.arch armv8.2-a+sha3)
1654 bool "Enable support for persistent memory"
1655 select ARCH_HAS_PMEM_API
1656 select ARCH_HAS_UACCESS_FLUSHCACHE
1658 Say Y to enable support for the persistent memory API based on the
1659 ARMv8.2 DCPoP feature.
1661 The feature is detected at runtime, and the kernel will use DC CVAC
1662 operations if DC CVAP is not supported (following the behaviour of
1663 DC CVAP itself if the system does not define a point of persistence).
1665 config ARM64_RAS_EXTN
1666 bool "Enable support for RAS CPU Extensions"
1669 CPUs that support the Reliability, Availability and Serviceability
1670 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1671 errors, classify them and report them to software.
1673 On CPUs with these extensions system software can use additional
1674 barriers to determine if faults are pending and read the
1675 classification from a new set of registers.
1677 Selecting this feature will allow the kernel to use these barriers
1678 and access the new registers if the system supports the extension.
1679 Platform RAS features may additionally depend on firmware support.
1682 bool "Enable support for Common Not Private (CNP) translations"
1684 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1686 Common Not Private (CNP) allows translation table entries to
1687 be shared between different PEs in the same inner shareable
1688 domain, so the hardware can use this fact to optimise the
1689 caching of such entries in the TLB.
1691 Selecting this option allows the CNP feature to be detected
1692 at runtime, and does not affect PEs that do not implement
1695 endmenu # "ARMv8.2 architectural features"
1697 menu "ARMv8.3 architectural features"
1699 config ARM64_PTR_AUTH
1700 bool "Enable support for pointer authentication"
1703 Pointer authentication (part of the ARMv8.3 Extensions) provides
1704 instructions for signing and authenticating pointers against secret
1705 keys, which can be used to mitigate Return Oriented Programming (ROP)
1708 This option enables these instructions at EL0 (i.e. for userspace).
1709 Choosing this option will cause the kernel to initialise secret keys
1710 for each process at exec() time, with these keys being
1711 context-switched along with the process.
1713 The feature is detected at runtime. If the feature is not present in
1714 hardware it will not be advertised to userspace/KVM guest nor will it
1717 If the feature is present on the boot CPU but not on a late CPU, then
1718 the late CPU will be parked. Also, if the boot CPU does not have
1719 address auth and the late CPU has then the late CPU will still boot
1720 but with the feature disabled. On such a system, this option should
1723 config ARM64_PTR_AUTH_KERNEL
1724 bool "Use pointer authentication for kernel"
1726 depends on ARM64_PTR_AUTH
1727 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1728 # Modern compilers insert a .note.gnu.property section note for PAC
1729 # which is only understood by binutils starting with version 2.33.1.
1730 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1731 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1732 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1734 If the compiler supports the -mbranch-protection or
1735 -msign-return-address flag (e.g. GCC 7 or later), then this option
1736 will cause the kernel itself to be compiled with return address
1737 protection. In this case, and if the target hardware is known to
1738 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1739 disabled with minimal loss of protection.
1741 This feature works with FUNCTION_GRAPH_TRACER option only if
1742 DYNAMIC_FTRACE_WITH_REGS is enabled.
1744 config CC_HAS_BRANCH_PROT_PAC_RET
1745 # GCC 9 or later, clang 8 or later
1746 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1748 config CC_HAS_SIGN_RETURN_ADDRESS
1750 def_bool $(cc-option,-msign-return-address=all)
1753 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1755 config AS_HAS_CFI_NEGATE_RA_STATE
1756 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1758 endmenu # "ARMv8.3 architectural features"
1760 menu "ARMv8.4 architectural features"
1762 config ARM64_AMU_EXTN
1763 bool "Enable support for the Activity Monitors Unit CPU extension"
1766 The activity monitors extension is an optional extension introduced
1767 by the ARMv8.4 CPU architecture. This enables support for version 1
1768 of the activity monitors architecture, AMUv1.
1770 To enable the use of this extension on CPUs that implement it, say Y.
1772 Note that for architectural reasons, firmware _must_ implement AMU
1773 support when running on CPUs that present the activity monitors
1774 extension. The required support is present in:
1775 * Version 1.5 and later of the ARM Trusted Firmware
1777 For kernels that have this configuration enabled but boot with broken
1778 firmware, you may need to say N here until the firmware is fixed.
1779 Otherwise you may experience firmware panics or lockups when
1780 accessing the counter registers. Even if you are not observing these
1781 symptoms, the values returned by the register reads might not
1782 correctly reflect reality. Most commonly, the value read will be 0,
1783 indicating that the counter is not enabled.
1785 config AS_HAS_ARMV8_4
1786 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1788 config ARM64_TLB_RANGE
1789 bool "Enable support for tlbi range feature"
1791 depends on AS_HAS_ARMV8_4
1793 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1794 range of input addresses.
1796 The feature introduces new assembly instructions, and they were
1797 support when binutils >= 2.30.
1799 endmenu # "ARMv8.4 architectural features"
1801 menu "ARMv8.5 architectural features"
1803 config AS_HAS_ARMV8_5
1804 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1807 bool "Branch Target Identification support"
1810 Branch Target Identification (part of the ARMv8.5 Extensions)
1811 provides a mechanism to limit the set of locations to which computed
1812 branch instructions such as BR or BLR can jump.
1814 To make use of BTI on CPUs that support it, say Y.
1816 BTI is intended to provide complementary protection to other control
1817 flow integrity protection mechanisms, such as the Pointer
1818 authentication mechanism provided as part of the ARMv8.3 Extensions.
1819 For this reason, it does not make sense to enable this option without
1820 also enabling support for pointer authentication. Thus, when
1821 enabling this option you should also select ARM64_PTR_AUTH=y.
1823 Userspace binaries must also be specifically compiled to make use of
1824 this mechanism. If you say N here or the hardware does not support
1825 BTI, such binaries can still run, but you get no additional
1826 enforcement of branch destinations.
1828 config ARM64_BTI_KERNEL
1829 bool "Use Branch Target Identification for kernel"
1831 depends on ARM64_BTI
1832 depends on ARM64_PTR_AUTH_KERNEL
1833 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1834 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1835 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1836 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1837 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1838 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1840 Build the kernel with Branch Target Identification annotations
1841 and enable enforcement of this for kernel code. When this option
1842 is enabled and the system supports BTI all kernel code including
1843 modular code must have BTI enabled.
1845 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1846 # GCC 9 or later, clang 8 or later
1847 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1850 bool "Enable support for E0PD"
1853 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1854 that EL0 accesses made via TTBR1 always fault in constant time,
1855 providing similar benefits to KASLR as those provided by KPTI, but
1856 with lower overhead and without disrupting legitimate access to
1857 kernel memory such as SPE.
1859 This option enables E0PD for TTBR1 where available.
1862 bool "Enable support for random number generation"
1865 Random number generation (part of the ARMv8.5 Extensions)
1866 provides a high bandwidth, cryptographically secure
1867 hardware random number generator.
1869 config ARM64_AS_HAS_MTE
1870 # Initial support for MTE went in binutils 2.32.0, checked with
1871 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1872 # as a late addition to the final architecture spec (LDGM/STGM)
1873 # is only supported in the newer 2.32.x and 2.33 binutils
1874 # versions, hence the extra "stgm" instruction check below.
1875 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1878 bool "Memory Tagging Extension support"
1880 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1881 depends on AS_HAS_ARMV8_5
1882 depends on AS_HAS_LSE_ATOMICS
1883 # Required for tag checking in the uaccess routines
1884 depends on ARM64_PAN
1885 select ARCH_HAS_SUBPAGE_FAULTS
1886 select ARCH_USES_HIGH_VMA_FLAGS
1888 Memory Tagging (part of the ARMv8.5 Extensions) provides
1889 architectural support for run-time, always-on detection of
1890 various classes of memory error to aid with software debugging
1891 to eliminate vulnerabilities arising from memory-unsafe
1894 This option enables the support for the Memory Tagging
1895 Extension at EL0 (i.e. for userspace).
1897 Selecting this option allows the feature to be detected at
1898 runtime. Any secondary CPU not implementing this feature will
1899 not be allowed a late bring-up.
1901 Userspace binaries that want to use this feature must
1902 explicitly opt in. The mechanism for the userspace is
1905 Documentation/arm64/memory-tagging-extension.rst.
1907 endmenu # "ARMv8.5 architectural features"
1909 menu "ARMv8.7 architectural features"
1912 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1914 depends on ARM64_PAN
1916 Enhanced Privileged Access Never (EPAN) allows Privileged
1917 Access Never to be used with Execute-only mappings.
1919 The feature is detected at runtime, and will remain disabled
1920 if the cpu does not implement the feature.
1921 endmenu # "ARMv8.7 architectural features"
1924 bool "ARM Scalable Vector Extension support"
1927 The Scalable Vector Extension (SVE) is an extension to the AArch64
1928 execution state which complements and extends the SIMD functionality
1929 of the base architecture to support much larger vectors and to enable
1930 additional vectorisation opportunities.
1932 To enable use of this extension on CPUs that implement it, say Y.
1934 On CPUs that support the SVE2 extensions, this option will enable
1937 Note that for architectural reasons, firmware _must_ implement SVE
1938 support when running on SVE capable hardware. The required support
1941 * version 1.5 and later of the ARM Trusted Firmware
1942 * the AArch64 boot wrapper since commit 5e1261e08abf
1943 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1945 For other firmware implementations, consult the firmware documentation
1948 If you need the kernel to boot on SVE-capable hardware with broken
1949 firmware, you may need to say N here until you get your firmware
1950 fixed. Otherwise, you may experience firmware panics or lockups when
1951 booting the kernel. If unsure and you are not observing these
1952 symptoms, you should assume that it is safe to say Y.
1955 bool "ARM Scalable Matrix Extension support"
1957 depends on ARM64_SVE
1959 The Scalable Matrix Extension (SME) is an extension to the AArch64
1960 execution state which utilises a substantial subset of the SVE
1961 instruction set, together with the addition of new architectural
1962 register state capable of holding two dimensional matrix tiles to
1963 enable various matrix operations.
1965 config ARM64_MODULE_PLTS
1966 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1968 select HAVE_MOD_ARCH_SPECIFIC
1970 Allocate PLTs when loading modules so that jumps and calls whose
1971 targets are too far away for their relative offsets to be encoded
1972 in the instructions themselves can be bounced via veneers in the
1973 module's PLT. This allows modules to be allocated in the generic
1974 vmalloc area after the dedicated module memory area has been
1977 When running with address space randomization (KASLR), the module
1978 region itself may be too far away for ordinary relative jumps and
1979 calls, and so in that case, module PLTs are required and cannot be
1982 Specific errata workaround(s) might also force module PLTs to be
1983 enabled (ARM64_ERRATUM_843419).
1985 config ARM64_PSEUDO_NMI
1986 bool "Support for NMI-like interrupts"
1989 Adds support for mimicking Non-Maskable Interrupts through the use of
1990 GIC interrupt priority. This support requires version 3 or later of
1993 This high priority configuration for interrupts needs to be
1994 explicitly enabled by setting the kernel parameter
1995 "irqchip.gicv3_pseudo_nmi" to 1.
2000 config ARM64_DEBUG_PRIORITY_MASKING
2001 bool "Debug interrupt priority masking"
2003 This adds runtime checks to functions enabling/disabling
2004 interrupts when using priority masking. The additional checks verify
2005 the validity of ICC_PMR_EL1 when calling concerned functions.
2008 endif # ARM64_PSEUDO_NMI
2011 bool "Build a relocatable kernel image" if EXPERT
2012 select ARCH_HAS_RELR
2015 This builds the kernel as a Position Independent Executable (PIE),
2016 which retains all relocation metadata required to relocate the
2017 kernel binary at runtime to a different virtual address than the
2018 address it was linked at.
2019 Since AArch64 uses the RELA relocation format, this requires a
2020 relocation pass at runtime even if the kernel is loaded at the
2021 same address it was linked at.
2023 config RANDOMIZE_BASE
2024 bool "Randomize the address of the kernel image"
2025 select ARM64_MODULE_PLTS if MODULES
2028 Randomizes the virtual address at which the kernel image is
2029 loaded, as a security feature that deters exploit attempts
2030 relying on knowledge of the location of kernel internals.
2032 It is the bootloader's job to provide entropy, by passing a
2033 random u64 value in /chosen/kaslr-seed at kernel entry.
2035 When booting via the UEFI stub, it will invoke the firmware's
2036 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2037 to the kernel proper. In addition, it will randomise the physical
2038 location of the kernel Image as well.
2042 config RANDOMIZE_MODULE_REGION_FULL
2043 bool "Randomize the module region over a 2 GB range"
2044 depends on RANDOMIZE_BASE
2047 Randomizes the location of the module region inside a 2 GB window
2048 covering the core kernel. This way, it is less likely for modules
2049 to leak information about the location of core kernel data structures
2050 but it does imply that function calls between modules and the core
2051 kernel will need to be resolved via veneers in the module PLT.
2053 When this option is not set, the module region will be randomized over
2054 a limited range that contains the [_stext, _etext] interval of the
2055 core kernel, so branch relocations are almost always in range unless
2056 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2057 particular case of region exhaustion, modules might be able to fall
2058 back to a larger 2GB area.
2060 config CC_HAVE_STACKPROTECTOR_SYSREG
2061 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2063 config STACKPROTECTOR_PER_TASK
2065 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2067 # The GPIO number here must be sorted by descending number. In case of
2068 # a multiplatform kernel, we just want the highest value required by the
2069 # selected platforms.
2072 default 2048 if ARCH_APPLE
2075 Maximum number of GPIOs in the system.
2077 If unsure, leave the default value.
2079 endmenu # "Kernel Features"
2083 config ARM64_ACPI_PARKING_PROTOCOL
2084 bool "Enable support for the ARM64 ACPI parking protocol"
2087 Enable support for the ARM64 ACPI parking protocol. If disabled
2088 the kernel will not allow booting through the ARM64 ACPI parking
2089 protocol even if the corresponding data is present in the ACPI
2093 string "Default kernel command string"
2096 Provide a set of default command-line options at build time by
2097 entering them here. As a minimum, you should specify the the
2098 root device (e.g. root=/dev/nfs).
2101 prompt "Kernel command line type" if CMDLINE != ""
2102 default CMDLINE_FROM_BOOTLOADER
2104 Choose how the kernel will handle the provided default kernel
2105 command line string.
2107 config CMDLINE_FROM_BOOTLOADER
2108 bool "Use bootloader kernel arguments if available"
2110 Uses the command-line options passed by the boot loader. If
2111 the boot loader doesn't provide any, the default kernel command
2112 string provided in CMDLINE will be used.
2114 config CMDLINE_FORCE
2115 bool "Always use the default kernel command string"
2117 Always use the default kernel command string, even if the boot
2118 loader passes other arguments to the kernel.
2119 This is useful if you cannot or don't want to change the
2120 command-line options your boot loader passes to the kernel.
2128 bool "UEFI runtime support"
2129 depends on OF && !CPU_BIG_ENDIAN
2130 depends on KERNEL_MODE_NEON
2131 select ARCH_SUPPORTS_ACPI
2134 select EFI_PARAMS_FROM_FDT
2135 select EFI_RUNTIME_WRAPPERS
2137 select EFI_GENERIC_STUB
2138 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2141 This option provides support for runtime services provided
2142 by UEFI firmware (such as non-volatile variables, realtime
2143 clock, and platform reset). A UEFI stub is also provided to
2144 allow the kernel to be booted as an EFI application. This
2145 is only useful on systems that have UEFI firmware.
2148 bool "Enable support for SMBIOS (DMI) tables"
2152 This enables SMBIOS/DMI feature for systems.
2154 This option is only useful on systems that have UEFI firmware.
2155 However, even with this option, the resultant kernel should
2156 continue to boot on existing non-UEFI platforms.
2158 endmenu # "Boot options"
2160 menu "Power management options"
2162 source "kernel/power/Kconfig"
2164 config ARCH_HIBERNATION_POSSIBLE
2168 config ARCH_HIBERNATION_HEADER
2170 depends on HIBERNATION
2172 config ARCH_SUSPEND_POSSIBLE
2175 endmenu # "Power management options"
2177 menu "CPU Power Management"
2179 source "drivers/cpuidle/Kconfig"
2181 source "drivers/cpufreq/Kconfig"
2183 endmenu # "CPU Power Management"
2185 source "drivers/acpi/Kconfig"
2187 source "arch/arm64/kvm/Kconfig"
2190 source "arch/arm64/crypto/Kconfig"