2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
33 #include <mach/irqs.h>
35 #include <mach/regs-gpio.h>
36 #include <mach/gpio-samsung.h>
39 #include <plat/gpio-core.h>
40 #include <plat/gpio-cfg.h>
41 #include <plat/gpio-cfg-helpers.h>
44 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
45 unsigned int off, samsung_gpio_pull_t pull)
47 void __iomem *reg = chip->base + 0x08;
51 pup = __raw_readl(reg);
54 __raw_writel(pup, reg);
59 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
62 void __iomem *reg = chip->base + 0x08;
64 u32 pup = __raw_readl(reg);
69 return (__force samsung_gpio_pull_t)pup;
72 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
73 unsigned int off, samsung_gpio_pull_t pull)
76 case S3C_GPIO_PULL_NONE:
79 case S3C_GPIO_PULL_UP:
82 case S3C_GPIO_PULL_DOWN:
86 return samsung_gpio_setpull_updown(chip, off, pull);
89 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
92 samsung_gpio_pull_t pull;
94 pull = samsung_gpio_getpull_updown(chip, off);
98 pull = S3C_GPIO_PULL_UP;
102 pull = S3C_GPIO_PULL_NONE;
105 pull = S3C_GPIO_PULL_DOWN;
112 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
113 unsigned int off, samsung_gpio_pull_t pull,
114 samsung_gpio_pull_t updown)
116 void __iomem *reg = chip->base + 0x08;
117 u32 pup = __raw_readl(reg);
121 else if (pull == S3C_GPIO_PULL_NONE)
126 __raw_writel(pup, reg);
130 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
132 samsung_gpio_pull_t updown)
134 void __iomem *reg = chip->base + 0x08;
135 u32 pup = __raw_readl(reg);
138 return pup ? S3C_GPIO_PULL_NONE : updown;
141 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
144 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
147 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
148 unsigned int off, samsung_gpio_pull_t pull)
150 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
153 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
156 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
159 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
160 unsigned int off, samsung_gpio_pull_t pull)
162 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
166 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
167 * @chip: The gpio chip that is being configured.
168 * @off: The offset for the GPIO being configured.
169 * @cfg: The configuration value to set.
171 * This helper deal with the GPIO cases where the control register
172 * has two bits of configuration per gpio, which have the following
176 * 1x = special function
179 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
180 unsigned int off, unsigned int cfg)
182 void __iomem *reg = chip->base;
183 unsigned int shift = off * 2;
186 if (samsung_gpio_is_cfg_special(cfg)) {
194 con = __raw_readl(reg);
195 con &= ~(0x3 << shift);
197 __raw_writel(con, reg);
203 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
204 * @chip: The gpio chip that is being configured.
205 * @off: The offset for the GPIO being configured.
207 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
208 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
209 * S3C_GPIO_SPECIAL() macro.
212 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
217 con = __raw_readl(chip->base);
221 /* this conversion works for IN and OUT as well as special mode */
222 return S3C_GPIO_SPECIAL(con);
226 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
227 * @chip: The gpio chip that is being configured.
228 * @off: The offset for the GPIO being configured.
229 * @cfg: The configuration value to set.
231 * This helper deal with the GPIO cases where the control register has 4 bits
232 * of control per GPIO, generally in the form of:
235 * others = Special functions (dependent on bank)
237 * Note, since the code to deal with the case where there are two control
238 * registers instead of one, we do not have a separate set of functions for
242 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
243 unsigned int off, unsigned int cfg)
245 void __iomem *reg = chip->base;
246 unsigned int shift = (off & 7) * 4;
249 if (off < 8 && chip->chip.ngpio > 8)
252 if (samsung_gpio_is_cfg_special(cfg)) {
257 con = __raw_readl(reg);
258 con &= ~(0xf << shift);
260 __raw_writel(con, reg);
266 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
267 * @chip: The gpio chip that is being configured.
268 * @off: The offset for the GPIO being configured.
270 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
271 * register setting into a value the software can use, such as could be passed
272 * to samsung_gpio_setcfg_4bit().
274 * @sa samsung_gpio_getcfg_2bit
277 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
280 void __iomem *reg = chip->base;
281 unsigned int shift = (off & 7) * 4;
284 if (off < 8 && chip->chip.ngpio > 8)
287 con = __raw_readl(reg);
291 /* this conversion works for IN and OUT as well as special mode */
292 return S3C_GPIO_SPECIAL(con);
295 #ifdef CONFIG_PLAT_S3C24XX
297 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
298 * @chip: The gpio chip that is being configured.
299 * @off: The offset for the GPIO being configured.
300 * @cfg: The configuration value to set.
302 * This helper deal with the GPIO cases where the control register
303 * has one bit of configuration for the gpio, where setting the bit
304 * means the pin is in special function mode and unset means output.
307 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
308 unsigned int off, unsigned int cfg)
310 void __iomem *reg = chip->base;
311 unsigned int shift = off;
314 if (samsung_gpio_is_cfg_special(cfg)) {
317 /* Map output to 0, and SFN2 to 1 */
325 con = __raw_readl(reg);
326 con &= ~(0x1 << shift);
328 __raw_writel(con, reg);
334 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
335 * @chip: The gpio chip that is being configured.
336 * @off: The offset for the GPIO being configured.
338 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
339 * GPIO configuration value.
341 * @sa samsung_gpio_getcfg_2bit
342 * @sa samsung_gpio_getcfg_4bit
345 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
350 con = __raw_readl(chip->base);
355 return S3C_GPIO_SFN(con);
359 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
362 for (; nr_chips > 0; nr_chips--, chipcfg++) {
363 if (!chipcfg->set_config)
364 chipcfg->set_config = samsung_gpio_setcfg_4bit;
365 if (!chipcfg->get_config)
366 chipcfg->get_config = samsung_gpio_getcfg_4bit;
367 if (!chipcfg->set_pull)
368 chipcfg->set_pull = samsung_gpio_setpull_updown;
369 if (!chipcfg->get_pull)
370 chipcfg->get_pull = samsung_gpio_getpull_updown;
374 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
375 .set_config = samsung_gpio_setcfg_2bit,
376 .get_config = samsung_gpio_getcfg_2bit,
379 #ifdef CONFIG_PLAT_S3C24XX
380 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
381 .set_config = s3c24xx_gpio_setcfg_abank,
382 .get_config = s3c24xx_gpio_getcfg_abank,
386 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
401 .set_config = samsung_gpio_setcfg_2bit,
402 .get_config = samsung_gpio_getcfg_2bit,
406 .set_config = samsung_gpio_setcfg_2bit,
407 .get_config = samsung_gpio_getcfg_2bit,
411 .set_config = samsung_gpio_setcfg_2bit,
412 .get_config = samsung_gpio_getcfg_2bit,
415 .set_config = samsung_gpio_setcfg_2bit,
416 .get_config = samsung_gpio_getcfg_2bit,
421 * Default routines for controlling GPIO, based on the original S3C24XX
422 * GPIO functions which deal with the case where each gpio bank of the
423 * chip is as following:
425 * base + 0x00: Control register, 2 bits per gpio
426 * gpio n: 2 bits starting at (2*n)
427 * 00 = input, 01 = output, others mean special-function
428 * base + 0x04: Data register, 1 bit per gpio
432 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
434 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
435 void __iomem *base = ourchip->base;
439 samsung_gpio_lock(ourchip, flags);
441 con = __raw_readl(base + 0x00);
442 con &= ~(3 << (offset * 2));
444 __raw_writel(con, base + 0x00);
446 samsung_gpio_unlock(ourchip, flags);
450 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
451 unsigned offset, int value)
453 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
454 void __iomem *base = ourchip->base;
459 samsung_gpio_lock(ourchip, flags);
461 dat = __raw_readl(base + 0x04);
462 dat &= ~(1 << offset);
465 __raw_writel(dat, base + 0x04);
467 con = __raw_readl(base + 0x00);
468 con &= ~(3 << (offset * 2));
469 con |= 1 << (offset * 2);
471 __raw_writel(con, base + 0x00);
472 __raw_writel(dat, base + 0x04);
474 samsung_gpio_unlock(ourchip, flags);
479 * The samsung_gpiolib_4bit routines are to control the gpio banks where
480 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
483 * base + 0x00: Control register, 4 bits per gpio
484 * gpio n: 4 bits starting at (4*n)
485 * 0000 = input, 0001 = output, others mean special-function
486 * base + 0x04: Data register, 1 bit per gpio
489 * Note, since the data register is one bit per gpio and is at base + 0x4
490 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
491 * state of the output.
494 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
497 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
498 void __iomem *base = ourchip->base;
501 con = __raw_readl(base + GPIOCON_OFF);
502 if (ourchip->bitmap_gpio_int & BIT(offset))
503 con |= 0xf << con_4bit_shift(offset);
505 con &= ~(0xf << con_4bit_shift(offset));
506 __raw_writel(con, base + GPIOCON_OFF);
508 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
513 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
514 unsigned int offset, int value)
516 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
517 void __iomem *base = ourchip->base;
521 con = __raw_readl(base + GPIOCON_OFF);
522 con &= ~(0xf << con_4bit_shift(offset));
523 con |= 0x1 << con_4bit_shift(offset);
525 dat = __raw_readl(base + GPIODAT_OFF);
530 dat &= ~(1 << offset);
532 __raw_writel(dat, base + GPIODAT_OFF);
533 __raw_writel(con, base + GPIOCON_OFF);
534 __raw_writel(dat, base + GPIODAT_OFF);
536 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
542 * The next set of routines are for the case where the GPIO configuration
543 * registers are 4 bits per GPIO but there is more than one register (the
544 * bank has more than 8 GPIOs.
546 * This case is the similar to the 4 bit case, but the registers are as
549 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
550 * gpio n: 4 bits starting at (4*n)
551 * 0000 = input, 0001 = output, others mean special-function
552 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
553 * gpio n: 4 bits starting at (4*n)
554 * 0000 = input, 0001 = output, others mean special-function
555 * base + 0x08: Data register, 1 bit per gpio
558 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
559 * routines we store the 'base + 0x4' address so that these routines see
560 * the data register at ourchip->base + 0x04.
563 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
566 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
567 void __iomem *base = ourchip->base;
568 void __iomem *regcon = base;
576 con = __raw_readl(regcon);
577 con &= ~(0xf << con_4bit_shift(offset));
578 __raw_writel(con, regcon);
580 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
585 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
586 unsigned int offset, int value)
588 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
589 void __iomem *base = ourchip->base;
590 void __iomem *regcon = base;
593 unsigned con_offset = offset;
600 con = __raw_readl(regcon);
601 con &= ~(0xf << con_4bit_shift(con_offset));
602 con |= 0x1 << con_4bit_shift(con_offset);
604 dat = __raw_readl(base + GPIODAT_OFF);
609 dat &= ~(1 << offset);
611 __raw_writel(dat, base + GPIODAT_OFF);
612 __raw_writel(con, regcon);
613 __raw_writel(dat, base + GPIODAT_OFF);
615 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
620 #ifdef CONFIG_PLAT_S3C24XX
621 /* The next set of routines are for the case of s3c24xx bank a */
623 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
628 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
629 unsigned offset, int value)
631 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
632 void __iomem *base = ourchip->base;
637 local_irq_save(flags);
639 con = __raw_readl(base + 0x00);
640 dat = __raw_readl(base + 0x04);
642 dat &= ~(1 << offset);
646 __raw_writel(dat, base + 0x04);
648 con &= ~(1 << offset);
650 __raw_writel(con, base + 0x00);
651 __raw_writel(dat, base + 0x04);
653 local_irq_restore(flags);
658 static void samsung_gpiolib_set(struct gpio_chip *chip,
659 unsigned offset, int value)
661 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
662 void __iomem *base = ourchip->base;
666 samsung_gpio_lock(ourchip, flags);
668 dat = __raw_readl(base + 0x04);
669 dat &= ~(1 << offset);
672 __raw_writel(dat, base + 0x04);
674 samsung_gpio_unlock(ourchip, flags);
677 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
679 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
682 val = __raw_readl(ourchip->base + 0x04);
690 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
691 * for use with the configuration calls, and other parts of the s3c gpiolib
694 * Not all s3c support code will need this, as some configurations of cpu
695 * may only support one or two different configuration options and have an
696 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
697 * the machine support file should provide its own samsung_gpiolib_getchip()
698 * and any other necessary functions.
701 #ifdef CONFIG_S3C_GPIO_TRACK
702 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
704 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
709 gpn = chip->chip.base;
710 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
711 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
712 s3c_gpios[gpn] = chip;
715 #endif /* CONFIG_S3C_GPIO_TRACK */
718 * samsung_gpiolib_add() - add the Samsung gpio_chip.
719 * @chip: The chip to register
721 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
722 * information and makes the necessary alterations for the platform and
723 * notes the information for use with the configuration systems and any
724 * other parts of the system.
727 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
729 struct gpio_chip *gc = &chip->chip;
736 spin_lock_init(&chip->lock);
738 if (!gc->direction_input)
739 gc->direction_input = samsung_gpiolib_2bit_input;
740 if (!gc->direction_output)
741 gc->direction_output = samsung_gpiolib_2bit_output;
743 gc->set = samsung_gpiolib_set;
745 gc->get = samsung_gpiolib_get;
748 if (chip->pm != NULL) {
749 if (!chip->pm->save || !chip->pm->resume)
750 pr_err("gpio: %s has missing PM functions\n",
753 pr_err("gpio: %s has no PM function\n", gc->label);
756 /* gpiochip_add() prints own failure message on error. */
757 ret = gpiochip_add_data(gc, chip);
759 s3c_gpiolib_track(chip);
762 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
763 int nr_chips, void __iomem *base)
766 struct gpio_chip *gc = &chip->chip;
768 for (i = 0 ; i < nr_chips; i++, chip++) {
769 /* skip banks not present on SoC */
770 if (chip->chip.base >= S3C_GPIO_END)
774 chip->config = &s3c24xx_gpiocfg_default;
776 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
777 if ((base != NULL) && (chip->base == NULL))
778 chip->base = base + ((i) * 0x10);
780 if (!gc->direction_input)
781 gc->direction_input = samsung_gpiolib_2bit_input;
782 if (!gc->direction_output)
783 gc->direction_output = samsung_gpiolib_2bit_output;
785 samsung_gpiolib_add(chip);
789 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
790 int nr_chips, void __iomem *base,
795 for (i = 0 ; i < nr_chips; i++, chip++) {
796 chip->chip.direction_input = samsung_gpiolib_2bit_input;
797 chip->chip.direction_output = samsung_gpiolib_2bit_output;
800 chip->config = &samsung_gpio_cfgs[7];
802 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
803 if ((base != NULL) && (chip->base == NULL))
804 chip->base = base + ((i) * offset);
806 samsung_gpiolib_add(chip);
811 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
812 * @chip: The gpio chip that is being configured.
813 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
815 * This helper deal with the GPIO cases where the control register has 4 bits
816 * of control per GPIO, generally in the form of:
819 * others = Special functions (dependent on bank)
821 * Note, since the code to deal with the case where there are two control
822 * registers instead of one, we do not have a separate set of function
823 * (samsung_gpiolib_add_4bit2_chips)for each case.
826 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
827 int nr_chips, void __iomem *base)
831 for (i = 0 ; i < nr_chips; i++, chip++) {
832 chip->chip.direction_input = samsung_gpiolib_4bit_input;
833 chip->chip.direction_output = samsung_gpiolib_4bit_output;
836 chip->config = &samsung_gpio_cfgs[2];
838 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
839 if ((base != NULL) && (chip->base == NULL))
840 chip->base = base + ((i) * 0x20);
842 chip->bitmap_gpio_int = 0;
844 samsung_gpiolib_add(chip);
848 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
851 for (; nr_chips > 0; nr_chips--, chip++) {
852 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
853 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
856 chip->config = &samsung_gpio_cfgs[2];
858 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
860 samsung_gpiolib_add(chip);
864 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
866 struct samsung_gpio_chip *samsung_chip = gpiochip_get_data(chip);
868 return samsung_chip->irq_base + offset;
871 #ifdef CONFIG_PLAT_S3C24XX
872 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
875 if (soc_is_s3c2412())
876 return IRQ_EINT0_2412 + offset;
878 return IRQ_EINT0 + offset;
882 return IRQ_EINT4 + offset - 4;
888 #ifdef CONFIG_ARCH_S3C64XX
889 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
891 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
894 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
896 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
900 struct samsung_gpio_chip s3c24xx_gpios[] = {
901 #ifdef CONFIG_PLAT_S3C24XX
903 .config = &s3c24xx_gpiocfg_banka,
905 .base = S3C2410_GPA(0),
906 .owner = THIS_MODULE,
909 .direction_input = s3c24xx_gpiolib_banka_input,
910 .direction_output = s3c24xx_gpiolib_banka_output,
914 .base = S3C2410_GPB(0),
915 .owner = THIS_MODULE,
921 .base = S3C2410_GPC(0),
922 .owner = THIS_MODULE,
928 .base = S3C2410_GPD(0),
929 .owner = THIS_MODULE,
935 .base = S3C2410_GPE(0),
937 .owner = THIS_MODULE,
942 .base = S3C2410_GPF(0),
943 .owner = THIS_MODULE,
946 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
949 .irq_base = IRQ_EINT8,
951 .base = S3C2410_GPG(0),
952 .owner = THIS_MODULE,
955 .to_irq = samsung_gpiolib_to_irq,
959 .base = S3C2410_GPH(0),
960 .owner = THIS_MODULE,
965 /* GPIOS for the S3C2443 and later devices. */
967 .base = S3C2440_GPJCON,
969 .base = S3C2410_GPJ(0),
970 .owner = THIS_MODULE,
975 .base = S3C2443_GPKCON,
977 .base = S3C2410_GPK(0),
978 .owner = THIS_MODULE,
983 .base = S3C2443_GPLCON,
985 .base = S3C2410_GPL(0),
986 .owner = THIS_MODULE,
991 .base = S3C2443_GPMCON,
993 .base = S3C2410_GPM(0),
994 .owner = THIS_MODULE,
1003 * GPIO bank summary:
1005 * Bank GPIOs Style SlpCon ExtInt Group
1011 * F 16 2Bit Yes 4 [1]
1013 * H 10 4Bit[2] Yes 6
1014 * I 16 2Bit Yes None
1015 * J 12 2Bit Yes None
1016 * K 16 4Bit[2] No None
1017 * L 15 4Bit[2] No None
1018 * M 6 4Bit No IRQ_EINT
1019 * N 16 2Bit No IRQ_EINT
1024 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1025 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1028 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1029 #ifdef CONFIG_ARCH_S3C64XX
1032 .base = S3C64XX_GPA(0),
1033 .ngpio = S3C64XX_GPIO_A_NR,
1038 .base = S3C64XX_GPB(0),
1039 .ngpio = S3C64XX_GPIO_B_NR,
1044 .base = S3C64XX_GPC(0),
1045 .ngpio = S3C64XX_GPIO_C_NR,
1050 .base = S3C64XX_GPD(0),
1051 .ngpio = S3C64XX_GPIO_D_NR,
1055 .config = &samsung_gpio_cfgs[0],
1057 .base = S3C64XX_GPE(0),
1058 .ngpio = S3C64XX_GPIO_E_NR,
1062 .base = S3C64XX_GPG_BASE,
1064 .base = S3C64XX_GPG(0),
1065 .ngpio = S3C64XX_GPIO_G_NR,
1069 .base = S3C64XX_GPM_BASE,
1070 .config = &samsung_gpio_cfgs[1],
1072 .base = S3C64XX_GPM(0),
1073 .ngpio = S3C64XX_GPIO_M_NR,
1075 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1081 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1082 #ifdef CONFIG_ARCH_S3C64XX
1084 .base = S3C64XX_GPH_BASE + 0x4,
1086 .base = S3C64XX_GPH(0),
1087 .ngpio = S3C64XX_GPIO_H_NR,
1091 .base = S3C64XX_GPK_BASE + 0x4,
1092 .config = &samsung_gpio_cfgs[0],
1094 .base = S3C64XX_GPK(0),
1095 .ngpio = S3C64XX_GPIO_K_NR,
1099 .base = S3C64XX_GPL_BASE + 0x4,
1100 .config = &samsung_gpio_cfgs[1],
1102 .base = S3C64XX_GPL(0),
1103 .ngpio = S3C64XX_GPIO_L_NR,
1105 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1111 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1112 #ifdef CONFIG_ARCH_S3C64XX
1114 .base = S3C64XX_GPF_BASE,
1115 .config = &samsung_gpio_cfgs[6],
1117 .base = S3C64XX_GPF(0),
1118 .ngpio = S3C64XX_GPIO_F_NR,
1122 .config = &samsung_gpio_cfgs[7],
1124 .base = S3C64XX_GPI(0),
1125 .ngpio = S3C64XX_GPIO_I_NR,
1129 .config = &samsung_gpio_cfgs[7],
1131 .base = S3C64XX_GPJ(0),
1132 .ngpio = S3C64XX_GPIO_J_NR,
1136 .config = &samsung_gpio_cfgs[6],
1138 .base = S3C64XX_GPO(0),
1139 .ngpio = S3C64XX_GPIO_O_NR,
1143 .config = &samsung_gpio_cfgs[6],
1145 .base = S3C64XX_GPP(0),
1146 .ngpio = S3C64XX_GPIO_P_NR,
1150 .config = &samsung_gpio_cfgs[6],
1152 .base = S3C64XX_GPQ(0),
1153 .ngpio = S3C64XX_GPIO_Q_NR,
1157 .base = S3C64XX_GPN_BASE,
1158 .irq_base = IRQ_EINT(0),
1159 .config = &samsung_gpio_cfgs[5],
1161 .base = S3C64XX_GPN(0),
1162 .ngpio = S3C64XX_GPIO_N_NR,
1164 .to_irq = samsung_gpiolib_to_irq,
1170 /* TODO: cleanup soc_is_* */
1171 static __init int samsung_gpiolib_init(void)
1174 * Currently there are two drivers that can provide GPIO support for
1175 * Samsung SoCs. For device tree enabled platforms, the new
1176 * pinctrl-samsung driver is used, providing both GPIO and pin control
1177 * interfaces. For legacy (non-DT) platforms this driver is used.
1179 if (of_have_populated_dt())
1182 if (soc_is_s3c24xx()) {
1183 samsung_gpiolib_set_cfg(samsung_gpio_cfgs,
1184 ARRAY_SIZE(samsung_gpio_cfgs));
1185 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
1186 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
1187 } else if (soc_is_s3c64xx()) {
1188 samsung_gpiolib_set_cfg(samsung_gpio_cfgs,
1189 ARRAY_SIZE(samsung_gpio_cfgs));
1190 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
1191 ARRAY_SIZE(s3c64xx_gpios_2bit),
1192 S3C64XX_VA_GPIO + 0xE0, 0x20);
1193 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
1194 ARRAY_SIZE(s3c64xx_gpios_4bit),
1196 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
1197 ARRAY_SIZE(s3c64xx_gpios_4bit2));
1202 core_initcall(samsung_gpiolib_init);
1204 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
1206 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1207 unsigned long flags;
1214 offset = pin - chip->chip.base;
1216 samsung_gpio_lock(chip, flags);
1217 ret = samsung_gpio_do_setcfg(chip, offset, config);
1218 samsung_gpio_unlock(chip, flags);
1222 EXPORT_SYMBOL(s3c_gpio_cfgpin);
1224 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
1229 for (; nr > 0; nr--, start++) {
1230 ret = s3c_gpio_cfgpin(start, cfg);
1237 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
1239 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
1240 unsigned int cfg, samsung_gpio_pull_t pull)
1244 for (; nr > 0; nr--, start++) {
1245 s3c_gpio_setpull(start, pull);
1246 ret = s3c_gpio_cfgpin(start, cfg);
1253 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
1255 unsigned s3c_gpio_getcfg(unsigned int pin)
1257 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1258 unsigned long flags;
1263 offset = pin - chip->chip.base;
1265 samsung_gpio_lock(chip, flags);
1266 ret = samsung_gpio_do_getcfg(chip, offset);
1267 samsung_gpio_unlock(chip, flags);
1272 EXPORT_SYMBOL(s3c_gpio_getcfg);
1274 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
1276 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1277 unsigned long flags;
1283 offset = pin - chip->chip.base;
1285 samsung_gpio_lock(chip, flags);
1286 ret = samsung_gpio_do_setpull(chip, offset, pull);
1287 samsung_gpio_unlock(chip, flags);
1291 EXPORT_SYMBOL(s3c_gpio_setpull);
1293 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
1295 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1296 unsigned long flags;
1301 offset = pin - chip->chip.base;
1303 samsung_gpio_lock(chip, flags);
1304 pup = samsung_gpio_do_getpull(chip, offset);
1305 samsung_gpio_unlock(chip, flags);
1308 return (__force samsung_gpio_pull_t)pup;
1310 EXPORT_SYMBOL(s3c_gpio_getpull);
1312 #ifdef CONFIG_PLAT_S3C24XX
1313 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
1315 unsigned long flags;
1316 unsigned long misccr;
1318 local_irq_save(flags);
1319 misccr = __raw_readl(S3C24XX_MISCCR);
1322 __raw_writel(misccr, S3C24XX_MISCCR);
1323 local_irq_restore(flags);
1327 EXPORT_SYMBOL(s3c2410_modify_misccr);