1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 // http://www.samsung.com/
6 // Copyright 2008 Openmoko, Inc.
7 // Copyright 2008 Simtec Electronics
8 // Ben Dooks <ben@simtec.co.uk>
9 // http://armlinux.simtec.co.uk/
11 // SAMSUNG - GPIOlib support
13 #include <linux/kernel.h>
14 #include <linux/irq.h>
16 #include <linux/gpio.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
24 #include <linux/slab.h>
25 #include <linux/of_address.h>
29 #include <mach/irqs.h>
31 #include <mach/regs-gpio.h>
32 #include <mach/gpio-samsung.h>
35 #include <plat/gpio-core.h>
36 #include <plat/gpio-cfg.h>
37 #include <plat/gpio-cfg-helpers.h>
40 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
41 unsigned int off, samsung_gpio_pull_t pull)
43 void __iomem *reg = chip->base + 0x08;
47 pup = __raw_readl(reg);
50 __raw_writel(pup, reg);
55 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
58 void __iomem *reg = chip->base + 0x08;
60 u32 pup = __raw_readl(reg);
65 return (__force samsung_gpio_pull_t)pup;
68 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
69 unsigned int off, samsung_gpio_pull_t pull)
72 case S3C_GPIO_PULL_NONE:
75 case S3C_GPIO_PULL_UP:
78 case S3C_GPIO_PULL_DOWN:
82 return samsung_gpio_setpull_updown(chip, off, pull);
85 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
88 samsung_gpio_pull_t pull;
90 pull = samsung_gpio_getpull_updown(chip, off);
94 pull = S3C_GPIO_PULL_UP;
98 pull = S3C_GPIO_PULL_NONE;
101 pull = S3C_GPIO_PULL_DOWN;
108 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
109 unsigned int off, samsung_gpio_pull_t pull,
110 samsung_gpio_pull_t updown)
112 void __iomem *reg = chip->base + 0x08;
113 u32 pup = __raw_readl(reg);
117 else if (pull == S3C_GPIO_PULL_NONE)
122 __raw_writel(pup, reg);
126 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
128 samsung_gpio_pull_t updown)
130 void __iomem *reg = chip->base + 0x08;
131 u32 pup = __raw_readl(reg);
134 return pup ? S3C_GPIO_PULL_NONE : updown;
137 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
140 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
143 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
144 unsigned int off, samsung_gpio_pull_t pull)
146 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
149 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
152 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
155 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
156 unsigned int off, samsung_gpio_pull_t pull)
158 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
162 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
163 * @chip: The gpio chip that is being configured.
164 * @off: The offset for the GPIO being configured.
165 * @cfg: The configuration value to set.
167 * This helper deal with the GPIO cases where the control register
168 * has two bits of configuration per gpio, which have the following
172 * 1x = special function
175 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
176 unsigned int off, unsigned int cfg)
178 void __iomem *reg = chip->base;
179 unsigned int shift = off * 2;
182 if (samsung_gpio_is_cfg_special(cfg)) {
190 con = __raw_readl(reg);
191 con &= ~(0x3 << shift);
193 __raw_writel(con, reg);
199 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
200 * @chip: The gpio chip that is being configured.
201 * @off: The offset for the GPIO being configured.
203 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
204 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
205 * S3C_GPIO_SPECIAL() macro.
208 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
213 con = __raw_readl(chip->base);
217 /* this conversion works for IN and OUT as well as special mode */
218 return S3C_GPIO_SPECIAL(con);
222 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
223 * @chip: The gpio chip that is being configured.
224 * @off: The offset for the GPIO being configured.
225 * @cfg: The configuration value to set.
227 * This helper deal with the GPIO cases where the control register has 4 bits
228 * of control per GPIO, generally in the form of:
231 * others = Special functions (dependent on bank)
233 * Note, since the code to deal with the case where there are two control
234 * registers instead of one, we do not have a separate set of functions for
238 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
239 unsigned int off, unsigned int cfg)
241 void __iomem *reg = chip->base;
242 unsigned int shift = (off & 7) * 4;
245 if (off < 8 && chip->chip.ngpio > 8)
248 if (samsung_gpio_is_cfg_special(cfg)) {
253 con = __raw_readl(reg);
254 con &= ~(0xf << shift);
256 __raw_writel(con, reg);
262 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
263 * @chip: The gpio chip that is being configured.
264 * @off: The offset for the GPIO being configured.
266 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
267 * register setting into a value the software can use, such as could be passed
268 * to samsung_gpio_setcfg_4bit().
270 * @sa samsung_gpio_getcfg_2bit
273 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
276 void __iomem *reg = chip->base;
277 unsigned int shift = (off & 7) * 4;
280 if (off < 8 && chip->chip.ngpio > 8)
283 con = __raw_readl(reg);
287 /* this conversion works for IN and OUT as well as special mode */
288 return S3C_GPIO_SPECIAL(con);
291 #ifdef CONFIG_PLAT_S3C24XX
293 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
294 * @chip: The gpio chip that is being configured.
295 * @off: The offset for the GPIO being configured.
296 * @cfg: The configuration value to set.
298 * This helper deal with the GPIO cases where the control register
299 * has one bit of configuration for the gpio, where setting the bit
300 * means the pin is in special function mode and unset means output.
303 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
304 unsigned int off, unsigned int cfg)
306 void __iomem *reg = chip->base;
307 unsigned int shift = off;
310 if (samsung_gpio_is_cfg_special(cfg)) {
313 /* Map output to 0, and SFN2 to 1 */
321 con = __raw_readl(reg);
322 con &= ~(0x1 << shift);
324 __raw_writel(con, reg);
330 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
331 * @chip: The gpio chip that is being configured.
332 * @off: The offset for the GPIO being configured.
334 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
335 * GPIO configuration value.
337 * @sa samsung_gpio_getcfg_2bit
338 * @sa samsung_gpio_getcfg_4bit
341 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
346 con = __raw_readl(chip->base);
351 return S3C_GPIO_SFN(con);
355 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
358 for (; nr_chips > 0; nr_chips--, chipcfg++) {
359 if (!chipcfg->set_config)
360 chipcfg->set_config = samsung_gpio_setcfg_4bit;
361 if (!chipcfg->get_config)
362 chipcfg->get_config = samsung_gpio_getcfg_4bit;
363 if (!chipcfg->set_pull)
364 chipcfg->set_pull = samsung_gpio_setpull_updown;
365 if (!chipcfg->get_pull)
366 chipcfg->get_pull = samsung_gpio_getpull_updown;
370 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
371 .set_config = samsung_gpio_setcfg_2bit,
372 .get_config = samsung_gpio_getcfg_2bit,
375 #ifdef CONFIG_PLAT_S3C24XX
376 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
377 .set_config = s3c24xx_gpio_setcfg_abank,
378 .get_config = s3c24xx_gpio_getcfg_abank,
382 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
397 .set_config = samsung_gpio_setcfg_2bit,
398 .get_config = samsung_gpio_getcfg_2bit,
402 .set_config = samsung_gpio_setcfg_2bit,
403 .get_config = samsung_gpio_getcfg_2bit,
407 .set_config = samsung_gpio_setcfg_2bit,
408 .get_config = samsung_gpio_getcfg_2bit,
411 .set_config = samsung_gpio_setcfg_2bit,
412 .get_config = samsung_gpio_getcfg_2bit,
417 * Default routines for controlling GPIO, based on the original S3C24XX
418 * GPIO functions which deal with the case where each gpio bank of the
419 * chip is as following:
421 * base + 0x00: Control register, 2 bits per gpio
422 * gpio n: 2 bits starting at (2*n)
423 * 00 = input, 01 = output, others mean special-function
424 * base + 0x04: Data register, 1 bit per gpio
428 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
430 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
431 void __iomem *base = ourchip->base;
435 samsung_gpio_lock(ourchip, flags);
437 con = __raw_readl(base + 0x00);
438 con &= ~(3 << (offset * 2));
440 __raw_writel(con, base + 0x00);
442 samsung_gpio_unlock(ourchip, flags);
446 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
447 unsigned offset, int value)
449 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
450 void __iomem *base = ourchip->base;
455 samsung_gpio_lock(ourchip, flags);
457 dat = __raw_readl(base + 0x04);
458 dat &= ~(1 << offset);
461 __raw_writel(dat, base + 0x04);
463 con = __raw_readl(base + 0x00);
464 con &= ~(3 << (offset * 2));
465 con |= 1 << (offset * 2);
467 __raw_writel(con, base + 0x00);
468 __raw_writel(dat, base + 0x04);
470 samsung_gpio_unlock(ourchip, flags);
475 * The samsung_gpiolib_4bit routines are to control the gpio banks where
476 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
479 * base + 0x00: Control register, 4 bits per gpio
480 * gpio n: 4 bits starting at (4*n)
481 * 0000 = input, 0001 = output, others mean special-function
482 * base + 0x04: Data register, 1 bit per gpio
485 * Note, since the data register is one bit per gpio and is at base + 0x4
486 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
487 * state of the output.
490 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
493 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
494 void __iomem *base = ourchip->base;
497 con = __raw_readl(base + GPIOCON_OFF);
498 if (ourchip->bitmap_gpio_int & BIT(offset))
499 con |= 0xf << con_4bit_shift(offset);
501 con &= ~(0xf << con_4bit_shift(offset));
502 __raw_writel(con, base + GPIOCON_OFF);
504 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
509 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
510 unsigned int offset, int value)
512 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
513 void __iomem *base = ourchip->base;
517 con = __raw_readl(base + GPIOCON_OFF);
518 con &= ~(0xf << con_4bit_shift(offset));
519 con |= 0x1 << con_4bit_shift(offset);
521 dat = __raw_readl(base + GPIODAT_OFF);
526 dat &= ~(1 << offset);
528 __raw_writel(dat, base + GPIODAT_OFF);
529 __raw_writel(con, base + GPIOCON_OFF);
530 __raw_writel(dat, base + GPIODAT_OFF);
532 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
538 * The next set of routines are for the case where the GPIO configuration
539 * registers are 4 bits per GPIO but there is more than one register (the
540 * bank has more than 8 GPIOs.
542 * This case is the similar to the 4 bit case, but the registers are as
545 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
546 * gpio n: 4 bits starting at (4*n)
547 * 0000 = input, 0001 = output, others mean special-function
548 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
549 * gpio n: 4 bits starting at (4*n)
550 * 0000 = input, 0001 = output, others mean special-function
551 * base + 0x08: Data register, 1 bit per gpio
554 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
555 * routines we store the 'base + 0x4' address so that these routines see
556 * the data register at ourchip->base + 0x04.
559 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
562 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
563 void __iomem *base = ourchip->base;
564 void __iomem *regcon = base;
572 con = __raw_readl(regcon);
573 con &= ~(0xf << con_4bit_shift(offset));
574 __raw_writel(con, regcon);
576 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
581 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
582 unsigned int offset, int value)
584 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
585 void __iomem *base = ourchip->base;
586 void __iomem *regcon = base;
589 unsigned con_offset = offset;
596 con = __raw_readl(regcon);
597 con &= ~(0xf << con_4bit_shift(con_offset));
598 con |= 0x1 << con_4bit_shift(con_offset);
600 dat = __raw_readl(base + GPIODAT_OFF);
605 dat &= ~(1 << offset);
607 __raw_writel(dat, base + GPIODAT_OFF);
608 __raw_writel(con, regcon);
609 __raw_writel(dat, base + GPIODAT_OFF);
611 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
616 #ifdef CONFIG_PLAT_S3C24XX
617 /* The next set of routines are for the case of s3c24xx bank a */
619 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
624 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
625 unsigned offset, int value)
627 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
628 void __iomem *base = ourchip->base;
633 local_irq_save(flags);
635 con = __raw_readl(base + 0x00);
636 dat = __raw_readl(base + 0x04);
638 dat &= ~(1 << offset);
642 __raw_writel(dat, base + 0x04);
644 con &= ~(1 << offset);
646 __raw_writel(con, base + 0x00);
647 __raw_writel(dat, base + 0x04);
649 local_irq_restore(flags);
654 static void samsung_gpiolib_set(struct gpio_chip *chip,
655 unsigned offset, int value)
657 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
658 void __iomem *base = ourchip->base;
662 samsung_gpio_lock(ourchip, flags);
664 dat = __raw_readl(base + 0x04);
665 dat &= ~(1 << offset);
668 __raw_writel(dat, base + 0x04);
670 samsung_gpio_unlock(ourchip, flags);
673 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
675 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
678 val = __raw_readl(ourchip->base + 0x04);
686 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
687 * for use with the configuration calls, and other parts of the s3c gpiolib
690 * Not all s3c support code will need this, as some configurations of cpu
691 * may only support one or two different configuration options and have an
692 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
693 * the machine support file should provide its own samsung_gpiolib_getchip()
694 * and any other necessary functions.
697 #ifdef CONFIG_S3C_GPIO_TRACK
698 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
700 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
705 gpn = chip->chip.base;
706 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
707 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
708 s3c_gpios[gpn] = chip;
711 #endif /* CONFIG_S3C_GPIO_TRACK */
714 * samsung_gpiolib_add() - add the Samsung gpio_chip.
715 * @chip: The chip to register
717 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
718 * information and makes the necessary alterations for the platform and
719 * notes the information for use with the configuration systems and any
720 * other parts of the system.
723 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
725 struct gpio_chip *gc = &chip->chip;
732 spin_lock_init(&chip->lock);
734 if (!gc->direction_input)
735 gc->direction_input = samsung_gpiolib_2bit_input;
736 if (!gc->direction_output)
737 gc->direction_output = samsung_gpiolib_2bit_output;
739 gc->set = samsung_gpiolib_set;
741 gc->get = samsung_gpiolib_get;
744 if (chip->pm != NULL) {
745 if (!chip->pm->save || !chip->pm->resume)
746 pr_err("gpio: %s has missing PM functions\n",
749 pr_err("gpio: %s has no PM function\n", gc->label);
752 /* gpiochip_add() prints own failure message on error. */
753 ret = gpiochip_add_data(gc, chip);
755 s3c_gpiolib_track(chip);
758 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
759 int nr_chips, void __iomem *base)
762 struct gpio_chip *gc = &chip->chip;
764 for (i = 0 ; i < nr_chips; i++, chip++) {
765 /* skip banks not present on SoC */
766 if (chip->chip.base >= S3C_GPIO_END)
770 chip->config = &s3c24xx_gpiocfg_default;
772 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
773 if ((base != NULL) && (chip->base == NULL))
774 chip->base = base + ((i) * 0x10);
776 if (!gc->direction_input)
777 gc->direction_input = samsung_gpiolib_2bit_input;
778 if (!gc->direction_output)
779 gc->direction_output = samsung_gpiolib_2bit_output;
781 samsung_gpiolib_add(chip);
785 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
786 int nr_chips, void __iomem *base,
791 for (i = 0 ; i < nr_chips; i++, chip++) {
792 chip->chip.direction_input = samsung_gpiolib_2bit_input;
793 chip->chip.direction_output = samsung_gpiolib_2bit_output;
796 chip->config = &samsung_gpio_cfgs[7];
798 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
799 if ((base != NULL) && (chip->base == NULL))
800 chip->base = base + ((i) * offset);
802 samsung_gpiolib_add(chip);
807 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
808 * @chip: The gpio chip that is being configured.
809 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
811 * This helper deal with the GPIO cases where the control register has 4 bits
812 * of control per GPIO, generally in the form of:
815 * others = Special functions (dependent on bank)
817 * Note, since the code to deal with the case where there are two control
818 * registers instead of one, we do not have a separate set of function
819 * (samsung_gpiolib_add_4bit2_chips)for each case.
822 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
823 int nr_chips, void __iomem *base)
827 for (i = 0 ; i < nr_chips; i++, chip++) {
828 chip->chip.direction_input = samsung_gpiolib_4bit_input;
829 chip->chip.direction_output = samsung_gpiolib_4bit_output;
832 chip->config = &samsung_gpio_cfgs[2];
834 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
835 if ((base != NULL) && (chip->base == NULL))
836 chip->base = base + ((i) * 0x20);
838 chip->bitmap_gpio_int = 0;
840 samsung_gpiolib_add(chip);
844 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
847 for (; nr_chips > 0; nr_chips--, chip++) {
848 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
849 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
852 chip->config = &samsung_gpio_cfgs[2];
854 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
856 samsung_gpiolib_add(chip);
860 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
862 struct samsung_gpio_chip *samsung_chip = gpiochip_get_data(chip);
864 return samsung_chip->irq_base + offset;
867 #ifdef CONFIG_PLAT_S3C24XX
868 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
871 if (soc_is_s3c2412())
872 return IRQ_EINT0_2412 + offset;
874 return IRQ_EINT0 + offset;
878 return IRQ_EINT4 + offset - 4;
884 #ifdef CONFIG_ARCH_S3C64XX
885 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
887 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
890 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
892 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
896 struct samsung_gpio_chip s3c24xx_gpios[] = {
897 #ifdef CONFIG_PLAT_S3C24XX
899 .config = &s3c24xx_gpiocfg_banka,
901 .base = S3C2410_GPA(0),
902 .owner = THIS_MODULE,
905 .direction_input = s3c24xx_gpiolib_banka_input,
906 .direction_output = s3c24xx_gpiolib_banka_output,
910 .base = S3C2410_GPB(0),
911 .owner = THIS_MODULE,
917 .base = S3C2410_GPC(0),
918 .owner = THIS_MODULE,
924 .base = S3C2410_GPD(0),
925 .owner = THIS_MODULE,
931 .base = S3C2410_GPE(0),
933 .owner = THIS_MODULE,
938 .base = S3C2410_GPF(0),
939 .owner = THIS_MODULE,
942 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
945 .irq_base = IRQ_EINT8,
947 .base = S3C2410_GPG(0),
948 .owner = THIS_MODULE,
951 .to_irq = samsung_gpiolib_to_irq,
955 .base = S3C2410_GPH(0),
956 .owner = THIS_MODULE,
961 /* GPIOS for the S3C2443 and later devices. */
963 .base = S3C2440_GPJCON,
965 .base = S3C2410_GPJ(0),
966 .owner = THIS_MODULE,
971 .base = S3C2443_GPKCON,
973 .base = S3C2410_GPK(0),
974 .owner = THIS_MODULE,
979 .base = S3C2443_GPLCON,
981 .base = S3C2410_GPL(0),
982 .owner = THIS_MODULE,
987 .base = S3C2443_GPMCON,
989 .base = S3C2410_GPM(0),
990 .owner = THIS_MODULE,
1001 * Bank GPIOs Style SlpCon ExtInt Group
1007 * F 16 2Bit Yes 4 [1]
1009 * H 10 4Bit[2] Yes 6
1010 * I 16 2Bit Yes None
1011 * J 12 2Bit Yes None
1012 * K 16 4Bit[2] No None
1013 * L 15 4Bit[2] No None
1014 * M 6 4Bit No IRQ_EINT
1015 * N 16 2Bit No IRQ_EINT
1020 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1021 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1024 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1025 #ifdef CONFIG_ARCH_S3C64XX
1028 .base = S3C64XX_GPA(0),
1029 .ngpio = S3C64XX_GPIO_A_NR,
1034 .base = S3C64XX_GPB(0),
1035 .ngpio = S3C64XX_GPIO_B_NR,
1040 .base = S3C64XX_GPC(0),
1041 .ngpio = S3C64XX_GPIO_C_NR,
1046 .base = S3C64XX_GPD(0),
1047 .ngpio = S3C64XX_GPIO_D_NR,
1051 .config = &samsung_gpio_cfgs[0],
1053 .base = S3C64XX_GPE(0),
1054 .ngpio = S3C64XX_GPIO_E_NR,
1058 .base = S3C64XX_GPG_BASE,
1060 .base = S3C64XX_GPG(0),
1061 .ngpio = S3C64XX_GPIO_G_NR,
1065 .base = S3C64XX_GPM_BASE,
1066 .config = &samsung_gpio_cfgs[1],
1068 .base = S3C64XX_GPM(0),
1069 .ngpio = S3C64XX_GPIO_M_NR,
1071 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1077 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1078 #ifdef CONFIG_ARCH_S3C64XX
1080 .base = S3C64XX_GPH_BASE + 0x4,
1082 .base = S3C64XX_GPH(0),
1083 .ngpio = S3C64XX_GPIO_H_NR,
1087 .base = S3C64XX_GPK_BASE + 0x4,
1088 .config = &samsung_gpio_cfgs[0],
1090 .base = S3C64XX_GPK(0),
1091 .ngpio = S3C64XX_GPIO_K_NR,
1095 .base = S3C64XX_GPL_BASE + 0x4,
1096 .config = &samsung_gpio_cfgs[1],
1098 .base = S3C64XX_GPL(0),
1099 .ngpio = S3C64XX_GPIO_L_NR,
1101 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1107 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1108 #ifdef CONFIG_ARCH_S3C64XX
1110 .base = S3C64XX_GPF_BASE,
1111 .config = &samsung_gpio_cfgs[6],
1113 .base = S3C64XX_GPF(0),
1114 .ngpio = S3C64XX_GPIO_F_NR,
1118 .config = &samsung_gpio_cfgs[7],
1120 .base = S3C64XX_GPI(0),
1121 .ngpio = S3C64XX_GPIO_I_NR,
1125 .config = &samsung_gpio_cfgs[7],
1127 .base = S3C64XX_GPJ(0),
1128 .ngpio = S3C64XX_GPIO_J_NR,
1132 .config = &samsung_gpio_cfgs[6],
1134 .base = S3C64XX_GPO(0),
1135 .ngpio = S3C64XX_GPIO_O_NR,
1139 .config = &samsung_gpio_cfgs[6],
1141 .base = S3C64XX_GPP(0),
1142 .ngpio = S3C64XX_GPIO_P_NR,
1146 .config = &samsung_gpio_cfgs[6],
1148 .base = S3C64XX_GPQ(0),
1149 .ngpio = S3C64XX_GPIO_Q_NR,
1153 .base = S3C64XX_GPN_BASE,
1154 .irq_base = IRQ_EINT(0),
1155 .config = &samsung_gpio_cfgs[5],
1157 .base = S3C64XX_GPN(0),
1158 .ngpio = S3C64XX_GPIO_N_NR,
1160 .to_irq = samsung_gpiolib_to_irq,
1166 /* TODO: cleanup soc_is_* */
1167 static __init int samsung_gpiolib_init(void)
1170 * Currently there are two drivers that can provide GPIO support for
1171 * Samsung SoCs. For device tree enabled platforms, the new
1172 * pinctrl-samsung driver is used, providing both GPIO and pin control
1173 * interfaces. For legacy (non-DT) platforms this driver is used.
1175 if (of_have_populated_dt())
1178 if (soc_is_s3c24xx()) {
1179 samsung_gpiolib_set_cfg(samsung_gpio_cfgs,
1180 ARRAY_SIZE(samsung_gpio_cfgs));
1181 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
1182 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
1183 } else if (soc_is_s3c64xx()) {
1184 samsung_gpiolib_set_cfg(samsung_gpio_cfgs,
1185 ARRAY_SIZE(samsung_gpio_cfgs));
1186 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
1187 ARRAY_SIZE(s3c64xx_gpios_2bit),
1188 S3C64XX_VA_GPIO + 0xE0, 0x20);
1189 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
1190 ARRAY_SIZE(s3c64xx_gpios_4bit),
1192 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
1193 ARRAY_SIZE(s3c64xx_gpios_4bit2));
1198 core_initcall(samsung_gpiolib_init);
1200 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
1202 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1203 unsigned long flags;
1210 offset = pin - chip->chip.base;
1212 samsung_gpio_lock(chip, flags);
1213 ret = samsung_gpio_do_setcfg(chip, offset, config);
1214 samsung_gpio_unlock(chip, flags);
1218 EXPORT_SYMBOL(s3c_gpio_cfgpin);
1220 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
1225 for (; nr > 0; nr--, start++) {
1226 ret = s3c_gpio_cfgpin(start, cfg);
1233 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
1235 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
1236 unsigned int cfg, samsung_gpio_pull_t pull)
1240 for (; nr > 0; nr--, start++) {
1241 s3c_gpio_setpull(start, pull);
1242 ret = s3c_gpio_cfgpin(start, cfg);
1249 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
1251 unsigned s3c_gpio_getcfg(unsigned int pin)
1253 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1254 unsigned long flags;
1259 offset = pin - chip->chip.base;
1261 samsung_gpio_lock(chip, flags);
1262 ret = samsung_gpio_do_getcfg(chip, offset);
1263 samsung_gpio_unlock(chip, flags);
1268 EXPORT_SYMBOL(s3c_gpio_getcfg);
1270 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
1272 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1273 unsigned long flags;
1279 offset = pin - chip->chip.base;
1281 samsung_gpio_lock(chip, flags);
1282 ret = samsung_gpio_do_setpull(chip, offset, pull);
1283 samsung_gpio_unlock(chip, flags);
1287 EXPORT_SYMBOL(s3c_gpio_setpull);
1289 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
1291 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1292 unsigned long flags;
1297 offset = pin - chip->chip.base;
1299 samsung_gpio_lock(chip, flags);
1300 pup = samsung_gpio_do_getpull(chip, offset);
1301 samsung_gpio_unlock(chip, flags);
1304 return (__force samsung_gpio_pull_t)pup;
1306 EXPORT_SYMBOL(s3c_gpio_getpull);
1308 #ifdef CONFIG_PLAT_S3C24XX
1309 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
1311 unsigned long flags;
1312 unsigned long misccr;
1314 local_irq_save(flags);
1315 misccr = __raw_readl(S3C24XX_MISCCR);
1318 __raw_writel(misccr, S3C24XX_MISCCR);
1319 local_irq_restore(flags);
1323 EXPORT_SYMBOL(s3c2410_modify_misccr);