2 * linux/arch/arm/mm/proc-v7.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv7 processor support.
12 #include <linux/arm-smccc.h>
13 #include <linux/init.h>
14 #include <linux/linkage.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/hwcap.h>
18 #include <asm/pgtable-hwdef.h>
19 #include <asm/pgtable.h>
21 #include "proc-macros.S"
23 #ifdef CONFIG_ARM_LPAE
24 #include "proc-v7-3level.S"
26 #include "proc-v7-2level.S"
29 ENTRY(cpu_v7_proc_init)
31 ENDPROC(cpu_v7_proc_init)
33 ENTRY(cpu_v7_proc_fin)
34 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
35 bic r0, r0, #0x1000 @ ...i............
36 bic r0, r0, #0x0006 @ .............ca.
37 mcr p15, 0, r0, c1, c0, 0 @ disable caches
39 ENDPROC(cpu_v7_proc_fin)
44 * Perform a soft reset of the system. Put the CPU into the
45 * same state as it would be if it had been reset, and branch
46 * to what would be the reset vector.
48 * - loc - location to jump to for soft reset
50 * This code must be executed using a flat identity mapping with
54 .pushsection .idmap.text, "ax"
56 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
57 bic r1, r1, #0x1 @ ...............m
58 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
59 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
68 * Idle the processor (eg, wait for interrupt).
70 * IRQs are already disabled.
73 dsb @ WFI may enter a low-power mode
76 ENDPROC(cpu_v7_do_idle)
78 ENTRY(cpu_v7_dcache_clean_area)
79 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
82 1: dcache_line_size r2, r3
83 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
89 ENDPROC(cpu_v7_dcache_clean_area)
91 #ifdef CONFIG_ARM_PSCI
93 ENTRY(cpu_v7_smc_switch_mm)
95 movw r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
96 movt r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
100 ENDPROC(cpu_v7_smc_switch_mm)
102 ENTRY(cpu_v7_hvc_switch_mm)
104 movw r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
105 movt r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
109 ENDPROC(cpu_v7_hvc_switch_mm)
111 ENTRY(cpu_v7_iciallu_switch_mm)
113 mcr p15, 0, r3, c7, c5, 0 @ ICIALLU
115 ENDPROC(cpu_v7_iciallu_switch_mm)
116 ENTRY(cpu_v7_bpiall_switch_mm)
118 mcr p15, 0, r3, c7, c5, 6 @ flush BTAC/BTB
120 ENDPROC(cpu_v7_bpiall_switch_mm)
122 string cpu_v7_name, "ARMv7 Processor"
125 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
126 .globl cpu_v7_suspend_size
127 .equ cpu_v7_suspend_size, 4 * 9
128 #ifdef CONFIG_ARM_CPU_SUSPEND
129 ENTRY(cpu_v7_do_suspend)
130 stmfd sp!, {r4 - r11, lr}
131 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
132 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
135 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
136 #ifdef CONFIG_ARM_LPAE
137 mrrc p15, 1, r5, r7, c2 @ TTB 1
139 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
141 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
143 mrc p15, 0, r8, c1, c0, 0 @ Control register
144 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
145 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
147 ldmfd sp!, {r4 - r11, pc}
148 ENDPROC(cpu_v7_do_suspend)
150 ENTRY(cpu_v7_do_resume)
152 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
153 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
155 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
156 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
159 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
160 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
161 #ifdef CONFIG_ARM_LPAE
162 mcrr p15, 0, r1, ip, c2 @ TTB 0
163 mcrr p15, 1, r5, r7, c2 @ TTB 1
165 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
166 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
167 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
168 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
170 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
173 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
174 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
175 #endif /* CONFIG_MMU */
176 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
177 teq r4, r9 @ Is it already set?
178 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
179 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
182 mov r0, r8 @ control register
184 ENDPROC(cpu_v7_do_resume)
187 .globl cpu_ca9mp_suspend_size
188 .equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
189 #ifdef CONFIG_ARM_CPU_SUSPEND
190 ENTRY(cpu_ca9mp_do_suspend)
192 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
193 mrc p15, 0, r5, c15, c0, 0 @ Power register
197 ENDPROC(cpu_ca9mp_do_suspend)
199 ENTRY(cpu_ca9mp_do_resume)
201 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
202 teq r4, r10 @ Already restored?
203 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
204 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
205 teq r5, r10 @ Already restored?
206 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
208 ENDPROC(cpu_ca9mp_do_resume)
211 #ifdef CONFIG_CPU_PJ4B
212 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
213 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
214 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
215 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
216 globl_equ cpu_pj4b_reset, cpu_v7_reset
217 #ifdef CONFIG_PJ4B_ERRATA_4742
218 ENTRY(cpu_pj4b_do_idle)
219 dsb @ WFI may enter a low-power mode
223 ENDPROC(cpu_pj4b_do_idle)
225 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
227 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
228 #ifdef CONFIG_ARM_CPU_SUSPEND
229 ENTRY(cpu_pj4b_do_suspend)
230 stmfd sp!, {r6 - r10}
231 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
232 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
233 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
234 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
235 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
236 stmia r0!, {r6 - r10}
237 ldmfd sp!, {r6 - r10}
239 ENDPROC(cpu_pj4b_do_suspend)
241 ENTRY(cpu_pj4b_do_resume)
242 ldmia r0!, {r6 - r10}
243 mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features
244 mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0
245 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
246 mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1
247 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC
249 ENDPROC(cpu_pj4b_do_resume)
251 .globl cpu_pj4b_suspend_size
252 .equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
259 * Initialise TLB, Caches, and MMU state ready to switch the MMU
260 * on. Return in r0 the new CP15 C1 control register setting.
262 * r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack
263 * r4: TTBR0 (low word)
264 * r5: TTBR0 (high word if LPAE)
266 * r9: Main ID register
268 * This should be able to cover all ARMv7 cores.
270 * It is assumed that:
271 * - cache type register is implemented
276 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
284 1: adr r12, __v7_setup_stack @ the local stack
285 stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
287 ldmia r12, {r0-r5, lr}
289 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
290 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
291 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
292 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
293 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
294 mcreq p15, 0, r0, c1, c0, 1
300 * r0, r10 available for use
301 * r1, r2, r4, r5, r9, r13: must be preserved
302 * r3: contains MIDR rX number in bits 23-20
303 * r6: contains MIDR rXpY as 8-bit XY number
307 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
308 teq r3, #0x00100000 @ only present in r1p*
309 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
310 orreq r0, r0, #(1 << 6) @ set IBE to 1
311 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
313 #ifdef CONFIG_ARM_ERRATA_458693
314 teq r6, #0x20 @ only present in r2p0
315 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
316 orreq r0, r0, #(1 << 5) @ set L1NEON to 1
317 orreq r0, r0, #(1 << 9) @ set PLDNOP to 1
318 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
320 #ifdef CONFIG_ARM_ERRATA_460075
321 teq r6, #0x20 @ only present in r2p0
322 mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
324 orreq r0, r0, #(1 << 22) @ set the Write Allocate disable bit
325 mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
330 #ifdef CONFIG_ARM_ERRATA_742230
331 cmp r6, #0x22 @ only present up to r2p2
332 mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register
333 orrle r0, r0, #1 << 4 @ set bit #4
334 mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register
336 #ifdef CONFIG_ARM_ERRATA_742231
337 teq r6, #0x20 @ present in r2p0
338 teqne r6, #0x21 @ present in r2p1
339 teqne r6, #0x22 @ present in r2p2
340 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
341 orreq r0, r0, #1 << 12 @ set bit #12
342 orreq r0, r0, #1 << 22 @ set bit #22
343 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
345 #ifdef CONFIG_ARM_ERRATA_743622
346 teq r3, #0x00200000 @ only present in r2p*
347 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
348 orreq r0, r0, #1 << 6 @ set bit #6
349 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
351 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
352 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
354 mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register
355 orrlt r0, r0, #1 << 11 @ set bit #11
356 mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register
362 #ifdef CONFIG_ARM_ERRATA_773022
363 cmp r6, #0x4 @ only present up to r0p4
364 mrcle p15, 0, r0, c1, c0, 1 @ read aux control register
365 orrle r0, r0, #1 << 1 @ disable loop buffer
366 mcrle p15, 0, r0, c1, c0, 1 @ write aux control register
371 #ifdef CONFIG_CPU_PJ4B
373 /* Auxiliary Debug Modes Control 1 Register */
374 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
375 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
376 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
378 /* Auxiliary Debug Modes Control 2 Register */
379 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
380 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
381 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
382 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
383 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
384 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
385 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
387 /* Auxiliary Functional Modes Control Register 0 */
388 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
389 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
390 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
392 /* Auxiliary Debug Modes Control 0 Register */
393 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
395 /* Auxiliary Debug Modes Control 1 Register */
396 mrc p15, 1, r0, c15, c1, 1
397 orr r0, r0, #PJ4B_CLEAN_LINE
398 orr r0, r0, #PJ4B_INTER_PARITY
399 bic r0, r0, #PJ4B_STATIC_BP
400 mcr p15, 1, r0, c15, c1, 1
402 /* Auxiliary Debug Modes Control 2 Register */
403 mrc p15, 1, r0, c15, c1, 2
404 bic r0, r0, #PJ4B_FAST_LDR
405 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
406 mcr p15, 1, r0, c15, c1, 2
408 /* Auxiliary Functional Modes Control Register 0 */
409 mrc p15, 1, r0, c15, c2, 0
411 orr r0, r0, #PJ4B_SMP_CFB
413 orr r0, r0, #PJ4B_L1_PAR_CHK
414 orr r0, r0, #PJ4B_BROADCAST_CACHE
415 mcr p15, 1, r0, c15, c2, 0
417 /* Auxiliary Debug Modes Control 0 Register */
418 mrc p15, 1, r0, c15, c1, 0
419 orr r0, r0, #PJ4B_WFI_WFE
420 mcr p15, 1, r0, c15, c1, 0
422 #endif /* CONFIG_CPU_PJ4B */
425 adr r12, __v7_setup_stack @ the local stack
426 stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
428 ldmia r12, {r0-r5, lr}
431 and r0, r9, #0xff000000 @ ARM?
434 and r3, r9, #0x00f00000 @ variant
435 and r6, r9, #0x0000000f @ revision
436 orr r6, r6, r3, lsr #20-4 @ combine variant and revision
437 ubfx r0, r9, #4, #12 @ primary part number
439 /* Cortex-A8 Errata */
440 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
444 /* Cortex-A9 Errata */
445 ldr r10, =0x00000c09 @ Cortex-A9 primary part number
449 /* Cortex-A15 Errata */
450 ldr r10, =0x00000c0f @ Cortex-A15 primary part number
456 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
458 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
459 v7_ttb_setup r10, r4, r5, r8, r3 @ TTBCR, TTBRx setup
462 mcr p15, 0, r3, c10, c2, 0 @ write PRRR
463 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
465 dsb @ Complete invalidations
466 #ifndef CONFIG_ARM_THUMBEE
467 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
468 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
469 teq r0, #(1 << 12) @ check if ThumbEE is present
472 mcr p14, 6, r3, c1, c0, 0 @ Initialize TEEHBR to 0
473 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
474 orr r0, r0, #1 @ set the 1st bit in order to
475 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
480 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
481 #ifdef CONFIG_SWP_EMULATE
482 orr r3, r3, #(1 << 10) @ set SW bit in "clear"
483 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
485 mrc p15, 0, r0, c1, c0, 0 @ read control register
486 bic r0, r0, r3 @ clear bits them
487 orr r0, r0, r6 @ set them
488 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
489 ret lr @ return to head.S:__ret
494 .space 4 * 7 @ 12 registers
498 .weak cpu_v7_bugs_init
500 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
501 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
503 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
504 @ generic v7 bpiall on context switch
505 globl_equ cpu_v7_bpiall_proc_init, cpu_v7_proc_init
506 globl_equ cpu_v7_bpiall_proc_fin, cpu_v7_proc_fin
507 globl_equ cpu_v7_bpiall_reset, cpu_v7_reset
508 globl_equ cpu_v7_bpiall_do_idle, cpu_v7_do_idle
509 globl_equ cpu_v7_bpiall_dcache_clean_area, cpu_v7_dcache_clean_area
510 globl_equ cpu_v7_bpiall_set_pte_ext, cpu_v7_set_pte_ext
511 globl_equ cpu_v7_bpiall_suspend_size, cpu_v7_suspend_size
512 #ifdef CONFIG_ARM_CPU_SUSPEND
513 globl_equ cpu_v7_bpiall_do_suspend, cpu_v7_do_suspend
514 globl_equ cpu_v7_bpiall_do_resume, cpu_v7_do_resume
516 define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
518 #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_bpiall_processor_functions
520 #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_processor_functions
523 #ifndef CONFIG_ARM_LPAE
524 @ Cortex-A8 - always needs bpiall switch_mm implementation
525 globl_equ cpu_ca8_proc_init, cpu_v7_proc_init
526 globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin
527 globl_equ cpu_ca8_reset, cpu_v7_reset
528 globl_equ cpu_ca8_do_idle, cpu_v7_do_idle
529 globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
530 globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext
531 globl_equ cpu_ca8_switch_mm, cpu_v7_bpiall_switch_mm
532 globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size
533 #ifdef CONFIG_ARM_CPU_SUSPEND
534 globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend
535 globl_equ cpu_ca8_do_resume, cpu_v7_do_resume
537 define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca8_ibe
539 @ Cortex-A9 - needs more registers preserved across suspend/resume
540 @ and bpiall switch_mm for hardening
541 globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init
542 globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin
543 globl_equ cpu_ca9mp_reset, cpu_v7_reset
544 globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle
545 globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
546 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
547 globl_equ cpu_ca9mp_switch_mm, cpu_v7_bpiall_switch_mm
549 globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm
551 globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext
552 define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
555 @ Cortex-A15 - needs iciallu switch_mm for hardening
556 globl_equ cpu_ca15_proc_init, cpu_v7_proc_init
557 globl_equ cpu_ca15_proc_fin, cpu_v7_proc_fin
558 globl_equ cpu_ca15_reset, cpu_v7_reset
559 globl_equ cpu_ca15_do_idle, cpu_v7_do_idle
560 globl_equ cpu_ca15_dcache_clean_area, cpu_v7_dcache_clean_area
561 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
562 globl_equ cpu_ca15_switch_mm, cpu_v7_iciallu_switch_mm
564 globl_equ cpu_ca15_switch_mm, cpu_v7_switch_mm
566 globl_equ cpu_ca15_set_pte_ext, cpu_v7_set_pte_ext
567 globl_equ cpu_ca15_suspend_size, cpu_v7_suspend_size
568 globl_equ cpu_ca15_do_suspend, cpu_v7_do_suspend
569 globl_equ cpu_ca15_do_resume, cpu_v7_do_resume
570 define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca15_ibe
571 #ifdef CONFIG_CPU_PJ4B
572 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
577 string cpu_arch_name, "armv7"
578 string cpu_elf_name, "v7"
581 .section ".proc.info.init", #alloc
584 * Standard v7 proc info content
586 .macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
587 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
588 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
589 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
590 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
591 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
592 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
593 initfn \initfunc, \name
596 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
597 HWCAP_EDSP | HWCAP_TLS | \hwcaps
605 #ifndef CONFIG_ARM_LPAE
607 * ARM Ltd. Cortex A5 processor.
609 .type __v7_ca5mp_proc_info, #object
610 __v7_ca5mp_proc_info:
613 __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
614 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
617 * ARM Ltd. Cortex A9 processor.
619 .type __v7_ca9mp_proc_info, #object
620 __v7_ca9mp_proc_info:
623 __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
624 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
627 * ARM Ltd. Cortex A8 processor.
629 .type __v7_ca8_proc_info, #object
633 __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
634 .size __v7_ca8_proc_info, . - __v7_ca8_proc_info
636 #endif /* CONFIG_ARM_LPAE */
639 * Marvell PJ4B processor.
641 #ifdef CONFIG_CPU_PJ4B
642 .type __v7_pj4b_proc_info, #object
646 __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
647 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
651 * ARM Ltd. Cortex R7 processor.
653 .type __v7_cr7mp_proc_info, #object
654 __v7_cr7mp_proc_info:
657 __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
658 .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
661 * ARM Ltd. Cortex A7 processor.
663 .type __v7_ca7mp_proc_info, #object
664 __v7_ca7mp_proc_info:
667 __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
668 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
671 * ARM Ltd. Cortex A12 processor.
673 .type __v7_ca12mp_proc_info, #object
674 __v7_ca12mp_proc_info:
677 __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
678 .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
681 * ARM Ltd. Cortex A15 processor.
683 .type __v7_ca15mp_proc_info, #object
684 __v7_ca15mp_proc_info:
687 __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup, proc_fns = ca15_processor_functions
688 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
691 * Broadcom Corporation Brahma-B15 processor.
693 .type __v7_b15mp_proc_info, #object
694 __v7_b15mp_proc_info:
697 __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup, proc_fns = ca15_processor_functions
698 .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
701 * ARM Ltd. Cortex A17 processor.
703 .type __v7_ca17mp_proc_info, #object
704 __v7_ca17mp_proc_info:
707 __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
708 .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
710 /* ARM Ltd. Cortex A73 processor */
711 .type __v7_ca73_proc_info, #object
715 __v7_proc __v7_ca73_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
716 .size __v7_ca73_proc_info, . - __v7_ca73_proc_info
718 /* ARM Ltd. Cortex A75 processor */
719 .type __v7_ca75_proc_info, #object
723 __v7_proc __v7_ca75_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
724 .size __v7_ca75_proc_info, . - __v7_ca75_proc_info
727 * Qualcomm Inc. Krait processors.
729 .type __krait_proc_info, #object
731 .long 0x510f0400 @ Required ID value
732 .long 0xff0ffc00 @ Mask for ID
734 * Some Krait processors don't indicate support for SDIV and UDIV
735 * instructions in the ARM instruction set, even though they actually
736 * do support them. They also don't indicate support for fused multiply
737 * instructions even though they actually do support them.
739 __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
740 .size __krait_proc_info, . - __krait_proc_info
743 * Match any ARMv7 processor core.
745 .type __v7_proc_info, #object
747 .long 0x000f0000 @ Required ID value
748 .long 0x000f0000 @ Mask for ID
749 __v7_proc __v7_proc_info, __v7_setup
750 .size __v7_proc_info, . - __v7_proc_info