arch/arm/mm/proc-v7.S

   1 /*
   2  *  linux/arch/arm/mm/proc-v7.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  This is the "shell" of the ARMv7 processor support.
  11  */
  12 #include <linux/arm-smccc.h>
  13 #include <linux/init.h>
  14 #include <linux/linkage.h>
  15 #include <asm/assembler.h>
  16 #include <asm/asm-offsets.h>
  17 #include <asm/hwcap.h>
  18 #include <asm/pgtable-hwdef.h>
  19 #include <asm/pgtable.h>
  20 #include <asm/memory.h>
  21
  22 #include "proc-macros.S"
  23
  24 #ifdef CONFIG_ARM_LPAE
  25 #include "proc-v7-3level.S"
  26 #else
  27 #include "proc-v7-2level.S"
  28 #endif
  29
  30 ENTRY(cpu_v7_proc_init)
  31         ret     lr
  32 ENDPROC(cpu_v7_proc_init)
  33
  34 ENTRY(cpu_v7_proc_fin)
  35         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  36         bic     r0, r0, #0x1000                 @ ...i............
  37         bic     r0, r0, #0x0006                 @ .............ca.
  38         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  39         ret     lr
  40 ENDPROC(cpu_v7_proc_fin)
  41
  42 /*
  43  *      cpu_v7_reset(loc)
  44  *
  45  *      Perform a soft reset of the system.  Put the CPU into the
  46  *      same state as it would be if it had been reset, and branch
  47  *      to what would be the reset vector.
  48  *
  49  *      - loc   - location to jump to for soft reset
  50  *
  51  *      This code must be executed using a flat identity mapping with
  52  *      caches disabled.
  53  */
  54         .align  5
  55         .pushsection    .idmap.text, "ax"
  56 ENTRY(cpu_v7_reset)
  57         mrc     p15, 0, r1, c1, c0, 0           @ ctrl register
  58         bic     r1, r1, #0x1                    @ ...............m
  59  THUMB( bic     r1, r1, #1 << 30 )              @ SCTLR.TE (Thumb exceptions)
  60         mcr     p15, 0, r1, c1, c0, 0           @ disable MMU
  61         isb
  62         bx      r0
  63 ENDPROC(cpu_v7_reset)
  64         .popsection
  65
  66 /*
  67  *      cpu_v7_do_idle()
  68  *
  69  *      Idle the processor (eg, wait for interrupt).
  70  *
  71  *      IRQs are already disabled.
  72  */
  73 ENTRY(cpu_v7_do_idle)
  74         dsb                                     @ WFI may enter a low-power mode
  75         wfi
  76         ret     lr
  77 ENDPROC(cpu_v7_do_idle)
  78
  79 ENTRY(cpu_v7_dcache_clean_area)
  80         ALT_SMP(W(nop))                 @ MP extensions imply L1 PTW
  81         ALT_UP_B(1f)
  82         ret     lr
  83 1:      dcache_line_size r2, r3
  84 2:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  85         add     r0, r0, r2
  86         subs    r1, r1, r2
  87         bhi     2b
  88         dsb     ishst
  89         ret     lr
  90 ENDPROC(cpu_v7_dcache_clean_area)
  91
  92 #ifdef CONFIG_ARM_PSCI
  93         .arch_extension sec
  94 ENTRY(cpu_v7_smc_switch_mm)
  95         stmfd   sp!, {r0 - r3}
  96         movw    r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
  97         movt    r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
  98         smc     #0
  99         ldmfd   sp!, {r0 - r3}
 100         b       cpu_v7_switch_mm
 101 ENDPROC(cpu_v7_smc_switch_mm)
 102         .arch_extension virt
 103 ENTRY(cpu_v7_hvc_switch_mm)
 104         stmfd   sp!, {r0 - r3}
 105         movw    r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
 106         movt    r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
 107         hvc     #0
 108         ldmfd   sp!, {r0 - r3}
 109         b       cpu_v7_switch_mm
 110 ENDPROC(cpu_v7_hvc_switch_mm)
 111 #endif
 112 ENTRY(cpu_v7_iciallu_switch_mm)
 113         mov     r3, #0
 114         mcr     p15, 0, r3, c7, c5, 0           @ ICIALLU
 115         b       cpu_v7_switch_mm
 116 ENDPROC(cpu_v7_iciallu_switch_mm)
 117 ENTRY(cpu_v7_bpiall_switch_mm)
 118         mov     r3, #0
 119         mcr     p15, 0, r3, c7, c5, 6           @ flush BTAC/BTB
 120         b       cpu_v7_switch_mm
 121 ENDPROC(cpu_v7_bpiall_switch_mm)
 122
 123         string  cpu_v7_name, "ARMv7 Processor"
 124         .align
 125
 126 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
 127 .globl  cpu_v7_suspend_size
 128 .equ    cpu_v7_suspend_size, 4 * 9
 129 #ifdef CONFIG_ARM_CPU_SUSPEND
 130 ENTRY(cpu_v7_do_suspend)
 131         stmfd   sp!, {r4 - r11, lr}
 132         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 133         mrc     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
 134         stmia   r0!, {r4 - r5}
 135 #ifdef CONFIG_MMU
 136         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
 137 #ifdef CONFIG_ARM_LPAE
 138         mrrc    p15, 1, r5, r7, c2      @ TTB 1
 139 #else
 140         mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
 141 #endif
 142         mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
 143 #endif
 144         mrc     p15, 0, r8, c1, c0, 0   @ Control register
 145         mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
 146         mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
 147         stmia   r0, {r5 - r11}
 148         ldmfd   sp!, {r4 - r11, pc}
 149 ENDPROC(cpu_v7_do_suspend)
 150
 151 ENTRY(cpu_v7_do_resume)
 152         mov     ip, #0
 153         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
 154         mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
 155         ldmia   r0!, {r4 - r5}
 156         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 157         mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
 158         ldmia   r0, {r5 - r11}
 159 #ifdef CONFIG_MMU
 160         mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
 161         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
 162 #ifdef CONFIG_ARM_LPAE
 163         mcrr    p15, 0, r1, ip, c2      @ TTB 0
 164         mcrr    p15, 1, r5, r7, c2      @ TTB 1
 165 #else
 166         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
 167         ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
 168         mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
 169         mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
 170 #endif
 171         mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
 172         ldr     r4, =PRRR               @ PRRR
 173         ldr     r5, =NMRR               @ NMRR
 174         mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
 175         mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
 176 #endif  /* CONFIG_MMU */
 177         mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
 178         teq     r4, r9                  @ Is it already set?
 179         mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
 180         mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
 181         isb
 182         dsb
 183         mov     r0, r8                  @ control register
 184         b       cpu_resume_mmu
 185 ENDPROC(cpu_v7_do_resume)
 186 #endif
 187
 188 .globl  cpu_ca9mp_suspend_size
 189 .equ    cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
 190 #ifdef CONFIG_ARM_CPU_SUSPEND
 191 ENTRY(cpu_ca9mp_do_suspend)
 192         stmfd   sp!, {r4 - r5}
 193         mrc     p15, 0, r4, c15, c0, 1          @ Diagnostic register
 194         mrc     p15, 0, r5, c15, c0, 0          @ Power register
 195         stmia   r0!, {r4 - r5}
 196         ldmfd   sp!, {r4 - r5}
 197         b       cpu_v7_do_suspend
 198 ENDPROC(cpu_ca9mp_do_suspend)
 199
 200 ENTRY(cpu_ca9mp_do_resume)
 201         ldmia   r0!, {r4 - r5}
 202         mrc     p15, 0, r10, c15, c0, 1         @ Read Diagnostic register
 203         teq     r4, r10                         @ Already restored?
 204         mcrne   p15, 0, r4, c15, c0, 1          @ No, so restore it
 205         mrc     p15, 0, r10, c15, c0, 0         @ Read Power register
 206         teq     r5, r10                         @ Already restored?
 207         mcrne   p15, 0, r5, c15, c0, 0          @ No, so restore it
 208         b       cpu_v7_do_resume
 209 ENDPROC(cpu_ca9mp_do_resume)
 210 #endif
 211
 212 #ifdef CONFIG_CPU_PJ4B
 213         globl_equ       cpu_pj4b_switch_mm,     cpu_v7_switch_mm
 214         globl_equ       cpu_pj4b_set_pte_ext,   cpu_v7_set_pte_ext
 215         globl_equ       cpu_pj4b_proc_init,     cpu_v7_proc_init
 216         globl_equ       cpu_pj4b_proc_fin,      cpu_v7_proc_fin
 217         globl_equ       cpu_pj4b_reset,         cpu_v7_reset
 218 #ifdef CONFIG_PJ4B_ERRATA_4742
 219 ENTRY(cpu_pj4b_do_idle)
 220         dsb                                     @ WFI may enter a low-power mode
 221         wfi
 222         dsb                                     @barrier
 223         ret     lr
 224 ENDPROC(cpu_pj4b_do_idle)
 225 #else
 226         globl_equ       cpu_pj4b_do_idle,       cpu_v7_do_idle
 227 #endif
 228         globl_equ       cpu_pj4b_dcache_clean_area,     cpu_v7_dcache_clean_area
 229 #ifdef CONFIG_ARM_CPU_SUSPEND
 230 ENTRY(cpu_pj4b_do_suspend)
 231         stmfd   sp!, {r6 - r10}
 232         mrc     p15, 1, r6, c15, c1, 0  @ save CP15 - extra features
 233         mrc     p15, 1, r7, c15, c2, 0  @ save CP15 - Aux Func Modes Ctrl 0
 234         mrc     p15, 1, r8, c15, c1, 2  @ save CP15 - Aux Debug Modes Ctrl 2
 235         mrc     p15, 1, r9, c15, c1, 1  @ save CP15 - Aux Debug Modes Ctrl 1
 236         mrc     p15, 0, r10, c9, c14, 0  @ save CP15 - PMC
 237         stmia   r0!, {r6 - r10}
 238         ldmfd   sp!, {r6 - r10}
 239         b cpu_v7_do_suspend
 240 ENDPROC(cpu_pj4b_do_suspend)
 241
 242 ENTRY(cpu_pj4b_do_resume)
 243         ldmia   r0!, {r6 - r10}
 244         mcr     p15, 1, r6, c15, c1, 0  @ restore CP15 - extra features
 245         mcr     p15, 1, r7, c15, c2, 0  @ restore CP15 - Aux Func Modes Ctrl 0
 246         mcr     p15, 1, r8, c15, c1, 2  @ restore CP15 - Aux Debug Modes Ctrl 2
 247         mcr     p15, 1, r9, c15, c1, 1  @ restore CP15 - Aux Debug Modes Ctrl 1
 248         mcr     p15, 0, r10, c9, c14, 0  @ restore CP15 - PMC
 249         b cpu_v7_do_resume
 250 ENDPROC(cpu_pj4b_do_resume)
 251 #endif
 252 .globl  cpu_pj4b_suspend_size
 253 .equ    cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
 254
 255 #endif
 256
 257 /*
 258  *      __v7_setup
 259  *
 260  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
 261  *      on.  Return in r0 the new CP15 C1 control register setting.
 262  *
 263  *      r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack
 264  *      r4: TTBR0 (low word)
 265  *      r5: TTBR0 (high word if LPAE)
 266  *      r8: TTBR1
 267  *      r9: Main ID register
 268  *
 269  *      This should be able to cover all ARMv7 cores.
 270  *
 271  *      It is assumed that:
 272  *      - cache type register is implemented
 273  */
 274 __v7_ca5mp_setup:
 275 __v7_ca9mp_setup:
 276 __v7_cr7mp_setup:
 277         mov     r10, #(1 << 0)                  @ Cache/TLB ops broadcasting
 278         b       1f
 279 __v7_ca7mp_setup:
 280 __v7_ca12mp_setup:
 281 __v7_ca15mp_setup:
 282 __v7_b15mp_setup:
 283 __v7_ca17mp_setup:
 284         mov     r10, #0
 285 1:      adr     r0, __v7_setup_stack_ptr
 286         ldr     r12, [r0]
 287         add     r12, r12, r0                    @ the local stack
 288         stmia   r12, {r1-r6, lr}                @ v7_invalidate_l1 touches r0-r6
 289         bl      v7_invalidate_l1
 290         ldmia   r12, {r1-r6, lr}
 291 #ifdef CONFIG_SMP
 292         orr     r10, r10, #(1 << 6)             @ Enable SMP/nAMP mode
 293         ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
 294         ALT_UP(mov      r0, r10)                @ fake it for UP
 295         orr     r10, r10, r0                    @ Set required bits
 296         teq     r10, r0                         @ Were they already set?
 297         mcrne   p15, 0, r10, c1, c0, 1          @ No, update register
 298 #endif
 299         b       __v7_setup_cont
 300
 301 /*
 302  * Errata:
 303  *  r0, r10 available for use
 304  *  r1, r2, r4, r5, r9, r13: must be preserved
 305  *  r3: contains MIDR rX number in bits 23-20
 306  *  r6: contains MIDR rXpY as 8-bit XY number
 307  *  r9: MIDR
 308  */
 309 __ca8_errata:
 310 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
 311         teq     r3, #0x00100000                 @ only present in r1p*
 312         mrceq   p15, 0, r0, c1, c0, 1           @ read aux control register
 313         orreq   r0, r0, #(1 << 6)               @ set IBE to 1
 314         mcreq   p15, 0, r0, c1, c0, 1           @ write aux control register
 315 #endif
 316 #ifdef CONFIG_ARM_ERRATA_458693
 317         teq     r6, #0x20                       @ only present in r2p0
 318         mrceq   p15, 0, r0, c1, c0, 1           @ read aux control register
 319         orreq   r0, r0, #(1 << 5)               @ set L1NEON to 1
 320         orreq   r0, r0, #(1 << 9)               @ set PLDNOP to 1
 321         mcreq   p15, 0, r0, c1, c0, 1           @ write aux control register
 322 #endif
 323 #ifdef CONFIG_ARM_ERRATA_460075
 324         teq     r6, #0x20                       @ only present in r2p0
 325         mrceq   p15, 1, r0, c9, c0, 2           @ read L2 cache aux ctrl register
 326         tsteq   r0, #1 << 22
 327         orreq   r0, r0, #(1 << 22)              @ set the Write Allocate disable bit
 328         mcreq   p15, 1, r0, c9, c0, 2           @ write the L2 cache aux ctrl register
 329 #endif
 330         b       __errata_finish
 331
 332 __ca9_errata:
 333 #ifdef CONFIG_ARM_ERRATA_742230
 334         cmp     r6, #0x22                       @ only present up to r2p2
 335         mrcle   p15, 0, r0, c15, c0, 1          @ read diagnostic register
 336         orrle   r0, r0, #1 << 4                 @ set bit #4
 337         mcrle   p15, 0, r0, c15, c0, 1          @ write diagnostic register
 338 #endif
 339 #ifdef CONFIG_ARM_ERRATA_742231
 340         teq     r6, #0x20                       @ present in r2p0
 341         teqne   r6, #0x21                       @ present in r2p1
 342         teqne   r6, #0x22                       @ present in r2p2
 343         mrceq   p15, 0, r0, c15, c0, 1          @ read diagnostic register
 344         orreq   r0, r0, #1 << 12                @ set bit #12
 345         orreq   r0, r0, #1 << 22                @ set bit #22
 346         mcreq   p15, 0, r0, c15, c0, 1          @ write diagnostic register
 347 #endif
 348 #ifdef CONFIG_ARM_ERRATA_743622
 349         teq     r3, #0x00200000                 @ only present in r2p*
 350         mrceq   p15, 0, r0, c15, c0, 1          @ read diagnostic register
 351         orreq   r0, r0, #1 << 6                 @ set bit #6
 352         mcreq   p15, 0, r0, c15, c0, 1          @ write diagnostic register
 353 #endif
 354 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
 355         ALT_SMP(cmp r6, #0x30)                  @ present prior to r3p0
 356         ALT_UP_B(1f)
 357         mrclt   p15, 0, r0, c15, c0, 1          @ read diagnostic register
 358         orrlt   r0, r0, #1 << 11                @ set bit #11
 359         mcrlt   p15, 0, r0, c15, c0, 1          @ write diagnostic register
 360 1:
 361 #endif
 362         b       __errata_finish
 363
 364 __ca15_errata:
 365 #ifdef CONFIG_ARM_ERRATA_773022
 366         cmp     r6, #0x4                        @ only present up to r0p4
 367         mrcle   p15, 0, r0, c1, c0, 1           @ read aux control register
 368         orrle   r0, r0, #1 << 1                 @ disable loop buffer
 369         mcrle   p15, 0, r0, c1, c0, 1           @ write aux control register
 370 #endif
 371         b       __errata_finish
 372
 373 __ca12_errata:
 374 #ifdef CONFIG_ARM_ERRATA_818325_852422
 375         mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
 376         orr     r10, r10, #1 << 12              @ set bit #12
 377         mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
 378 #endif
 379 #ifdef CONFIG_ARM_ERRATA_821420
 380         mrc     p15, 0, r10, c15, c0, 2         @ read internal feature reg
 381         orr     r10, r10, #1 << 1               @ set bit #1
 382         mcr     p15, 0, r10, c15, c0, 2         @ write internal feature reg
 383 #endif
 384 #ifdef CONFIG_ARM_ERRATA_825619
 385         mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
 386         orr     r10, r10, #1 << 24              @ set bit #24
 387         mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
 388 #endif
 389         b       __errata_finish
 390
 391 __ca17_errata:
 392 #ifdef CONFIG_ARM_ERRATA_852421
 393         cmp     r6, #0x12                       @ only present up to r1p2
 394         mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 395         orrle   r10, r10, #1 << 24              @ set bit #24
 396         mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 397 #endif
 398 #ifdef CONFIG_ARM_ERRATA_852423
 399         cmp     r6, #0x12                       @ only present up to r1p2
 400         mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 401         orrle   r10, r10, #1 << 12              @ set bit #12
 402         mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 403 #endif
 404         b       __errata_finish
 405
 406 __v7_pj4b_setup:
 407 #ifdef CONFIG_CPU_PJ4B
 408
 409 /* Auxiliary Debug Modes Control 1 Register */
 410 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
 411 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
 412 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
 413
 414 /* Auxiliary Debug Modes Control 2 Register */
 415 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
 416 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
 417 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
 418 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
 419 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
 420 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
 421                             PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
 422
 423 /* Auxiliary Functional Modes Control Register 0 */
 424 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
 425 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
 426 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
 427
 428 /* Auxiliary Debug Modes Control 0 Register */
 429 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
 430
 431         /* Auxiliary Debug Modes Control 1 Register */
 432         mrc     p15, 1, r0, c15, c1, 1
 433         orr     r0, r0, #PJ4B_CLEAN_LINE
 434         orr     r0, r0, #PJ4B_INTER_PARITY
 435         bic     r0, r0, #PJ4B_STATIC_BP
 436         mcr     p15, 1, r0, c15, c1, 1
 437
 438         /* Auxiliary Debug Modes Control 2 Register */
 439         mrc     p15, 1, r0, c15, c1, 2
 440         bic     r0, r0, #PJ4B_FAST_LDR
 441         orr     r0, r0, #PJ4B_AUX_DBG_CTRL2
 442         mcr     p15, 1, r0, c15, c1, 2
 443
 444         /* Auxiliary Functional Modes Control Register 0 */
 445         mrc     p15, 1, r0, c15, c2, 0
 446 #ifdef CONFIG_SMP
 447         orr     r0, r0, #PJ4B_SMP_CFB
 448 #endif
 449         orr     r0, r0, #PJ4B_L1_PAR_CHK
 450         orr     r0, r0, #PJ4B_BROADCAST_CACHE
 451         mcr     p15, 1, r0, c15, c2, 0
 452
 453         /* Auxiliary Debug Modes Control 0 Register */
 454         mrc     p15, 1, r0, c15, c1, 0
 455         orr     r0, r0, #PJ4B_WFI_WFE
 456         mcr     p15, 1, r0, c15, c1, 0
 457
 458 #endif /* CONFIG_CPU_PJ4B */
 459
 460 __v7_setup:
 461         adr     r0, __v7_setup_stack_ptr
 462         ldr     r12, [r0]
 463         add     r12, r12, r0                    @ the local stack
 464         stmia   r12, {r1-r6, lr}                @ v7_invalidate_l1 touches r0-r6
 465         bl      v7_invalidate_l1
 466         ldmia   r12, {r1-r6, lr}
 467
 468 __v7_setup_cont:
 469         and     r0, r9, #0xff000000             @ ARM?
 470         teq     r0, #0x41000000
 471         bne     __errata_finish
 472         and     r3, r9, #0x00f00000             @ variant
 473         and     r6, r9, #0x0000000f             @ revision
 474         orr     r6, r6, r3, lsr #20-4           @ combine variant and revision
 475         ubfx    r0, r9, #4, #12                 @ primary part number
 476
 477         /* Cortex-A8 Errata */
 478         ldr     r10, =0x00000c08                @ Cortex-A8 primary part number
 479         teq     r0, r10
 480         beq     __ca8_errata
 481
 482         /* Cortex-A9 Errata */
 483         ldr     r10, =0x00000c09                @ Cortex-A9 primary part number
 484         teq     r0, r10
 485         beq     __ca9_errata
 486
 487         /* Cortex-A12 Errata */
 488         ldr     r10, =0x00000c0d                @ Cortex-A12 primary part number
 489         teq     r0, r10
 490         beq     __ca12_errata
 491
 492         /* Cortex-A17 Errata */
 493         ldr     r10, =0x00000c0e                @ Cortex-A17 primary part number
 494         teq     r0, r10
 495         beq     __ca17_errata
 496
 497         /* Cortex-A15 Errata */
 498         ldr     r10, =0x00000c0f                @ Cortex-A15 primary part number
 499         teq     r0, r10
 500         beq     __ca15_errata
 501
 502 __errata_finish:
 503         mov     r10, #0
 504         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
 505 #ifdef CONFIG_MMU
 506         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
 507         v7_ttb_setup r10, r4, r5, r8, r3        @ TTBCR, TTBRx setup
 508         ldr     r3, =PRRR                       @ PRRR
 509         ldr     r6, =NMRR                       @ NMRR
 510         mcr     p15, 0, r3, c10, c2, 0          @ write PRRR
 511         mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
 512 #endif
 513         dsb                                     @ Complete invalidations
 514 #ifndef CONFIG_ARM_THUMBEE
 515         mrc     p15, 0, r0, c0, c1, 0           @ read ID_PFR0 for ThumbEE
 516         and     r0, r0, #(0xf << 12)            @ ThumbEE enabled field
 517         teq     r0, #(1 << 12)                  @ check if ThumbEE is present
 518         bne     1f
 519         mov     r3, #0
 520         mcr     p14, 6, r3, c1, c0, 0           @ Initialize TEEHBR to 0
 521         mrc     p14, 6, r0, c0, c0, 0           @ load TEECR
 522         orr     r0, r0, #1                      @ set the 1st bit in order to
 523         mcr     p14, 6, r0, c0, c0, 0           @ stop userspace TEEHBR access
 524 1:
 525 #endif
 526         adr     r3, v7_crval
 527         ldmia   r3, {r3, r6}
 528  ARM_BE8(orr    r6, r6, #1 << 25)               @ big-endian page tables
 529 #ifdef CONFIG_SWP_EMULATE
 530         orr     r3, r3, #(1 << 10)              @ set SW bit in "clear"
 531         bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
 532 #endif
 533         mrc     p15, 0, r0, c1, c0, 0           @ read control register
 534         bic     r0, r0, r3                      @ clear bits them
 535         orr     r0, r0, r6                      @ set them
 536  THUMB( orr     r0, r0, #1 << 30        )       @ Thumb exceptions
 537         ret     lr                              @ return to head.S:__ret
 538
 539         .align  2
 540 __v7_setup_stack_ptr:
 541         .word   PHYS_RELATIVE(__v7_setup_stack, .)
 542 ENDPROC(__v7_setup)
 543
 544         .bss
 545         .align  2
 546 __v7_setup_stack:
 547         .space  4 * 7                           @ 7 registers
 548
 549         __INITDATA
 550
 551         .weak cpu_v7_bugs_init
 552
 553         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
 554         define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
 555
 556 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 557         @ generic v7 bpiall on context switch
 558         globl_equ       cpu_v7_bpiall_proc_init,        cpu_v7_proc_init
 559         globl_equ       cpu_v7_bpiall_proc_fin,         cpu_v7_proc_fin
 560         globl_equ       cpu_v7_bpiall_reset,            cpu_v7_reset
 561         globl_equ       cpu_v7_bpiall_do_idle,          cpu_v7_do_idle
 562         globl_equ       cpu_v7_bpiall_dcache_clean_area, cpu_v7_dcache_clean_area
 563         globl_equ       cpu_v7_bpiall_set_pte_ext,      cpu_v7_set_pte_ext
 564         globl_equ       cpu_v7_bpiall_suspend_size,     cpu_v7_suspend_size
 565 #ifdef CONFIG_ARM_CPU_SUSPEND
 566         globl_equ       cpu_v7_bpiall_do_suspend,       cpu_v7_do_suspend
 567         globl_equ       cpu_v7_bpiall_do_resume,        cpu_v7_do_resume
 568 #endif
 569         define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
 570
 571 #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_bpiall_processor_functions
 572 #else
 573 #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_processor_functions
 574 #endif
 575
 576 #ifndef CONFIG_ARM_LPAE
 577         @ Cortex-A8 - always needs bpiall switch_mm implementation
 578         globl_equ       cpu_ca8_proc_init,      cpu_v7_proc_init
 579         globl_equ       cpu_ca8_proc_fin,       cpu_v7_proc_fin
 580         globl_equ       cpu_ca8_reset,          cpu_v7_reset
 581         globl_equ       cpu_ca8_do_idle,        cpu_v7_do_idle
 582         globl_equ       cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
 583         globl_equ       cpu_ca8_set_pte_ext,    cpu_v7_set_pte_ext
 584         globl_equ       cpu_ca8_switch_mm,      cpu_v7_bpiall_switch_mm
 585         globl_equ       cpu_ca8_suspend_size,   cpu_v7_suspend_size
 586 #ifdef CONFIG_ARM_CPU_SUSPEND
 587         globl_equ       cpu_ca8_do_suspend,     cpu_v7_do_suspend
 588         globl_equ       cpu_ca8_do_resume,      cpu_v7_do_resume
 589 #endif
 590         define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca8_ibe
 591
 592         @ Cortex-A9 - needs more registers preserved across suspend/resume
 593         @ and bpiall switch_mm for hardening
 594         globl_equ       cpu_ca9mp_proc_init,    cpu_v7_proc_init
 595         globl_equ       cpu_ca9mp_proc_fin,     cpu_v7_proc_fin
 596         globl_equ       cpu_ca9mp_reset,        cpu_v7_reset
 597         globl_equ       cpu_ca9mp_do_idle,      cpu_v7_do_idle
 598         globl_equ       cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
 599 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 600         globl_equ       cpu_ca9mp_switch_mm,    cpu_v7_bpiall_switch_mm
 601 #else
 602         globl_equ       cpu_ca9mp_switch_mm,    cpu_v7_switch_mm
 603 #endif
 604         globl_equ       cpu_ca9mp_set_pte_ext,  cpu_v7_set_pte_ext
 605         define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
 606 #endif
 607
 608         @ Cortex-A15 - needs iciallu switch_mm for hardening
 609         globl_equ       cpu_ca15_proc_init,     cpu_v7_proc_init
 610         globl_equ       cpu_ca15_proc_fin,      cpu_v7_proc_fin
 611         globl_equ       cpu_ca15_reset,         cpu_v7_reset
 612         globl_equ       cpu_ca15_do_idle,       cpu_v7_do_idle
 613         globl_equ       cpu_ca15_dcache_clean_area, cpu_v7_dcache_clean_area
 614 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 615         globl_equ       cpu_ca15_switch_mm,     cpu_v7_iciallu_switch_mm
 616 #else
 617         globl_equ       cpu_ca15_switch_mm,     cpu_v7_switch_mm
 618 #endif
 619         globl_equ       cpu_ca15_set_pte_ext,   cpu_v7_set_pte_ext
 620         globl_equ       cpu_ca15_suspend_size,  cpu_v7_suspend_size
 621         globl_equ       cpu_ca15_do_suspend,    cpu_v7_do_suspend
 622         globl_equ       cpu_ca15_do_resume,     cpu_v7_do_resume
 623         define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca15_ibe
 624 #ifdef CONFIG_CPU_PJ4B
 625         define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
 626 #endif
 627
 628         .section ".rodata"
 629
 630         string  cpu_arch_name, "armv7"
 631         string  cpu_elf_name, "v7"
 632         .align
 633
 634         .section ".proc.info.init", #alloc
 635
 636         /*
 637          * Standard v7 proc info content
 638          */
 639 .macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
 640         ALT_SMP(.long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 641                         PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
 642         ALT_UP(.long    PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 643                         PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
 644         .long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
 645                 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
 646         initfn  \initfunc, \name
 647         .long   cpu_arch_name
 648         .long   cpu_elf_name
 649         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
 650                 HWCAP_EDSP | HWCAP_TLS | \hwcaps
 651         .long   cpu_v7_name
 652         .long   \proc_fns
 653         .long   v7wbi_tlb_fns
 654         .long   v6_user_fns
 655         .long   v7_cache_fns
 656 .endm
 657
 658 #ifndef CONFIG_ARM_LPAE
 659         /*
 660          * ARM Ltd. Cortex A5 processor.
 661          */
 662         .type   __v7_ca5mp_proc_info, #object
 663 __v7_ca5mp_proc_info:
 664         .long   0x410fc050
 665         .long   0xff0ffff0
 666         __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
 667         .size   __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
 668
 669         /*
 670          * ARM Ltd. Cortex A9 processor.
 671          */
 672         .type   __v7_ca9mp_proc_info, #object
 673 __v7_ca9mp_proc_info:
 674         .long   0x410fc090
 675         .long   0xff0ffff0
 676         __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
 677         .size   __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
 678
 679         /*
 680          * ARM Ltd. Cortex A8 processor.
 681          */
 682         .type   __v7_ca8_proc_info, #object
 683 __v7_ca8_proc_info:
 684         .long   0x410fc080
 685         .long   0xff0ffff0
 686         __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
 687         .size   __v7_ca8_proc_info, . - __v7_ca8_proc_info
 688
 689 #endif  /* CONFIG_ARM_LPAE */
 690
 691         /*
 692          * Marvell PJ4B processor.
 693          */
 694 #ifdef CONFIG_CPU_PJ4B
 695         .type   __v7_pj4b_proc_info, #object
 696 __v7_pj4b_proc_info:
 697         .long   0x560f5800
 698         .long   0xff0fff00
 699         __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
 700         .size   __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
 701 #endif
 702
 703         /*
 704          * ARM Ltd. Cortex R7 processor.
 705          */
 706         .type   __v7_cr7mp_proc_info, #object
 707 __v7_cr7mp_proc_info:
 708         .long   0x410fc170
 709         .long   0xff0ffff0
 710         __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
 711         .size   __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
 712
 713         /*
 714          * ARM Ltd. Cortex A7 processor.
 715          */
 716         .type   __v7_ca7mp_proc_info, #object
 717 __v7_ca7mp_proc_info:
 718         .long   0x410fc070
 719         .long   0xff0ffff0
 720         __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
 721         .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
 722
 723         /*
 724          * ARM Ltd. Cortex A12 processor.
 725          */
 726         .type   __v7_ca12mp_proc_info, #object
 727 __v7_ca12mp_proc_info:
 728         .long   0x410fc0d0
 729         .long   0xff0ffff0
 730         __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
 731         .size   __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
 732
 733         /*
 734          * ARM Ltd. Cortex A15 processor.
 735          */
 736         .type   __v7_ca15mp_proc_info, #object
 737 __v7_ca15mp_proc_info:
 738         .long   0x410fc0f0
 739         .long   0xff0ffff0
 740         __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup, proc_fns = ca15_processor_functions
 741         .size   __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
 742
 743         /*
 744          * Broadcom Corporation Brahma-B15 processor.
 745          */
 746         .type   __v7_b15mp_proc_info, #object
 747 __v7_b15mp_proc_info:
 748         .long   0x420f00f0
 749         .long   0xff0ffff0
 750         __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup, proc_fns = ca15_processor_functions
 751         .size   __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
 752
 753         /*
 754          * ARM Ltd. Cortex A17 processor.
 755          */
 756         .type   __v7_ca17mp_proc_info, #object
 757 __v7_ca17mp_proc_info:
 758         .long   0x410fc0e0
 759         .long   0xff0ffff0
 760         __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
 761         .size   __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
 762
 763         /* ARM Ltd. Cortex A73 processor */
 764         .type   __v7_ca73_proc_info, #object
 765 __v7_ca73_proc_info:
 766         .long   0x410fd090
 767         .long   0xff0ffff0
 768         __v7_proc __v7_ca73_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
 769         .size   __v7_ca73_proc_info, . - __v7_ca73_proc_info
 770
 771         /* ARM Ltd. Cortex A75 processor */
 772         .type   __v7_ca75_proc_info, #object
 773 __v7_ca75_proc_info:
 774         .long   0x410fd0a0
 775         .long   0xff0ffff0
 776         __v7_proc __v7_ca75_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
 777         .size   __v7_ca75_proc_info, . - __v7_ca75_proc_info
 778
 779         /*
 780          * Qualcomm Inc. Krait processors.
 781          */
 782         .type   __krait_proc_info, #object
 783 __krait_proc_info:
 784         .long   0x510f0400              @ Required ID value
 785         .long   0xff0ffc00              @ Mask for ID
 786         /*
 787          * Some Krait processors don't indicate support for SDIV and UDIV
 788          * instructions in the ARM instruction set, even though they actually
 789          * do support them. They also don't indicate support for fused multiply
 790          * instructions even though they actually do support them.
 791          */
 792         __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
 793         .size   __krait_proc_info, . - __krait_proc_info
 794
 795         /*
 796          * Match any ARMv7 processor core.
 797          */
 798         .type   __v7_proc_info, #object
 799 __v7_proc_info:
 800         .long   0x000f0000              @ Required ID value
 801         .long   0x000f0000              @ Mask for ID
 802         __v7_proc __v7_proc_info, __v7_setup
 803         .size   __v7_proc_info, . - __v7_proc_info