1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mm/mmu.c
5 * Copyright (C) 1995-2005 Russell King
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/errno.h>
10 #include <linux/init.h>
11 #include <linux/mman.h>
12 #include <linux/nodemask.h>
13 #include <linux/memblock.h>
15 #include <linux/vmalloc.h>
16 #include <linux/sizes.h>
19 #include <asm/cputype.h>
20 #include <asm/sections.h>
21 #include <asm/cachetype.h>
22 #include <asm/fixmap.h>
23 #include <asm/sections.h>
24 #include <asm/setup.h>
25 #include <asm/smp_plat.h>
27 #include <asm/highmem.h>
28 #include <asm/system_info.h>
29 #include <asm/traps.h>
30 #include <asm/procinfo.h>
31 #include <asm/memory.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/pci.h>
36 #include <asm/fixmap.h>
42 extern unsigned long __atags_pointer;
45 * empty_zero_page is a special page that is used for
46 * zero-initialized data and COW.
48 struct page *empty_zero_page;
49 EXPORT_SYMBOL(empty_zero_page);
52 * The pmd table for the upper-most set of pages.
56 pmdval_t user_pmd_table = _PAGE_USER_TABLE;
58 #define CPOLICY_UNCACHED 0
59 #define CPOLICY_BUFFERED 1
60 #define CPOLICY_WRITETHROUGH 2
61 #define CPOLICY_WRITEBACK 3
62 #define CPOLICY_WRITEALLOC 4
64 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
65 static unsigned int ecc_mask __initdata = 0;
67 pgprot_t pgprot_kernel;
68 pgprot_t pgprot_hyp_device;
70 pgprot_t pgprot_s2_device;
72 EXPORT_SYMBOL(pgprot_user);
73 EXPORT_SYMBOL(pgprot_kernel);
76 const char policy[16];
83 #ifdef CONFIG_ARM_LPAE
84 #define s2_policy(policy) policy
86 #define s2_policy(policy) 0
89 unsigned long kimage_voffset __ro_after_init;
91 static struct cachepolicy cache_policies[] __initdata = {
95 .pmd = PMD_SECT_UNCACHED,
96 .pte = L_PTE_MT_UNCACHED,
97 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
101 .pmd = PMD_SECT_BUFFERED,
102 .pte = L_PTE_MT_BUFFERABLE,
103 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
105 .policy = "writethrough",
108 .pte = L_PTE_MT_WRITETHROUGH,
109 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
111 .policy = "writeback",
114 .pte = L_PTE_MT_WRITEBACK,
115 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
117 .policy = "writealloc",
119 .pmd = PMD_SECT_WBWA,
120 .pte = L_PTE_MT_WRITEALLOC,
121 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
125 #ifdef CONFIG_CPU_CP15
126 static unsigned long initial_pmd_value __initdata = 0;
129 * Initialise the cache_policy variable with the initial state specified
130 * via the "pmd" value. This is used to ensure that on ARMv6 and later,
131 * the C code sets the page tables up with the same policy as the head
132 * assembly code, which avoids an illegal state where the TLBs can get
133 * confused. See comments in early_cachepolicy() for more information.
135 void __init init_default_cache_policy(unsigned long pmd)
139 initial_pmd_value = pmd;
141 pmd &= PMD_SECT_CACHE_MASK;
143 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
144 if (cache_policies[i].pmd == pmd) {
149 if (i == ARRAY_SIZE(cache_policies))
150 pr_err("ERROR: could not find cache policy\n");
154 * These are useful for identifying cache coherency problems by allowing
155 * the cache or the cache and writebuffer to be turned off. (Note: the
156 * write buffer should not be on and the cache off).
158 static int __init early_cachepolicy(char *p)
160 int i, selected = -1;
162 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
163 int len = strlen(cache_policies[i].policy);
165 if (memcmp(p, cache_policies[i].policy, len) == 0) {
172 pr_err("ERROR: unknown or unsupported cache policy\n");
175 * This restriction is partly to do with the way we boot; it is
176 * unpredictable to have memory mapped using two different sets of
177 * memory attributes (shared, type, and cache attribs). We can not
178 * change these attributes once the initial assembly has setup the
181 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
182 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
183 cache_policies[cachepolicy].policy);
187 if (selected != cachepolicy) {
188 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
189 cachepolicy = selected;
195 early_param("cachepolicy", early_cachepolicy);
197 static int __init early_nocache(char *__unused)
199 char *p = "buffered";
200 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
201 early_cachepolicy(p);
204 early_param("nocache", early_nocache);
206 static int __init early_nowrite(char *__unused)
208 char *p = "uncached";
209 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
210 early_cachepolicy(p);
213 early_param("nowb", early_nowrite);
215 #ifndef CONFIG_ARM_LPAE
216 static int __init early_ecc(char *p)
218 if (memcmp(p, "on", 2) == 0)
219 ecc_mask = PMD_PROTECTION;
220 else if (memcmp(p, "off", 3) == 0)
224 early_param("ecc", early_ecc);
227 #else /* ifdef CONFIG_CPU_CP15 */
229 static int __init early_cachepolicy(char *p)
231 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
234 early_param("cachepolicy", early_cachepolicy);
236 static int __init noalign_setup(char *__unused)
238 pr_warn("noalign kernel parameter not supported without cp15\n");
241 __setup("noalign", noalign_setup);
243 #endif /* ifdef CONFIG_CPU_CP15 / else */
245 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
246 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
247 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
249 static struct mem_type mem_types[] __ro_after_init = {
250 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
251 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
253 .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
254 s2_policy(L_PTE_S2_MT_DEV_SHARED) |
256 .prot_l1 = PMD_TYPE_TABLE,
257 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
260 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
261 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
262 .prot_l1 = PMD_TYPE_TABLE,
263 .prot_sect = PROT_SECT_DEVICE,
266 [MT_DEVICE_CACHED] = { /* ioremap_cached */
267 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
268 .prot_l1 = PMD_TYPE_TABLE,
269 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
272 [MT_DEVICE_WC] = { /* ioremap_wc */
273 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
274 .prot_l1 = PMD_TYPE_TABLE,
275 .prot_sect = PROT_SECT_DEVICE,
279 .prot_pte = PROT_PTE_DEVICE,
280 .prot_l1 = PMD_TYPE_TABLE,
281 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
285 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
286 .domain = DOMAIN_KERNEL,
288 #ifndef CONFIG_ARM_LPAE
290 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
291 .domain = DOMAIN_KERNEL,
295 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
297 .prot_l1 = PMD_TYPE_TABLE,
298 .domain = DOMAIN_VECTORS,
300 [MT_HIGH_VECTORS] = {
301 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
302 L_PTE_USER | L_PTE_RDONLY,
303 .prot_l1 = PMD_TYPE_TABLE,
304 .domain = DOMAIN_VECTORS,
307 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
308 .prot_l1 = PMD_TYPE_TABLE,
309 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
310 .domain = DOMAIN_KERNEL,
313 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
315 .prot_l1 = PMD_TYPE_TABLE,
316 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
317 .domain = DOMAIN_KERNEL,
320 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
321 L_PTE_XN | L_PTE_RDONLY,
322 .prot_l1 = PMD_TYPE_TABLE,
323 #ifdef CONFIG_ARM_LPAE
324 .prot_sect = PMD_TYPE_SECT | L_PMD_SECT_RDONLY | PMD_SECT_AP2,
326 .prot_sect = PMD_TYPE_SECT,
328 .domain = DOMAIN_KERNEL,
331 .prot_sect = PMD_TYPE_SECT,
332 .domain = DOMAIN_KERNEL,
334 [MT_MEMORY_RWX_NONCACHED] = {
335 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
337 .prot_l1 = PMD_TYPE_TABLE,
338 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
339 .domain = DOMAIN_KERNEL,
341 [MT_MEMORY_RW_DTCM] = {
342 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
344 .prot_l1 = PMD_TYPE_TABLE,
345 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
346 .domain = DOMAIN_KERNEL,
348 [MT_MEMORY_RWX_ITCM] = {
349 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
350 .prot_l1 = PMD_TYPE_TABLE,
351 .domain = DOMAIN_KERNEL,
353 [MT_MEMORY_RW_SO] = {
354 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
355 L_PTE_MT_UNCACHED | L_PTE_XN,
356 .prot_l1 = PMD_TYPE_TABLE,
357 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
358 PMD_SECT_UNCACHED | PMD_SECT_XN,
359 .domain = DOMAIN_KERNEL,
361 [MT_MEMORY_DMA_READY] = {
362 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
364 .prot_l1 = PMD_TYPE_TABLE,
365 .domain = DOMAIN_KERNEL,
369 const struct mem_type *get_mem_type(unsigned int type)
371 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
373 EXPORT_SYMBOL(get_mem_type);
375 static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
377 static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
378 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
380 static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
382 return &bm_pte[pte_index(addr)];
385 static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
387 return pte_offset_kernel(dir, addr);
390 static inline pmd_t * __init fixmap_pmd(unsigned long addr)
392 pgd_t *pgd = pgd_offset_k(addr);
393 pud_t *pud = pud_offset(pgd, addr);
394 pmd_t *pmd = pmd_offset(pud, addr);
399 void __init early_fixmap_init(void)
404 * The early fixmap range spans multiple pmds, for which
405 * we are not prepared:
407 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
408 != FIXADDR_TOP >> PMD_SHIFT);
410 pmd = fixmap_pmd(FIXADDR_TOP);
411 pmd_populate_kernel(&init_mm, pmd, bm_pte);
413 pte_offset_fixmap = pte_offset_early_fixmap;
417 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
418 * As a result, this can only be called with preemption disabled, as under
421 void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
423 unsigned long vaddr = __fix_to_virt(idx);
424 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
426 /* Make sure fixmap region does not exceed available allocation. */
427 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
429 BUG_ON(idx >= __end_of_fixed_addresses);
431 /* We support only device mappings before pgprot_kernel is set. */
432 if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
433 pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0))
436 if (pgprot_val(prot))
437 set_pte_at(NULL, vaddr, pte,
438 pfn_pte(phys >> PAGE_SHIFT, prot));
440 pte_clear(NULL, vaddr, pte);
441 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
445 * Adjust the PMD section entries according to the CPU in use.
447 static void __init build_mem_type_table(void)
449 struct cachepolicy *cp;
450 unsigned int cr = get_cr();
451 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
452 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
453 int cpu_arch = cpu_architecture();
456 if (cpu_arch < CPU_ARCH_ARMv6) {
457 #if defined(CONFIG_CPU_DCACHE_DISABLE)
458 if (cachepolicy > CPOLICY_BUFFERED)
459 cachepolicy = CPOLICY_BUFFERED;
460 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
461 if (cachepolicy > CPOLICY_WRITETHROUGH)
462 cachepolicy = CPOLICY_WRITETHROUGH;
465 if (cpu_arch < CPU_ARCH_ARMv5) {
466 if (cachepolicy >= CPOLICY_WRITEALLOC)
467 cachepolicy = CPOLICY_WRITEBACK;
472 if (cachepolicy != CPOLICY_WRITEALLOC) {
473 pr_warn("Forcing write-allocate cache policy for SMP\n");
474 cachepolicy = CPOLICY_WRITEALLOC;
476 if (!(initial_pmd_value & PMD_SECT_S)) {
477 pr_warn("Forcing shared mappings for SMP\n");
478 initial_pmd_value |= PMD_SECT_S;
483 * Strip out features not present on earlier architectures.
484 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
485 * without extended page tables don't have the 'Shared' bit.
487 if (cpu_arch < CPU_ARCH_ARMv5)
488 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
489 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
490 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
491 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
492 mem_types[i].prot_sect &= ~PMD_SECT_S;
495 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
496 * "update-able on write" bit on ARM610). However, Xscale and
497 * Xscale3 require this bit to be cleared.
499 if (cpu_is_xscale_family()) {
500 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
501 mem_types[i].prot_sect &= ~PMD_BIT4;
502 mem_types[i].prot_l1 &= ~PMD_BIT4;
504 } else if (cpu_arch < CPU_ARCH_ARMv6) {
505 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
506 if (mem_types[i].prot_l1)
507 mem_types[i].prot_l1 |= PMD_BIT4;
508 if (mem_types[i].prot_sect)
509 mem_types[i].prot_sect |= PMD_BIT4;
514 * Mark the device areas according to the CPU/architecture.
516 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
517 if (!cpu_is_xsc3()) {
519 * Mark device regions on ARMv6+ as execute-never
520 * to prevent speculative instruction fetches.
522 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
523 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
524 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
525 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
527 /* Also setup NX memory mapping */
528 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
529 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_XN;
531 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
533 * For ARMv7 with TEX remapping,
534 * - shared device is SXCB=1100
535 * - nonshared device is SXCB=0100
536 * - write combine device mem is SXCB=0001
537 * (Uncached Normal memory)
539 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
540 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
541 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
542 } else if (cpu_is_xsc3()) {
545 * - shared device is TEXCB=00101
546 * - nonshared device is TEXCB=01000
547 * - write combine device mem is TEXCB=00100
548 * (Inner/Outer Uncacheable in xsc3 parlance)
550 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
551 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
552 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
555 * For ARMv6 and ARMv7 without TEX remapping,
556 * - shared device is TEXCB=00001
557 * - nonshared device is TEXCB=01000
558 * - write combine device mem is TEXCB=00100
559 * (Uncached Normal in ARMv6 parlance).
561 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
562 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
563 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
567 * On others, write combining is "Uncached/Buffered"
569 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
573 * Now deal with the memory-type mappings
575 cp = &cache_policies[cachepolicy];
576 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
577 s2_pgprot = cp->pte_s2;
578 hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
579 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
581 #ifndef CONFIG_ARM_LPAE
583 * We don't use domains on ARMv6 (since this causes problems with
584 * v6/v7 kernels), so we must use a separate memory type for user
585 * r/o, kernel r/w to map the vectors page.
587 if (cpu_arch == CPU_ARCH_ARMv6)
588 vecs_pgprot |= L_PTE_MT_VECTORS;
591 * Check is it with support for the PXN bit
592 * in the Short-descriptor translation table format descriptors.
594 if (cpu_arch == CPU_ARCH_ARMv7 &&
595 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
596 user_pmd_table |= PMD_PXNTABLE;
601 * ARMv6 and above have extended page tables.
603 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
604 #ifndef CONFIG_ARM_LPAE
606 * Mark cache clean areas and XIP ROM read only
607 * from SVC mode and no access from userspace.
609 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
610 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
611 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
612 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
616 * If the initial page tables were created with the S bit
617 * set, then we need to do the same here for the same
618 * reasons given in early_cachepolicy().
620 if (initial_pmd_value & PMD_SECT_S) {
621 user_pgprot |= L_PTE_SHARED;
622 kern_pgprot |= L_PTE_SHARED;
623 vecs_pgprot |= L_PTE_SHARED;
624 s2_pgprot |= L_PTE_SHARED;
625 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
626 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
627 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
628 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
629 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
630 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
631 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
632 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
633 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_S;
634 mem_types[MT_MEMORY_RO].prot_pte |= L_PTE_SHARED;
635 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
636 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
637 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
642 * Non-cacheable Normal - intended for memory areas that must
643 * not cause dirty cache line writebacks when used
645 if (cpu_arch >= CPU_ARCH_ARMv6) {
646 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
647 /* Non-cacheable Normal is XCB = 001 */
648 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
651 /* For both ARMv6 and non-TEX-remapping ARMv7 */
652 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
656 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
659 #ifdef CONFIG_ARM_LPAE
661 * Do not generate access flag faults for the kernel mappings.
663 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
664 mem_types[i].prot_pte |= PTE_EXT_AF;
665 if (mem_types[i].prot_sect)
666 mem_types[i].prot_sect |= PMD_SECT_AF;
668 kern_pgprot |= PTE_EXT_AF;
669 vecs_pgprot |= PTE_EXT_AF;
672 * Set PXN for user mappings
674 user_pgprot |= PTE_EXT_PXN;
677 for (i = 0; i < 16; i++) {
678 pteval_t v = pgprot_val(protection_map[i]);
679 protection_map[i] = __pgprot(v | user_pgprot);
682 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
683 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
685 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
686 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
687 L_PTE_DIRTY | kern_pgprot);
688 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
689 pgprot_s2_device = __pgprot(s2_device_pgprot);
690 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
692 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
693 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
694 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
695 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
696 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
697 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
698 mem_types[MT_MEMORY_RO].prot_sect |= ecc_mask | cp->pmd;
699 mem_types[MT_MEMORY_RO].prot_pte |= kern_pgprot;
700 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
701 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
702 mem_types[MT_ROM].prot_sect |= cp->pmd;
706 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
710 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
713 pr_info("Memory policy: %sData cache %s\n",
714 ecc_mask ? "ECC enabled, " : "", cp->policy);
716 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
717 struct mem_type *t = &mem_types[i];
719 t->prot_l1 |= PMD_DOMAIN(t->domain);
721 t->prot_sect |= PMD_DOMAIN(t->domain);
725 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
726 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
727 unsigned long size, pgprot_t vma_prot)
730 return pgprot_noncached(vma_prot);
731 else if (file->f_flags & O_SYNC)
732 return pgprot_writecombine(vma_prot);
735 EXPORT_SYMBOL(phys_mem_access_prot);
738 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
740 static void __init *early_alloc(unsigned long sz)
742 void *ptr = memblock_alloc(sz, sz);
745 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
751 static void *__init late_alloc(unsigned long sz)
753 void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz));
755 if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr)))
760 static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
762 void *(*alloc)(unsigned long sz))
764 if (pmd_none(*pmd)) {
765 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
766 __pmd_populate(pmd, __pa(pte), prot);
768 BUG_ON(pmd_bad(*pmd));
769 return pte_offset_kernel(pmd, addr);
772 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
775 return arm_pte_alloc(pmd, addr, prot, early_alloc);
778 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
779 unsigned long end, unsigned long pfn,
780 const struct mem_type *type,
781 void *(*alloc)(unsigned long sz),
784 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
786 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
787 ng ? PTE_EXT_NG : 0);
789 } while (pte++, addr += PAGE_SIZE, addr != end);
792 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
793 unsigned long end, phys_addr_t phys,
794 const struct mem_type *type, bool ng)
798 #ifndef CONFIG_ARM_LPAE
800 * In classic MMU format, puds and pmds are folded in to
801 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
802 * group of L1 entries making up one logical pointer to
803 * an L2 table (2MB), where as PMDs refer to the individual
804 * L1 entries (1MB). Hence increment to get the correct
805 * offset for odd 1MB sections.
806 * (See arch/arm/include/asm/pgtable-2level.h)
808 if (addr & SECTION_SIZE)
812 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
813 phys += SECTION_SIZE;
814 } while (pmd++, addr += SECTION_SIZE, addr != end);
819 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
820 unsigned long end, phys_addr_t phys,
821 const struct mem_type *type,
822 void *(*alloc)(unsigned long sz), bool ng)
824 pmd_t *pmd = pmd_offset(pud, addr);
829 * With LPAE, we must loop over to map
830 * all the pmds for the given range.
832 next = pmd_addr_end(addr, end);
835 * Try a section mapping - addr, next and phys must all be
836 * aligned to a section boundary.
838 if (type->prot_sect &&
839 ((addr | next | phys) & ~SECTION_MASK) == 0) {
840 __map_init_section(pmd, addr, next, phys, type, ng);
842 alloc_init_pte(pmd, addr, next,
843 __phys_to_pfn(phys), type, alloc, ng);
848 } while (pmd++, addr = next, addr != end);
851 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
852 unsigned long end, phys_addr_t phys,
853 const struct mem_type *type,
854 void *(*alloc)(unsigned long sz), bool ng)
856 pud_t *pud = pud_offset(pgd, addr);
860 next = pud_addr_end(addr, end);
861 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
863 } while (pud++, addr = next, addr != end);
866 #ifndef CONFIG_ARM_LPAE
867 static void __init create_36bit_mapping(struct mm_struct *mm,
869 const struct mem_type *type,
872 unsigned long addr, length, end;
877 phys = __pfn_to_phys(md->pfn);
878 length = PAGE_ALIGN(md->length);
880 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
881 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
882 (long long)__pfn_to_phys((u64)md->pfn), addr);
886 /* N.B. ARMv6 supersections are only defined to work with domain 0.
887 * Since domain assignments can in fact be arbitrary, the
888 * 'domain == 0' check below is required to insure that ARMv6
889 * supersections are only allocated for domain 0 regardless
890 * of the actual domain assignments in use.
893 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
894 (long long)__pfn_to_phys((u64)md->pfn), addr);
898 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
899 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
900 (long long)__pfn_to_phys((u64)md->pfn), addr);
905 * Shift bits [35:32] of address into bits [23:20] of PMD
908 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
910 pgd = pgd_offset(mm, addr);
913 pud_t *pud = pud_offset(pgd, addr);
914 pmd_t *pmd = pmd_offset(pud, addr);
917 for (i = 0; i < 16; i++)
918 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
919 (ng ? PMD_SECT_nG : 0));
921 addr += SUPERSECTION_SIZE;
922 phys += SUPERSECTION_SIZE;
923 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
924 } while (addr != end);
926 #endif /* !CONFIG_ARM_LPAE */
928 static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
929 void *(*alloc)(unsigned long sz),
932 unsigned long addr, length, end;
934 const struct mem_type *type;
937 type = &mem_types[md->type];
939 #ifndef CONFIG_ARM_LPAE
941 * Catch 36-bit addresses
943 if (md->pfn >= 0x100000) {
944 create_36bit_mapping(mm, md, type, ng);
949 addr = md->virtual & PAGE_MASK;
950 phys = __pfn_to_phys(md->pfn);
951 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
953 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
954 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
955 (long long)__pfn_to_phys(md->pfn), addr);
959 pgd = pgd_offset(mm, addr);
962 unsigned long next = pgd_addr_end(addr, end);
964 alloc_init_pud(pgd, addr, next, phys, type, alloc, ng);
968 } while (pgd++, addr != end);
972 * Create the page directory entries and any necessary
973 * page tables for the mapping specified by `md'. We
974 * are able to cope here with varying sizes and address
975 * offsets, and we take full advantage of sections and
978 static void __init create_mapping(struct map_desc *md)
980 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
981 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
982 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
986 if (md->type == MT_DEVICE &&
987 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
988 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
989 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
990 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
993 __create_mapping(&init_mm, md, early_alloc, false);
996 void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
999 #ifdef CONFIG_ARM_LPAE
1000 pud_t *pud = pud_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
1003 pmd_alloc(mm, pud, 0);
1005 __create_mapping(mm, md, late_alloc, ng);
1009 * Create the architecture specific mappings
1011 void __init iotable_init(struct map_desc *io_desc, int nr)
1013 struct map_desc *md;
1014 struct vm_struct *vm;
1015 struct static_vm *svm;
1020 svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm));
1022 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1023 __func__, sizeof(*svm) * nr, __alignof__(*svm));
1025 for (md = io_desc; nr; md++, nr--) {
1029 vm->addr = (void *)(md->virtual & PAGE_MASK);
1030 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
1031 vm->phys_addr = __pfn_to_phys(md->pfn);
1032 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
1033 vm->flags |= VM_ARM_MTYPE(md->type);
1034 vm->caller = iotable_init;
1035 add_static_vm_early(svm++);
1039 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
1042 struct vm_struct *vm;
1043 struct static_vm *svm;
1045 svm = memblock_alloc(sizeof(*svm), __alignof__(*svm));
1047 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1048 __func__, sizeof(*svm), __alignof__(*svm));
1051 vm->addr = (void *)addr;
1053 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
1054 vm->caller = caller;
1055 add_static_vm_early(svm);
1058 #ifndef CONFIG_ARM_LPAE
1061 * The Linux PMD is made of two consecutive section entries covering 2MB
1062 * (see definition in include/asm/pgtable-2level.h). However a call to
1063 * create_mapping() may optimize static mappings by using individual
1064 * 1MB section mappings. This leaves the actual PMD potentially half
1065 * initialized if the top or bottom section entry isn't used, leaving it
1066 * open to problems if a subsequent ioremap() or vmalloc() tries to use
1067 * the virtual space left free by that unused section entry.
1069 * Let's avoid the issue by inserting dummy vm entries covering the unused
1070 * PMD halves once the static mappings are in place.
1073 static void __init pmd_empty_section_gap(unsigned long addr)
1075 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1078 static void __init fill_pmd_gaps(void)
1080 struct static_vm *svm;
1081 struct vm_struct *vm;
1082 unsigned long addr, next = 0;
1085 list_for_each_entry(svm, &static_vmlist, list) {
1087 addr = (unsigned long)vm->addr;
1092 * Check if this vm starts on an odd section boundary.
1093 * If so and the first section entry for this PMD is free
1094 * then we block the corresponding virtual address.
1096 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1097 pmd = pmd_off_k(addr);
1099 pmd_empty_section_gap(addr & PMD_MASK);
1103 * Then check if this vm ends on an odd section boundary.
1104 * If so and the second section entry for this PMD is empty
1105 * then we block the corresponding virtual address.
1108 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1109 pmd = pmd_off_k(addr) + 1;
1111 pmd_empty_section_gap(addr);
1114 /* no need to look at any vm entry until we hit the next PMD */
1115 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1120 #define fill_pmd_gaps() do { } while (0)
1123 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1124 static void __init pci_reserve_io(void)
1126 struct static_vm *svm;
1128 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1132 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1135 #define pci_reserve_io() do { } while (0)
1138 #ifdef CONFIG_DEBUG_LL
1139 void __init debug_ll_io_init(void)
1141 struct map_desc map;
1143 debug_ll_addr(&map.pfn, &map.virtual);
1144 if (!map.pfn || !map.virtual)
1146 map.pfn = __phys_to_pfn(map.pfn);
1147 map.virtual &= PAGE_MASK;
1148 map.length = PAGE_SIZE;
1149 map.type = MT_DEVICE;
1150 iotable_init(&map, 1);
1154 static void * __initdata vmalloc_min =
1155 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1158 * vmalloc=size forces the vmalloc area to be exactly 'size'
1159 * bytes. This can be used to increase (or decrease) the vmalloc
1160 * area - the default is 240m.
1162 static int __init early_vmalloc(char *arg)
1164 unsigned long vmalloc_reserve = memparse(arg, NULL);
1166 if (vmalloc_reserve < SZ_16M) {
1167 vmalloc_reserve = SZ_16M;
1168 pr_warn("vmalloc area too small, limiting to %luMB\n",
1169 vmalloc_reserve >> 20);
1172 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1173 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1174 pr_warn("vmalloc area is too big, limiting to %luMB\n",
1175 vmalloc_reserve >> 20);
1178 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1181 early_param("vmalloc", early_vmalloc);
1183 phys_addr_t arm_lowmem_limit __initdata = 0;
1185 void __init adjust_lowmem_bounds(void)
1187 phys_addr_t memblock_limit = 0;
1189 struct memblock_region *reg;
1190 phys_addr_t lowmem_limit = 0;
1193 * Let's use our own (unoptimized) equivalent of __pa() that is
1194 * not affected by wrap-arounds when sizeof(phys_addr_t) == 4.
1195 * The result is used as the upper bound on physical memory address
1196 * and may itself be outside the valid range for which phys_addr_t
1197 * and therefore __pa() is defined.
1199 vmalloc_limit = (u64)(uintptr_t)vmalloc_min - PAGE_OFFSET + PHYS_OFFSET;
1202 * The first usable region must be PMD aligned. Mark its start
1203 * as MEMBLOCK_NOMAP if it isn't
1205 for_each_memblock(memory, reg) {
1206 if (!memblock_is_nomap(reg)) {
1207 if (!IS_ALIGNED(reg->base, PMD_SIZE)) {
1210 len = round_up(reg->base, PMD_SIZE) - reg->base;
1211 memblock_mark_nomap(reg->base, len);
1217 for_each_memblock(memory, reg) {
1218 phys_addr_t block_start = reg->base;
1219 phys_addr_t block_end = reg->base + reg->size;
1221 if (memblock_is_nomap(reg))
1224 if (reg->base < vmalloc_limit) {
1225 if (block_end > lowmem_limit)
1227 * Compare as u64 to ensure vmalloc_limit does
1228 * not get truncated. block_end should always
1229 * fit in phys_addr_t so there should be no
1230 * issue with assignment.
1232 lowmem_limit = min_t(u64,
1237 * Find the first non-pmd-aligned page, and point
1238 * memblock_limit at it. This relies on rounding the
1239 * limit down to be pmd-aligned, which happens at the
1240 * end of this function.
1242 * With this algorithm, the start or end of almost any
1243 * bank can be non-pmd-aligned. The only exception is
1244 * that the start of the bank 0 must be section-
1245 * aligned, since otherwise memory would need to be
1246 * allocated when mapping the start of bank 0, which
1247 * occurs before any free memory is mapped.
1249 if (!memblock_limit) {
1250 if (!IS_ALIGNED(block_start, PMD_SIZE))
1251 memblock_limit = block_start;
1252 else if (!IS_ALIGNED(block_end, PMD_SIZE))
1253 memblock_limit = lowmem_limit;
1259 arm_lowmem_limit = lowmem_limit;
1261 high_memory = __va(arm_lowmem_limit - 1) + 1;
1263 if (!memblock_limit)
1264 memblock_limit = arm_lowmem_limit;
1267 * Round the memblock limit down to a pmd size. This
1268 * helps to ensure that we will allocate memory from the
1269 * last full pmd, which should be mapped.
1271 memblock_limit = round_down(memblock_limit, PMD_SIZE);
1273 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1274 if (memblock_end_of_DRAM() > arm_lowmem_limit) {
1275 phys_addr_t end = memblock_end_of_DRAM();
1277 pr_notice("Ignoring RAM at %pa-%pa\n",
1278 &memblock_limit, &end);
1279 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1281 memblock_remove(memblock_limit, end - memblock_limit);
1285 memblock_set_current_limit(memblock_limit);
1288 static inline void prepare_page_table(void)
1294 * Clear out all the mappings below the kernel image.
1296 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1297 pmd_clear(pmd_off_k(addr));
1299 #ifdef CONFIG_XIP_KERNEL
1300 /* The XIP kernel is mapped in the module area -- skip over it */
1301 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
1303 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1304 pmd_clear(pmd_off_k(addr));
1307 * Find the end of the first block of lowmem.
1309 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1310 if (end >= arm_lowmem_limit)
1311 end = arm_lowmem_limit;
1314 * Clear out all the kernel space mappings, except for the first
1315 * memory bank, up to the vmalloc region.
1317 for (addr = __phys_to_virt(end);
1318 addr < VMALLOC_START; addr += PMD_SIZE)
1319 pmd_clear(pmd_off_k(addr));
1322 #ifdef CONFIG_ARM_LPAE
1323 /* the first page is reserved for pgd */
1324 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1325 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1327 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1331 * Reserve the special regions of memory
1333 void __init arm_mm_memblock_reserve(void)
1336 * Reserve the page tables. These are already in use,
1337 * and can only be in node 0.
1339 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1341 #ifdef CONFIG_SA1111
1343 * Because of the SA1111 DMA bug, we want to preserve our
1344 * precious DMA-able memory...
1346 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1351 * Set up the device mappings. Since we clear out the page tables for all
1352 * mappings above VMALLOC_START, except early fixmap, we might remove debug
1353 * device mappings. This means earlycon can be used to debug this function
1354 * Any other function or debugging method which may touch any device _will_
1357 static void __init devicemaps_init(const struct machine_desc *mdesc)
1359 struct map_desc map;
1364 * Allocate the vector page early.
1366 vectors = early_alloc(PAGE_SIZE * 2);
1368 early_trap_init(vectors);
1371 * Clear page table except top pmd used by early fixmaps
1373 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1374 pmd_clear(pmd_off_k(addr));
1376 if (__atags_pointer) {
1377 /* create a read-only mapping of the device tree */
1378 map.pfn = __phys_to_pfn(__atags_pointer & SECTION_MASK);
1379 map.virtual = FDT_FIXED_BASE;
1380 map.length = FDT_FIXED_SIZE;
1381 map.type = MT_MEMORY_RO;
1382 create_mapping(&map);
1386 * Map the kernel if it is XIP.
1387 * It is always first in the modulearea.
1389 #ifdef CONFIG_XIP_KERNEL
1390 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1391 map.virtual = MODULES_VADDR;
1392 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1394 create_mapping(&map);
1398 * Map the cache flushing regions.
1401 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1402 map.virtual = FLUSH_BASE;
1404 map.type = MT_CACHECLEAN;
1405 create_mapping(&map);
1407 #ifdef FLUSH_BASE_MINICACHE
1408 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1409 map.virtual = FLUSH_BASE_MINICACHE;
1411 map.type = MT_MINICLEAN;
1412 create_mapping(&map);
1416 * Create a mapping for the machine vectors at the high-vectors
1417 * location (0xffff0000). If we aren't using high-vectors, also
1418 * create a mapping at the low-vectors virtual address.
1420 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1421 map.virtual = 0xffff0000;
1422 map.length = PAGE_SIZE;
1423 #ifdef CONFIG_KUSER_HELPERS
1424 map.type = MT_HIGH_VECTORS;
1426 map.type = MT_LOW_VECTORS;
1428 create_mapping(&map);
1430 if (!vectors_high()) {
1432 map.length = PAGE_SIZE * 2;
1433 map.type = MT_LOW_VECTORS;
1434 create_mapping(&map);
1437 /* Now create a kernel read-only mapping */
1439 map.virtual = 0xffff0000 + PAGE_SIZE;
1440 map.length = PAGE_SIZE;
1441 map.type = MT_LOW_VECTORS;
1442 create_mapping(&map);
1445 * Ask the machine support to map in the statically mapped devices.
1453 /* Reserve fixed i/o space in VMALLOC region */
1457 * Finally flush the caches and tlb to ensure that we're in a
1458 * consistent state wrt the writebuffer. This also ensures that
1459 * any write-allocated cache lines in the vector page are written
1460 * back. After this point, we can start to touch devices again.
1462 local_flush_tlb_all();
1465 /* Enable asynchronous aborts */
1469 static void __init kmap_init(void)
1471 #ifdef CONFIG_HIGHMEM
1472 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1473 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1476 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1477 _PAGE_KERNEL_TABLE);
1480 static void __init map_lowmem(void)
1482 struct memblock_region *reg;
1483 phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE);
1484 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1486 /* Map all the lowmem memory banks. */
1487 for_each_memblock(memory, reg) {
1488 phys_addr_t start = reg->base;
1489 phys_addr_t end = start + reg->size;
1490 struct map_desc map;
1492 if (memblock_is_nomap(reg))
1495 if (end > arm_lowmem_limit)
1496 end = arm_lowmem_limit;
1500 if (end < kernel_x_start) {
1501 map.pfn = __phys_to_pfn(start);
1502 map.virtual = __phys_to_virt(start);
1503 map.length = end - start;
1504 map.type = MT_MEMORY_RWX;
1506 create_mapping(&map);
1507 } else if (start >= kernel_x_end) {
1508 map.pfn = __phys_to_pfn(start);
1509 map.virtual = __phys_to_virt(start);
1510 map.length = end - start;
1511 map.type = MT_MEMORY_RW;
1513 create_mapping(&map);
1515 /* This better cover the entire kernel */
1516 if (start < kernel_x_start) {
1517 map.pfn = __phys_to_pfn(start);
1518 map.virtual = __phys_to_virt(start);
1519 map.length = kernel_x_start - start;
1520 map.type = MT_MEMORY_RW;
1522 create_mapping(&map);
1525 map.pfn = __phys_to_pfn(kernel_x_start);
1526 map.virtual = __phys_to_virt(kernel_x_start);
1527 map.length = kernel_x_end - kernel_x_start;
1528 map.type = MT_MEMORY_RWX;
1530 create_mapping(&map);
1532 if (kernel_x_end < end) {
1533 map.pfn = __phys_to_pfn(kernel_x_end);
1534 map.virtual = __phys_to_virt(kernel_x_end);
1535 map.length = end - kernel_x_end;
1536 map.type = MT_MEMORY_RW;
1538 create_mapping(&map);
1544 #ifdef CONFIG_ARM_PV_FIXUP
1545 typedef void pgtables_remap(long long offset, unsigned long pgd);
1546 pgtables_remap lpae_pgtables_remap_asm;
1549 * early_paging_init() recreates boot time page table setup, allowing machines
1550 * to switch over to a high (>4G) address space on LPAE systems
1552 static void __init early_paging_init(const struct machine_desc *mdesc)
1554 pgtables_remap *lpae_pgtables_remap;
1555 unsigned long pa_pgd;
1556 unsigned int cr, ttbcr;
1559 if (!mdesc->pv_fixup)
1562 offset = mdesc->pv_fixup();
1567 * Get the address of the remap function in the 1:1 identity
1568 * mapping setup by the early page table assembly code. We
1569 * must get this prior to the pv update. The following barrier
1570 * ensures that this is complete before we fixup any P:V offsets.
1572 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1573 pa_pgd = __pa(swapper_pg_dir);
1576 pr_info("Switching physical address space to 0x%08llx\n",
1577 (u64)PHYS_OFFSET + offset);
1579 /* Re-set the phys pfn offset, and the pv offset */
1580 __pv_offset += offset;
1581 __pv_phys_pfn_offset += PFN_DOWN(offset);
1583 /* Run the patch stub to update the constants */
1584 fixup_pv_table(&__pv_table_begin,
1585 (&__pv_table_end - &__pv_table_begin) << 2);
1588 * We changing not only the virtual to physical mapping, but also
1589 * the physical addresses used to access memory. We need to flush
1590 * all levels of cache in the system with caching disabled to
1591 * ensure that all data is written back, and nothing is prefetched
1592 * into the caches. We also need to prevent the TLB walkers
1593 * allocating into the caches too. Note that this is ARMv7 LPAE
1597 set_cr(cr & ~(CR_I | CR_C));
1598 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
1599 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1600 : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
1604 * Fixup the page tables - this must be in the idmap region as
1605 * we need to disable the MMU to do this safely, and hence it
1606 * needs to be assembly. It's fairly simple, as we're using the
1607 * temporary tables setup by the initial assembly code.
1609 lpae_pgtables_remap(offset, pa_pgd);
1611 /* Re-enable the caches and cacheable TLB walks */
1612 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
1618 static void __init early_paging_init(const struct machine_desc *mdesc)
1622 if (!mdesc->pv_fixup)
1625 offset = mdesc->pv_fixup();
1629 pr_crit("Physical address space modification is only to support Keystone2.\n");
1630 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1631 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1632 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1637 static void __init early_fixmap_shutdown(void)
1640 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1642 pte_offset_fixmap = pte_offset_late_fixmap;
1643 pmd_clear(fixmap_pmd(va));
1644 local_flush_tlb_kernel_page(va);
1646 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1648 struct map_desc map;
1650 map.virtual = fix_to_virt(i);
1651 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1653 /* Only i/o device mappings are supported ATM */
1654 if (pte_none(*pte) ||
1655 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1658 map.pfn = pte_pfn(*pte);
1659 map.type = MT_DEVICE;
1660 map.length = PAGE_SIZE;
1662 create_mapping(&map);
1667 * paging_init() sets up the page tables, initialises the zone memory
1668 * maps, and sets up the zero page, bad page and bad page tables.
1670 void __init paging_init(const struct machine_desc *mdesc)
1674 prepare_page_table();
1676 memblock_set_current_limit(arm_lowmem_limit);
1677 dma_contiguous_remap();
1678 early_fixmap_shutdown();
1679 devicemaps_init(mdesc);
1683 top_pmd = pmd_off_k(0xffff0000);
1685 /* allocate the zero page. */
1686 zero_page = early_alloc(PAGE_SIZE);
1690 empty_zero_page = virt_to_page(zero_page);
1691 __flush_dcache_page(NULL, empty_zero_page);
1693 /* Compute the virt/idmap offset, mostly for the sake of KVM */
1694 kimage_voffset = (unsigned long)&kimage_voffset - virt_to_idmap(&kimage_voffset);
1697 void __init early_mm_init(const struct machine_desc *mdesc)
1699 build_mem_type_table();
1700 early_paging_init(mdesc);