1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mm/mmu.c
5 * Copyright (C) 1995-2005 Russell King
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/errno.h>
10 #include <linux/init.h>
11 #include <linux/mman.h>
12 #include <linux/nodemask.h>
13 #include <linux/memblock.h>
15 #include <linux/vmalloc.h>
16 #include <linux/sizes.h>
19 #include <asm/cputype.h>
20 #include <asm/cachetype.h>
21 #include <asm/fixmap.h>
22 #include <asm/sections.h>
23 #include <asm/setup.h>
24 #include <asm/smp_plat.h>
26 #include <asm/highmem.h>
27 #include <asm/system_info.h>
28 #include <asm/traps.h>
29 #include <asm/procinfo.h>
30 #include <asm/memory.h>
31 #include <asm/pgalloc.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/pci.h>
36 #include <asm/fixmap.h>
42 extern unsigned long __atags_pointer;
45 * empty_zero_page is a special page that is used for
46 * zero-initialized data and COW.
48 struct page *empty_zero_page;
49 EXPORT_SYMBOL(empty_zero_page);
52 * The pmd table for the upper-most set of pages.
56 pmdval_t user_pmd_table = _PAGE_USER_TABLE;
58 #define CPOLICY_UNCACHED 0
59 #define CPOLICY_BUFFERED 1
60 #define CPOLICY_WRITETHROUGH 2
61 #define CPOLICY_WRITEBACK 3
62 #define CPOLICY_WRITEALLOC 4
64 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
65 static unsigned int ecc_mask __initdata = 0;
67 pgprot_t pgprot_kernel;
69 EXPORT_SYMBOL(pgprot_user);
70 EXPORT_SYMBOL(pgprot_kernel);
73 const char policy[16];
79 static struct cachepolicy cache_policies[] __initdata = {
83 .pmd = PMD_SECT_UNCACHED,
84 .pte = L_PTE_MT_UNCACHED,
88 .pmd = PMD_SECT_BUFFERED,
89 .pte = L_PTE_MT_BUFFERABLE,
91 .policy = "writethrough",
94 .pte = L_PTE_MT_WRITETHROUGH,
96 .policy = "writeback",
99 .pte = L_PTE_MT_WRITEBACK,
101 .policy = "writealloc",
103 .pmd = PMD_SECT_WBWA,
104 .pte = L_PTE_MT_WRITEALLOC,
108 #ifdef CONFIG_CPU_CP15
109 static unsigned long initial_pmd_value __initdata = 0;
112 * Initialise the cache_policy variable with the initial state specified
113 * via the "pmd" value. This is used to ensure that on ARMv6 and later,
114 * the C code sets the page tables up with the same policy as the head
115 * assembly code, which avoids an illegal state where the TLBs can get
116 * confused. See comments in early_cachepolicy() for more information.
118 void __init init_default_cache_policy(unsigned long pmd)
122 initial_pmd_value = pmd;
124 pmd &= PMD_SECT_CACHE_MASK;
126 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
127 if (cache_policies[i].pmd == pmd) {
132 if (i == ARRAY_SIZE(cache_policies))
133 pr_err("ERROR: could not find cache policy\n");
137 * These are useful for identifying cache coherency problems by allowing
138 * the cache or the cache and writebuffer to be turned off. (Note: the
139 * write buffer should not be on and the cache off).
141 static int __init early_cachepolicy(char *p)
143 int i, selected = -1;
145 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
146 int len = strlen(cache_policies[i].policy);
148 if (memcmp(p, cache_policies[i].policy, len) == 0) {
155 pr_err("ERROR: unknown or unsupported cache policy\n");
158 * This restriction is partly to do with the way we boot; it is
159 * unpredictable to have memory mapped using two different sets of
160 * memory attributes (shared, type, and cache attribs). We can not
161 * change these attributes once the initial assembly has setup the
164 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
165 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
166 cache_policies[cachepolicy].policy);
170 if (selected != cachepolicy) {
171 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
172 cachepolicy = selected;
178 early_param("cachepolicy", early_cachepolicy);
180 static int __init early_nocache(char *__unused)
182 char *p = "buffered";
183 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
184 early_cachepolicy(p);
187 early_param("nocache", early_nocache);
189 static int __init early_nowrite(char *__unused)
191 char *p = "uncached";
192 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
193 early_cachepolicy(p);
196 early_param("nowb", early_nowrite);
198 #ifndef CONFIG_ARM_LPAE
199 static int __init early_ecc(char *p)
201 if (memcmp(p, "on", 2) == 0)
202 ecc_mask = PMD_PROTECTION;
203 else if (memcmp(p, "off", 3) == 0)
207 early_param("ecc", early_ecc);
210 #else /* ifdef CONFIG_CPU_CP15 */
212 static int __init early_cachepolicy(char *p)
214 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
217 early_param("cachepolicy", early_cachepolicy);
219 static int __init noalign_setup(char *__unused)
221 pr_warn("noalign kernel parameter not supported without cp15\n");
224 __setup("noalign", noalign_setup);
226 #endif /* ifdef CONFIG_CPU_CP15 / else */
228 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
229 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
230 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
232 static struct mem_type mem_types[] __ro_after_init = {
233 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
234 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
236 .prot_l1 = PMD_TYPE_TABLE,
237 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
240 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
241 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
242 .prot_l1 = PMD_TYPE_TABLE,
243 .prot_sect = PROT_SECT_DEVICE,
246 [MT_DEVICE_CACHED] = { /* ioremap_cache */
247 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
248 .prot_l1 = PMD_TYPE_TABLE,
249 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
252 [MT_DEVICE_WC] = { /* ioremap_wc */
253 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
254 .prot_l1 = PMD_TYPE_TABLE,
255 .prot_sect = PROT_SECT_DEVICE,
259 .prot_pte = PROT_PTE_DEVICE,
260 .prot_l1 = PMD_TYPE_TABLE,
261 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
265 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
266 .domain = DOMAIN_KERNEL,
268 #ifndef CONFIG_ARM_LPAE
270 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
271 .domain = DOMAIN_KERNEL,
275 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
277 .prot_l1 = PMD_TYPE_TABLE,
278 .domain = DOMAIN_VECTORS,
280 [MT_HIGH_VECTORS] = {
281 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
282 L_PTE_USER | L_PTE_RDONLY,
283 .prot_l1 = PMD_TYPE_TABLE,
284 .domain = DOMAIN_VECTORS,
287 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
288 .prot_l1 = PMD_TYPE_TABLE,
289 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
290 .domain = DOMAIN_KERNEL,
293 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
295 .prot_l1 = PMD_TYPE_TABLE,
296 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
297 .domain = DOMAIN_KERNEL,
300 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
301 L_PTE_XN | L_PTE_RDONLY,
302 .prot_l1 = PMD_TYPE_TABLE,
303 #ifdef CONFIG_ARM_LPAE
304 .prot_sect = PMD_TYPE_SECT | L_PMD_SECT_RDONLY | PMD_SECT_AP2,
306 .prot_sect = PMD_TYPE_SECT,
308 .domain = DOMAIN_KERNEL,
311 .prot_sect = PMD_TYPE_SECT,
312 .domain = DOMAIN_KERNEL,
314 [MT_MEMORY_RWX_NONCACHED] = {
315 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
317 .prot_l1 = PMD_TYPE_TABLE,
318 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
319 .domain = DOMAIN_KERNEL,
321 [MT_MEMORY_RW_DTCM] = {
322 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
324 .prot_l1 = PMD_TYPE_TABLE,
325 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
326 .domain = DOMAIN_KERNEL,
328 [MT_MEMORY_RWX_ITCM] = {
329 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
330 .prot_l1 = PMD_TYPE_TABLE,
331 .domain = DOMAIN_KERNEL,
333 [MT_MEMORY_RW_SO] = {
334 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
335 L_PTE_MT_UNCACHED | L_PTE_XN,
336 .prot_l1 = PMD_TYPE_TABLE,
337 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
338 PMD_SECT_UNCACHED | PMD_SECT_XN,
339 .domain = DOMAIN_KERNEL,
341 [MT_MEMORY_DMA_READY] = {
342 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
344 .prot_l1 = PMD_TYPE_TABLE,
345 .domain = DOMAIN_KERNEL,
349 const struct mem_type *get_mem_type(unsigned int type)
351 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
353 EXPORT_SYMBOL(get_mem_type);
355 static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
357 static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
358 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
360 static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
362 return &bm_pte[pte_index(addr)];
365 static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
367 return pte_offset_kernel(dir, addr);
370 static inline pmd_t * __init fixmap_pmd(unsigned long addr)
372 return pmd_off_k(addr);
375 void __init early_fixmap_init(void)
380 * The early fixmap range spans multiple pmds, for which
381 * we are not prepared:
383 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
384 != FIXADDR_TOP >> PMD_SHIFT);
386 pmd = fixmap_pmd(FIXADDR_TOP);
387 pmd_populate_kernel(&init_mm, pmd, bm_pte);
389 pte_offset_fixmap = pte_offset_early_fixmap;
393 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
394 * As a result, this can only be called with preemption disabled, as under
397 void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
399 unsigned long vaddr = __fix_to_virt(idx);
400 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
402 /* Make sure fixmap region does not exceed available allocation. */
403 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
405 BUG_ON(idx >= __end_of_fixed_addresses);
407 /* We support only device mappings before pgprot_kernel is set. */
408 if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
409 pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0))
412 if (pgprot_val(prot))
413 set_pte_at(NULL, vaddr, pte,
414 pfn_pte(phys >> PAGE_SHIFT, prot));
416 pte_clear(NULL, vaddr, pte);
417 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
421 * Adjust the PMD section entries according to the CPU in use.
423 static void __init build_mem_type_table(void)
425 struct cachepolicy *cp;
426 unsigned int cr = get_cr();
427 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
428 int cpu_arch = cpu_architecture();
431 if (cpu_arch < CPU_ARCH_ARMv6) {
432 #if defined(CONFIG_CPU_DCACHE_DISABLE)
433 if (cachepolicy > CPOLICY_BUFFERED)
434 cachepolicy = CPOLICY_BUFFERED;
435 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
436 if (cachepolicy > CPOLICY_WRITETHROUGH)
437 cachepolicy = CPOLICY_WRITETHROUGH;
440 if (cpu_arch < CPU_ARCH_ARMv5) {
441 if (cachepolicy >= CPOLICY_WRITEALLOC)
442 cachepolicy = CPOLICY_WRITEBACK;
447 if (cachepolicy != CPOLICY_WRITEALLOC) {
448 pr_warn("Forcing write-allocate cache policy for SMP\n");
449 cachepolicy = CPOLICY_WRITEALLOC;
451 if (!(initial_pmd_value & PMD_SECT_S)) {
452 pr_warn("Forcing shared mappings for SMP\n");
453 initial_pmd_value |= PMD_SECT_S;
458 * Strip out features not present on earlier architectures.
459 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
460 * without extended page tables don't have the 'Shared' bit.
462 if (cpu_arch < CPU_ARCH_ARMv5)
463 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
464 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
465 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
466 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
467 mem_types[i].prot_sect &= ~PMD_SECT_S;
470 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
471 * "update-able on write" bit on ARM610). However, Xscale and
472 * Xscale3 require this bit to be cleared.
474 if (cpu_is_xscale_family()) {
475 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
476 mem_types[i].prot_sect &= ~PMD_BIT4;
477 mem_types[i].prot_l1 &= ~PMD_BIT4;
479 } else if (cpu_arch < CPU_ARCH_ARMv6) {
480 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
481 if (mem_types[i].prot_l1)
482 mem_types[i].prot_l1 |= PMD_BIT4;
483 if (mem_types[i].prot_sect)
484 mem_types[i].prot_sect |= PMD_BIT4;
489 * Mark the device areas according to the CPU/architecture.
491 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
492 if (!cpu_is_xsc3()) {
494 * Mark device regions on ARMv6+ as execute-never
495 * to prevent speculative instruction fetches.
497 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
498 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
499 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
500 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
502 /* Also setup NX memory mapping */
503 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
504 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_XN;
506 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
508 * For ARMv7 with TEX remapping,
509 * - shared device is SXCB=1100
510 * - nonshared device is SXCB=0100
511 * - write combine device mem is SXCB=0001
512 * (Uncached Normal memory)
514 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
515 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
516 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
517 } else if (cpu_is_xsc3()) {
520 * - shared device is TEXCB=00101
521 * - nonshared device is TEXCB=01000
522 * - write combine device mem is TEXCB=00100
523 * (Inner/Outer Uncacheable in xsc3 parlance)
525 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
526 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
527 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
530 * For ARMv6 and ARMv7 without TEX remapping,
531 * - shared device is TEXCB=00001
532 * - nonshared device is TEXCB=01000
533 * - write combine device mem is TEXCB=00100
534 * (Uncached Normal in ARMv6 parlance).
536 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
537 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
538 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
542 * On others, write combining is "Uncached/Buffered"
544 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
548 * Now deal with the memory-type mappings
550 cp = &cache_policies[cachepolicy];
551 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
553 #ifndef CONFIG_ARM_LPAE
555 * We don't use domains on ARMv6 (since this causes problems with
556 * v6/v7 kernels), so we must use a separate memory type for user
557 * r/o, kernel r/w to map the vectors page.
559 if (cpu_arch == CPU_ARCH_ARMv6)
560 vecs_pgprot |= L_PTE_MT_VECTORS;
563 * Check is it with support for the PXN bit
564 * in the Short-descriptor translation table format descriptors.
566 if (cpu_arch == CPU_ARCH_ARMv7 &&
567 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
568 user_pmd_table |= PMD_PXNTABLE;
573 * ARMv6 and above have extended page tables.
575 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
576 #ifndef CONFIG_ARM_LPAE
578 * Mark cache clean areas and XIP ROM read only
579 * from SVC mode and no access from userspace.
581 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
582 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
583 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
584 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
588 * If the initial page tables were created with the S bit
589 * set, then we need to do the same here for the same
590 * reasons given in early_cachepolicy().
592 if (initial_pmd_value & PMD_SECT_S) {
593 user_pgprot |= L_PTE_SHARED;
594 kern_pgprot |= L_PTE_SHARED;
595 vecs_pgprot |= L_PTE_SHARED;
596 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
597 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
598 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
599 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
600 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
601 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
602 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
603 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
604 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_S;
605 mem_types[MT_MEMORY_RO].prot_pte |= L_PTE_SHARED;
606 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
607 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
608 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
613 * Non-cacheable Normal - intended for memory areas that must
614 * not cause dirty cache line writebacks when used
616 if (cpu_arch >= CPU_ARCH_ARMv6) {
617 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
618 /* Non-cacheable Normal is XCB = 001 */
619 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
622 /* For both ARMv6 and non-TEX-remapping ARMv7 */
623 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
627 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
630 #ifdef CONFIG_ARM_LPAE
632 * Do not generate access flag faults for the kernel mappings.
634 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
635 mem_types[i].prot_pte |= PTE_EXT_AF;
636 if (mem_types[i].prot_sect)
637 mem_types[i].prot_sect |= PMD_SECT_AF;
639 kern_pgprot |= PTE_EXT_AF;
640 vecs_pgprot |= PTE_EXT_AF;
643 * Set PXN for user mappings
645 user_pgprot |= PTE_EXT_PXN;
648 for (i = 0; i < 16; i++) {
649 pteval_t v = pgprot_val(protection_map[i]);
650 protection_map[i] = __pgprot(v | user_pgprot);
653 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
654 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
656 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
657 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
658 L_PTE_DIRTY | kern_pgprot);
660 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
661 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
662 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
663 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
664 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
665 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
666 mem_types[MT_MEMORY_RO].prot_sect |= ecc_mask | cp->pmd;
667 mem_types[MT_MEMORY_RO].prot_pte |= kern_pgprot;
668 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
669 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
670 mem_types[MT_ROM].prot_sect |= cp->pmd;
674 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
678 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
681 pr_info("Memory policy: %sData cache %s\n",
682 ecc_mask ? "ECC enabled, " : "", cp->policy);
684 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
685 struct mem_type *t = &mem_types[i];
687 t->prot_l1 |= PMD_DOMAIN(t->domain);
689 t->prot_sect |= PMD_DOMAIN(t->domain);
693 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
694 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
695 unsigned long size, pgprot_t vma_prot)
698 return pgprot_noncached(vma_prot);
699 else if (file->f_flags & O_SYNC)
700 return pgprot_writecombine(vma_prot);
703 EXPORT_SYMBOL(phys_mem_access_prot);
706 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
708 static void __init *early_alloc(unsigned long sz)
710 void *ptr = memblock_alloc(sz, sz);
713 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
719 static void *__init late_alloc(unsigned long sz)
721 void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz));
723 if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr)))
728 static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
730 void *(*alloc)(unsigned long sz))
732 if (pmd_none(*pmd)) {
733 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
734 __pmd_populate(pmd, __pa(pte), prot);
736 BUG_ON(pmd_bad(*pmd));
737 return pte_offset_kernel(pmd, addr);
740 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
743 return arm_pte_alloc(pmd, addr, prot, early_alloc);
746 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
747 unsigned long end, unsigned long pfn,
748 const struct mem_type *type,
749 void *(*alloc)(unsigned long sz),
752 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
754 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
755 ng ? PTE_EXT_NG : 0);
757 } while (pte++, addr += PAGE_SIZE, addr != end);
760 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
761 unsigned long end, phys_addr_t phys,
762 const struct mem_type *type, bool ng)
766 #ifndef CONFIG_ARM_LPAE
768 * In classic MMU format, puds and pmds are folded in to
769 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
770 * group of L1 entries making up one logical pointer to
771 * an L2 table (2MB), where as PMDs refer to the individual
772 * L1 entries (1MB). Hence increment to get the correct
773 * offset for odd 1MB sections.
774 * (See arch/arm/include/asm/pgtable-2level.h)
776 if (addr & SECTION_SIZE)
780 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
781 phys += SECTION_SIZE;
782 } while (pmd++, addr += SECTION_SIZE, addr != end);
787 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
788 unsigned long end, phys_addr_t phys,
789 const struct mem_type *type,
790 void *(*alloc)(unsigned long sz), bool ng)
792 pmd_t *pmd = pmd_offset(pud, addr);
797 * With LPAE, we must loop over to map
798 * all the pmds for the given range.
800 next = pmd_addr_end(addr, end);
803 * Try a section mapping - addr, next and phys must all be
804 * aligned to a section boundary.
806 if (type->prot_sect &&
807 ((addr | next | phys) & ~SECTION_MASK) == 0) {
808 __map_init_section(pmd, addr, next, phys, type, ng);
810 alloc_init_pte(pmd, addr, next,
811 __phys_to_pfn(phys), type, alloc, ng);
816 } while (pmd++, addr = next, addr != end);
819 static void __init alloc_init_pud(p4d_t *p4d, unsigned long addr,
820 unsigned long end, phys_addr_t phys,
821 const struct mem_type *type,
822 void *(*alloc)(unsigned long sz), bool ng)
824 pud_t *pud = pud_offset(p4d, addr);
828 next = pud_addr_end(addr, end);
829 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
831 } while (pud++, addr = next, addr != end);
834 static void __init alloc_init_p4d(pgd_t *pgd, unsigned long addr,
835 unsigned long end, phys_addr_t phys,
836 const struct mem_type *type,
837 void *(*alloc)(unsigned long sz), bool ng)
839 p4d_t *p4d = p4d_offset(pgd, addr);
843 next = p4d_addr_end(addr, end);
844 alloc_init_pud(p4d, addr, next, phys, type, alloc, ng);
846 } while (p4d++, addr = next, addr != end);
849 #ifndef CONFIG_ARM_LPAE
850 static void __init create_36bit_mapping(struct mm_struct *mm,
852 const struct mem_type *type,
855 unsigned long addr, length, end;
860 phys = __pfn_to_phys(md->pfn);
861 length = PAGE_ALIGN(md->length);
863 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
864 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
865 (long long)__pfn_to_phys((u64)md->pfn), addr);
869 /* N.B. ARMv6 supersections are only defined to work with domain 0.
870 * Since domain assignments can in fact be arbitrary, the
871 * 'domain == 0' check below is required to insure that ARMv6
872 * supersections are only allocated for domain 0 regardless
873 * of the actual domain assignments in use.
876 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
877 (long long)__pfn_to_phys((u64)md->pfn), addr);
881 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
882 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
883 (long long)__pfn_to_phys((u64)md->pfn), addr);
888 * Shift bits [35:32] of address into bits [23:20] of PMD
891 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
893 pgd = pgd_offset(mm, addr);
896 p4d_t *p4d = p4d_offset(pgd, addr);
897 pud_t *pud = pud_offset(p4d, addr);
898 pmd_t *pmd = pmd_offset(pud, addr);
901 for (i = 0; i < 16; i++)
902 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
903 (ng ? PMD_SECT_nG : 0));
905 addr += SUPERSECTION_SIZE;
906 phys += SUPERSECTION_SIZE;
907 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
908 } while (addr != end);
910 #endif /* !CONFIG_ARM_LPAE */
912 static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
913 void *(*alloc)(unsigned long sz),
916 unsigned long addr, length, end;
918 const struct mem_type *type;
921 type = &mem_types[md->type];
923 #ifndef CONFIG_ARM_LPAE
925 * Catch 36-bit addresses
927 if (md->pfn >= 0x100000) {
928 create_36bit_mapping(mm, md, type, ng);
933 addr = md->virtual & PAGE_MASK;
934 phys = __pfn_to_phys(md->pfn);
935 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
937 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
938 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
939 (long long)__pfn_to_phys(md->pfn), addr);
943 pgd = pgd_offset(mm, addr);
946 unsigned long next = pgd_addr_end(addr, end);
948 alloc_init_p4d(pgd, addr, next, phys, type, alloc, ng);
952 } while (pgd++, addr != end);
956 * Create the page directory entries and any necessary
957 * page tables for the mapping specified by `md'. We
958 * are able to cope here with varying sizes and address
959 * offsets, and we take full advantage of sections and
962 static void __init create_mapping(struct map_desc *md)
964 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
965 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
966 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
970 if (md->type == MT_DEVICE &&
971 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
972 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
973 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
974 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
977 __create_mapping(&init_mm, md, early_alloc, false);
980 void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
983 #ifdef CONFIG_ARM_LPAE
987 p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
990 pud = pud_alloc(mm, p4d, md->virtual);
993 pmd_alloc(mm, pud, 0);
995 __create_mapping(mm, md, late_alloc, ng);
999 * Create the architecture specific mappings
1001 void __init iotable_init(struct map_desc *io_desc, int nr)
1003 struct map_desc *md;
1004 struct vm_struct *vm;
1005 struct static_vm *svm;
1010 svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm));
1012 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1013 __func__, sizeof(*svm) * nr, __alignof__(*svm));
1015 for (md = io_desc; nr; md++, nr--) {
1019 vm->addr = (void *)(md->virtual & PAGE_MASK);
1020 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
1021 vm->phys_addr = __pfn_to_phys(md->pfn);
1022 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
1023 vm->flags |= VM_ARM_MTYPE(md->type);
1024 vm->caller = iotable_init;
1025 add_static_vm_early(svm++);
1029 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
1032 struct vm_struct *vm;
1033 struct static_vm *svm;
1035 svm = memblock_alloc(sizeof(*svm), __alignof__(*svm));
1037 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1038 __func__, sizeof(*svm), __alignof__(*svm));
1041 vm->addr = (void *)addr;
1043 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
1044 vm->caller = caller;
1045 add_static_vm_early(svm);
1048 #ifndef CONFIG_ARM_LPAE
1051 * The Linux PMD is made of two consecutive section entries covering 2MB
1052 * (see definition in include/asm/pgtable-2level.h). However a call to
1053 * create_mapping() may optimize static mappings by using individual
1054 * 1MB section mappings. This leaves the actual PMD potentially half
1055 * initialized if the top or bottom section entry isn't used, leaving it
1056 * open to problems if a subsequent ioremap() or vmalloc() tries to use
1057 * the virtual space left free by that unused section entry.
1059 * Let's avoid the issue by inserting dummy vm entries covering the unused
1060 * PMD halves once the static mappings are in place.
1063 static void __init pmd_empty_section_gap(unsigned long addr)
1065 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1068 static void __init fill_pmd_gaps(void)
1070 struct static_vm *svm;
1071 struct vm_struct *vm;
1072 unsigned long addr, next = 0;
1075 list_for_each_entry(svm, &static_vmlist, list) {
1077 addr = (unsigned long)vm->addr;
1082 * Check if this vm starts on an odd section boundary.
1083 * If so and the first section entry for this PMD is free
1084 * then we block the corresponding virtual address.
1086 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1087 pmd = pmd_off_k(addr);
1089 pmd_empty_section_gap(addr & PMD_MASK);
1093 * Then check if this vm ends on an odd section boundary.
1094 * If so and the second section entry for this PMD is empty
1095 * then we block the corresponding virtual address.
1098 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1099 pmd = pmd_off_k(addr) + 1;
1101 pmd_empty_section_gap(addr);
1104 /* no need to look at any vm entry until we hit the next PMD */
1105 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1110 #define fill_pmd_gaps() do { } while (0)
1113 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1114 static void __init pci_reserve_io(void)
1116 struct static_vm *svm;
1118 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1122 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1125 #define pci_reserve_io() do { } while (0)
1128 #ifdef CONFIG_DEBUG_LL
1129 void __init debug_ll_io_init(void)
1131 struct map_desc map;
1133 debug_ll_addr(&map.pfn, &map.virtual);
1134 if (!map.pfn || !map.virtual)
1136 map.pfn = __phys_to_pfn(map.pfn);
1137 map.virtual &= PAGE_MASK;
1138 map.length = PAGE_SIZE;
1139 map.type = MT_DEVICE;
1140 iotable_init(&map, 1);
1144 static void * __initdata vmalloc_min =
1145 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1148 * vmalloc=size forces the vmalloc area to be exactly 'size'
1149 * bytes. This can be used to increase (or decrease) the vmalloc
1150 * area - the default is 240m.
1152 static int __init early_vmalloc(char *arg)
1154 unsigned long vmalloc_reserve = memparse(arg, NULL);
1156 if (vmalloc_reserve < SZ_16M) {
1157 vmalloc_reserve = SZ_16M;
1158 pr_warn("vmalloc area too small, limiting to %luMB\n",
1159 vmalloc_reserve >> 20);
1162 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1163 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1164 pr_warn("vmalloc area is too big, limiting to %luMB\n",
1165 vmalloc_reserve >> 20);
1168 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1171 early_param("vmalloc", early_vmalloc);
1173 phys_addr_t arm_lowmem_limit __initdata = 0;
1175 void __init adjust_lowmem_bounds(void)
1177 phys_addr_t block_start, block_end, memblock_limit = 0;
1178 u64 vmalloc_limit, i;
1179 phys_addr_t lowmem_limit = 0;
1182 * Let's use our own (unoptimized) equivalent of __pa() that is
1183 * not affected by wrap-arounds when sizeof(phys_addr_t) == 4.
1184 * The result is used as the upper bound on physical memory address
1185 * and may itself be outside the valid range for which phys_addr_t
1186 * and therefore __pa() is defined.
1188 vmalloc_limit = (u64)(uintptr_t)vmalloc_min - PAGE_OFFSET + PHYS_OFFSET;
1191 * The first usable region must be PMD aligned. Mark its start
1192 * as MEMBLOCK_NOMAP if it isn't
1194 for_each_mem_range(i, &block_start, &block_end) {
1195 if (!IS_ALIGNED(block_start, PMD_SIZE)) {
1198 len = round_up(block_start, PMD_SIZE) - block_start;
1199 memblock_mark_nomap(block_start, len);
1204 for_each_mem_range(i, &block_start, &block_end) {
1205 if (block_start < vmalloc_limit) {
1206 if (block_end > lowmem_limit)
1208 * Compare as u64 to ensure vmalloc_limit does
1209 * not get truncated. block_end should always
1210 * fit in phys_addr_t so there should be no
1211 * issue with assignment.
1213 lowmem_limit = min_t(u64,
1218 * Find the first non-pmd-aligned page, and point
1219 * memblock_limit at it. This relies on rounding the
1220 * limit down to be pmd-aligned, which happens at the
1221 * end of this function.
1223 * With this algorithm, the start or end of almost any
1224 * bank can be non-pmd-aligned. The only exception is
1225 * that the start of the bank 0 must be section-
1226 * aligned, since otherwise memory would need to be
1227 * allocated when mapping the start of bank 0, which
1228 * occurs before any free memory is mapped.
1230 if (!memblock_limit) {
1231 if (!IS_ALIGNED(block_start, PMD_SIZE))
1232 memblock_limit = block_start;
1233 else if (!IS_ALIGNED(block_end, PMD_SIZE))
1234 memblock_limit = lowmem_limit;
1240 arm_lowmem_limit = lowmem_limit;
1242 high_memory = __va(arm_lowmem_limit - 1) + 1;
1244 if (!memblock_limit)
1245 memblock_limit = arm_lowmem_limit;
1248 * Round the memblock limit down to a pmd size. This
1249 * helps to ensure that we will allocate memory from the
1250 * last full pmd, which should be mapped.
1252 memblock_limit = round_down(memblock_limit, PMD_SIZE);
1254 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1255 if (memblock_end_of_DRAM() > arm_lowmem_limit) {
1256 phys_addr_t end = memblock_end_of_DRAM();
1258 pr_notice("Ignoring RAM at %pa-%pa\n",
1259 &memblock_limit, &end);
1260 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1262 memblock_remove(memblock_limit, end - memblock_limit);
1266 memblock_set_current_limit(memblock_limit);
1269 static inline void prepare_page_table(void)
1275 * Clear out all the mappings below the kernel image.
1277 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1278 pmd_clear(pmd_off_k(addr));
1280 #ifdef CONFIG_XIP_KERNEL
1281 /* The XIP kernel is mapped in the module area -- skip over it */
1282 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
1284 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1285 pmd_clear(pmd_off_k(addr));
1288 * Find the end of the first block of lowmem.
1290 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1291 if (end >= arm_lowmem_limit)
1292 end = arm_lowmem_limit;
1295 * Clear out all the kernel space mappings, except for the first
1296 * memory bank, up to the vmalloc region.
1298 for (addr = __phys_to_virt(end);
1299 addr < VMALLOC_START; addr += PMD_SIZE)
1300 pmd_clear(pmd_off_k(addr));
1303 #ifdef CONFIG_ARM_LPAE
1304 /* the first page is reserved for pgd */
1305 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1306 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1308 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1312 * Reserve the special regions of memory
1314 void __init arm_mm_memblock_reserve(void)
1317 * Reserve the page tables. These are already in use,
1318 * and can only be in node 0.
1320 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1322 #ifdef CONFIG_SA1111
1324 * Because of the SA1111 DMA bug, we want to preserve our
1325 * precious DMA-able memory...
1327 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1332 * Set up the device mappings. Since we clear out the page tables for all
1333 * mappings above VMALLOC_START, except early fixmap, we might remove debug
1334 * device mappings. This means earlycon can be used to debug this function
1335 * Any other function or debugging method which may touch any device _will_
1338 static void __init devicemaps_init(const struct machine_desc *mdesc)
1340 struct map_desc map;
1345 * Allocate the vector page early.
1347 vectors = early_alloc(PAGE_SIZE * 2);
1349 early_trap_init(vectors);
1352 * Clear page table except top pmd used by early fixmaps
1354 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1355 pmd_clear(pmd_off_k(addr));
1357 if (__atags_pointer) {
1358 /* create a read-only mapping of the device tree */
1359 map.pfn = __phys_to_pfn(__atags_pointer & SECTION_MASK);
1360 map.virtual = FDT_FIXED_BASE;
1361 map.length = FDT_FIXED_SIZE;
1362 map.type = MT_MEMORY_RO;
1363 create_mapping(&map);
1367 * Map the kernel if it is XIP.
1368 * It is always first in the modulearea.
1370 #ifdef CONFIG_XIP_KERNEL
1371 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1372 map.virtual = MODULES_VADDR;
1373 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1375 create_mapping(&map);
1379 * Map the cache flushing regions.
1382 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1383 map.virtual = FLUSH_BASE;
1385 map.type = MT_CACHECLEAN;
1386 create_mapping(&map);
1388 #ifdef FLUSH_BASE_MINICACHE
1389 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1390 map.virtual = FLUSH_BASE_MINICACHE;
1392 map.type = MT_MINICLEAN;
1393 create_mapping(&map);
1397 * Create a mapping for the machine vectors at the high-vectors
1398 * location (0xffff0000). If we aren't using high-vectors, also
1399 * create a mapping at the low-vectors virtual address.
1401 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1402 map.virtual = 0xffff0000;
1403 map.length = PAGE_SIZE;
1404 #ifdef CONFIG_KUSER_HELPERS
1405 map.type = MT_HIGH_VECTORS;
1407 map.type = MT_LOW_VECTORS;
1409 create_mapping(&map);
1411 if (!vectors_high()) {
1413 map.length = PAGE_SIZE * 2;
1414 map.type = MT_LOW_VECTORS;
1415 create_mapping(&map);
1418 /* Now create a kernel read-only mapping */
1420 map.virtual = 0xffff0000 + PAGE_SIZE;
1421 map.length = PAGE_SIZE;
1422 map.type = MT_LOW_VECTORS;
1423 create_mapping(&map);
1426 * Ask the machine support to map in the statically mapped devices.
1434 /* Reserve fixed i/o space in VMALLOC region */
1438 * Finally flush the caches and tlb to ensure that we're in a
1439 * consistent state wrt the writebuffer. This also ensures that
1440 * any write-allocated cache lines in the vector page are written
1441 * back. After this point, we can start to touch devices again.
1443 local_flush_tlb_all();
1446 /* Enable asynchronous aborts */
1450 static void __init kmap_init(void)
1452 #ifdef CONFIG_HIGHMEM
1453 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1454 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1457 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1458 _PAGE_KERNEL_TABLE);
1461 static void __init map_lowmem(void)
1463 phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE);
1464 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1465 phys_addr_t start, end;
1468 /* Map all the lowmem memory banks. */
1469 for_each_mem_range(i, &start, &end) {
1470 struct map_desc map;
1472 if (end > arm_lowmem_limit)
1473 end = arm_lowmem_limit;
1477 if (end < kernel_x_start) {
1478 map.pfn = __phys_to_pfn(start);
1479 map.virtual = __phys_to_virt(start);
1480 map.length = end - start;
1481 map.type = MT_MEMORY_RWX;
1483 create_mapping(&map);
1484 } else if (start >= kernel_x_end) {
1485 map.pfn = __phys_to_pfn(start);
1486 map.virtual = __phys_to_virt(start);
1487 map.length = end - start;
1488 map.type = MT_MEMORY_RW;
1490 create_mapping(&map);
1492 /* This better cover the entire kernel */
1493 if (start < kernel_x_start) {
1494 map.pfn = __phys_to_pfn(start);
1495 map.virtual = __phys_to_virt(start);
1496 map.length = kernel_x_start - start;
1497 map.type = MT_MEMORY_RW;
1499 create_mapping(&map);
1502 map.pfn = __phys_to_pfn(kernel_x_start);
1503 map.virtual = __phys_to_virt(kernel_x_start);
1504 map.length = kernel_x_end - kernel_x_start;
1505 map.type = MT_MEMORY_RWX;
1507 create_mapping(&map);
1509 if (kernel_x_end < end) {
1510 map.pfn = __phys_to_pfn(kernel_x_end);
1511 map.virtual = __phys_to_virt(kernel_x_end);
1512 map.length = end - kernel_x_end;
1513 map.type = MT_MEMORY_RW;
1515 create_mapping(&map);
1521 #ifdef CONFIG_ARM_PV_FIXUP
1522 typedef void pgtables_remap(long long offset, unsigned long pgd);
1523 pgtables_remap lpae_pgtables_remap_asm;
1526 * early_paging_init() recreates boot time page table setup, allowing machines
1527 * to switch over to a high (>4G) address space on LPAE systems
1529 static void __init early_paging_init(const struct machine_desc *mdesc)
1531 pgtables_remap *lpae_pgtables_remap;
1532 unsigned long pa_pgd;
1533 unsigned int cr, ttbcr;
1536 if (!mdesc->pv_fixup)
1539 offset = mdesc->pv_fixup();
1544 * Get the address of the remap function in the 1:1 identity
1545 * mapping setup by the early page table assembly code. We
1546 * must get this prior to the pv update. The following barrier
1547 * ensures that this is complete before we fixup any P:V offsets.
1549 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1550 pa_pgd = __pa(swapper_pg_dir);
1553 pr_info("Switching physical address space to 0x%08llx\n",
1554 (u64)PHYS_OFFSET + offset);
1556 /* Re-set the phys pfn offset, and the pv offset */
1557 __pv_offset += offset;
1558 __pv_phys_pfn_offset += PFN_DOWN(offset);
1560 /* Run the patch stub to update the constants */
1561 fixup_pv_table(&__pv_table_begin,
1562 (&__pv_table_end - &__pv_table_begin) << 2);
1565 * We changing not only the virtual to physical mapping, but also
1566 * the physical addresses used to access memory. We need to flush
1567 * all levels of cache in the system with caching disabled to
1568 * ensure that all data is written back, and nothing is prefetched
1569 * into the caches. We also need to prevent the TLB walkers
1570 * allocating into the caches too. Note that this is ARMv7 LPAE
1574 set_cr(cr & ~(CR_I | CR_C));
1575 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
1576 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1577 : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
1581 * Fixup the page tables - this must be in the idmap region as
1582 * we need to disable the MMU to do this safely, and hence it
1583 * needs to be assembly. It's fairly simple, as we're using the
1584 * temporary tables setup by the initial assembly code.
1586 lpae_pgtables_remap(offset, pa_pgd);
1588 /* Re-enable the caches and cacheable TLB walks */
1589 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
1595 static void __init early_paging_init(const struct machine_desc *mdesc)
1599 if (!mdesc->pv_fixup)
1602 offset = mdesc->pv_fixup();
1606 pr_crit("Physical address space modification is only to support Keystone2.\n");
1607 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1608 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1609 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1614 static void __init early_fixmap_shutdown(void)
1617 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1619 pte_offset_fixmap = pte_offset_late_fixmap;
1620 pmd_clear(fixmap_pmd(va));
1621 local_flush_tlb_kernel_page(va);
1623 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1625 struct map_desc map;
1627 map.virtual = fix_to_virt(i);
1628 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1630 /* Only i/o device mappings are supported ATM */
1631 if (pte_none(*pte) ||
1632 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1635 map.pfn = pte_pfn(*pte);
1636 map.type = MT_DEVICE;
1637 map.length = PAGE_SIZE;
1639 create_mapping(&map);
1644 * paging_init() sets up the page tables, initialises the zone memory
1645 * maps, and sets up the zero page, bad page and bad page tables.
1647 void __init paging_init(const struct machine_desc *mdesc)
1651 prepare_page_table();
1653 memblock_set_current_limit(arm_lowmem_limit);
1654 dma_contiguous_remap();
1655 early_fixmap_shutdown();
1656 devicemaps_init(mdesc);
1660 top_pmd = pmd_off_k(0xffff0000);
1662 /* allocate the zero page. */
1663 zero_page = early_alloc(PAGE_SIZE);
1667 empty_zero_page = virt_to_page(zero_page);
1668 __flush_dcache_page(NULL, empty_zero_page);
1671 void __init early_mm_init(const struct machine_desc *mdesc)
1673 build_mem_type_table();
1674 early_paging_init(mdesc);
1677 void set_pte_at(struct mm_struct *mm, unsigned long addr,
1678 pte_t *ptep, pte_t pteval)
1680 unsigned long ext = 0;
1682 if (addr < TASK_SIZE && pte_valid_user(pteval)) {
1683 if (!pte_special(pteval))
1684 __sync_icache_dcache(pteval);
1688 set_pte_ext(ptep, pteval, ext);