1 # SPDX-License-Identifier: GPL-2.0
2 comment "Processor Type"
4 # Select CPU types depending on the architecture selected. This selects
5 # which CPUs we support in the kernel image, and the compiler instruction
15 select CPU_PABRT_LEGACY
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
20 Say Y if you want support for the ARM7TDMI processor.
30 select CPU_COPY_V4WT if MMU
32 select CPU_PABRT_LEGACY
33 select CPU_THUMB_CAPABLE
34 select CPU_TLB_V4WT if MMU
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
37 MMU built around an ARM7TDMI core.
39 Say Y if you want support for the ARM720T processor.
50 select CPU_PABRT_LEGACY
51 select CPU_THUMB_CAPABLE
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
54 write buffer and MPU(Protection Unit) built around
57 Say Y if you want support for the ARM740T processor.
67 select CPU_PABRT_LEGACY
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
72 Say Y if you want support for the ARM9TDMI processor.
82 select CPU_COPY_V4WB if MMU
84 select CPU_PABRT_LEGACY
85 select CPU_THUMB_CAPABLE
86 select CPU_TLB_V4WBI if MMU
88 The ARM920T is licensed to be produced by numerous vendors,
89 and is used in the Cirrus EP93xx and the Samsung S3C2410.
91 Say Y if you want support for the ARM920T processor.
100 select CPU_CACHE_VIVT
101 select CPU_COPY_V4WB if MMU
103 select CPU_PABRT_LEGACY
104 select CPU_THUMB_CAPABLE
105 select CPU_TLB_V4WBI if MMU
107 The ARM922T is a version of the ARM920T, but with smaller
108 instruction and data caches. It is used in Altera's
109 Excalibur XA device family and Micrel's KS8695 Centaur.
111 Say Y if you want support for the ARM922T processor.
119 select CPU_CACHE_V4WT
120 select CPU_CACHE_VIVT
121 select CPU_COPY_V4WB if MMU
123 select CPU_PABRT_LEGACY
124 select CPU_THUMB_CAPABLE
125 select CPU_TLB_V4WBI if MMU
127 The ARM925T is a mix between the ARM920T and ARM926T, but with
128 different instruction and data caches. It is used in TI's OMAP
131 Say Y if you want support for the ARM925T processor.
138 select CPU_ABRT_EV5TJ
139 select CPU_CACHE_VIVT
140 select CPU_COPY_V4WB if MMU
142 select CPU_PABRT_LEGACY
143 select CPU_THUMB_CAPABLE
144 select CPU_TLB_V4WBI if MMU
146 This is a variant of the ARM920. It has slightly different
147 instruction sequences for cache and TLB operations. Curiously,
148 there is no documentation on it at the ARM corporate website.
150 Say Y if you want support for the ARM926T processor.
159 select CPU_CACHE_VIVT
160 select CPU_COPY_FA if MMU
162 select CPU_PABRT_LEGACY
163 select CPU_TLB_FA if MMU
165 The FA526 is a version of the ARMv4 compatible processor with
166 Branch Target Buffer, Unified TLB and cache line size 16.
168 Say Y if you want support for the FA526 processor.
176 select CPU_ABRT_NOMMU
177 select CPU_CACHE_VIVT
179 select CPU_PABRT_LEGACY
180 select CPU_THUMB_CAPABLE
182 ARM940T is a member of the ARM9TDMI family of general-
183 purpose microprocessors with MPU and separate 4KB
184 instruction and 4KB data cases, each with a 4-word line
187 Say Y if you want support for the ARM940T processor.
195 select CPU_ABRT_NOMMU
196 select CPU_CACHE_VIVT
198 select CPU_PABRT_LEGACY
199 select CPU_THUMB_CAPABLE
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
203 The TCM and ARMv5TE 32-bit instruction set is supported.
205 Say Y if you want support for the ARM946E-S processor.
208 # ARM1020 - needs validating
213 select CPU_CACHE_V4WT
214 select CPU_CACHE_VIVT
215 select CPU_COPY_V4WB if MMU
217 select CPU_PABRT_LEGACY
218 select CPU_THUMB_CAPABLE
219 select CPU_TLB_V4WBI if MMU
221 The ARM1020 is the 32K cached version of the ARM10 processor,
222 with an addition of a floating-point unit.
224 Say Y if you want support for the ARM1020 processor.
227 # ARM1020E - needs validating
233 select CPU_CACHE_V4WT
234 select CPU_CACHE_VIVT
235 select CPU_COPY_V4WB if MMU
237 select CPU_PABRT_LEGACY
238 select CPU_THUMB_CAPABLE
239 select CPU_TLB_V4WBI if MMU
246 select CPU_CACHE_VIVT
247 select CPU_COPY_V4WB if MMU # can probably do better
249 select CPU_PABRT_LEGACY
250 select CPU_THUMB_CAPABLE
251 select CPU_TLB_V4WBI if MMU
253 The ARM1022E is an implementation of the ARMv5TE architecture
254 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
255 embedded trace macrocell, and a floating-point unit.
257 Say Y if you want support for the ARM1022E processor.
264 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
265 select CPU_CACHE_VIVT
266 select CPU_COPY_V4WB if MMU # can probably do better
268 select CPU_PABRT_LEGACY
269 select CPU_THUMB_CAPABLE
270 select CPU_TLB_V4WBI if MMU
272 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
273 based upon the ARM10 integer core.
275 Say Y if you want support for the ARM1026EJ-S processor.
281 select CPU_32v3 if ARCH_RPC
282 select CPU_32v4 if !ARCH_RPC
284 select CPU_CACHE_V4WB
285 select CPU_CACHE_VIVT
286 select CPU_COPY_V4WB if MMU
288 select CPU_PABRT_LEGACY
289 select CPU_TLB_V4WB if MMU
291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
292 is available at five speeds ranging from 100 MHz to 233 MHz.
293 More information is available at
294 <http://developer.intel.com/design/strong/sa110.htm>.
296 Say Y if you want support for the SA-110 processor.
304 select CPU_CACHE_V4WB
305 select CPU_CACHE_VIVT
307 select CPU_PABRT_LEGACY
308 select CPU_TLB_V4WB if MMU
315 select CPU_CACHE_VIVT
317 select CPU_PABRT_LEGACY
318 select CPU_THUMB_CAPABLE
319 select CPU_TLB_V4WBI if MMU
321 # XScale Core Version 3
326 select CPU_CACHE_VIVT
328 select CPU_PABRT_LEGACY
329 select CPU_THUMB_CAPABLE
330 select CPU_TLB_V4WBI if MMU
333 # Marvell PJ1 (Mohawk)
338 select CPU_CACHE_VIVT
339 select CPU_COPY_V4WB if MMU
341 select CPU_PABRT_LEGACY
342 select CPU_THUMB_CAPABLE
343 select CPU_TLB_V4WBI if MMU
350 select CPU_CACHE_VIVT
351 select CPU_COPY_FEROCEON if MMU
353 select CPU_PABRT_LEGACY
354 select CPU_THUMB_CAPABLE
355 select CPU_TLB_FEROCEON if MMU
357 config CPU_FEROCEON_OLD_ID
358 bool "Accept early Feroceon cores with an ARM926 ID"
359 depends on CPU_FEROCEON && !CPU_ARM926T
362 This enables the usage of some old Feroceon cores
363 for which the CPU ID is equal to the ARM926 ID.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
382 select CPU_CACHE_VIPT
383 select CPU_COPY_V6 if MMU
385 select CPU_HAS_ASID if MMU
387 select CPU_THUMB_CAPABLE
388 select CPU_TLB_V6 if MMU
397 select CPU_CACHE_VIPT
398 select CPU_COPY_V6 if MMU
400 select CPU_HAS_ASID if MMU
402 select CPU_THUMB_CAPABLE
403 select CPU_TLB_V6 if MMU
412 select CPU_CACHE_VIPT
413 select CPU_COPY_V6 if MMU
414 select CPU_CP15_MMU if MMU
415 select CPU_CP15_MPU if !MMU
416 select CPU_HAS_ASID if MMU
418 select CPU_SPECTRE if MMU
419 select CPU_THUMB_CAPABLE
420 select CPU_TLB_V7 if MMU
426 select CPU_ABRT_NOMMU
429 select CPU_PABRT_LEGACY
434 select CPU_THUMB_CAPABLE
435 # There are no CPUs available with MMU that don't implement an ARM ISA:
438 Select this if your CPU doesn't support the 32 bit ARM instructions.
440 config CPU_THUMB_CAPABLE
443 Select this if your CPU can support Thumb mode.
445 # Figure out what processor architecture version we should be using.
446 # This defines the compiler instruction set which depends on the machine type.
449 select CPU_USE_DOMAINS if MMU
450 select NEED_KUSER_HELPERS
451 select TLS_REG_EMUL if SMP || !MMU
452 select CPU_NO_EFFICIENT_FFS
456 select CPU_USE_DOMAINS if MMU
457 select NEED_KUSER_HELPERS
458 select TLS_REG_EMUL if SMP || !MMU
459 select CPU_NO_EFFICIENT_FFS
463 select CPU_USE_DOMAINS if MMU
464 select NEED_KUSER_HELPERS
465 select TLS_REG_EMUL if SMP || !MMU
466 select CPU_NO_EFFICIENT_FFS
470 select CPU_USE_DOMAINS if MMU
471 select NEED_KUSER_HELPERS
472 select TLS_REG_EMUL if SMP || !MMU
476 select TLS_REG_EMUL if !CPU_32v6K && !MMU
488 config CPU_ABRT_NOMMU
503 config CPU_ABRT_EV5TJ
512 config CPU_PABRT_LEGACY
525 config CPU_CACHE_V4WT
528 config CPU_CACHE_V4WB
540 config CPU_CACHE_VIVT
543 config CPU_CACHE_VIPT
553 # The copy-page model
560 config CPU_COPY_FEROCEON
569 # This selects the TLB model
573 ARM Architecture Version 4 TLB with writethrough cache.
578 ARM Architecture Version 4 TLB with writeback cache.
583 ARM Architecture Version 4 TLB with writeback cache and invalidate
584 instruction cache entry.
586 config CPU_TLB_FEROCEON
589 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
594 Faraday ARM FA526 architecture, unified TLB with writeback cache
595 and invalidate instruction cache entry. Branch target buffer is
604 config VERIFY_PERMISSION_FAULT
611 This indicates whether the CPU has the ASID register; used to
612 tag TLB and possibly cache entries.
617 Processor has the CP15 register.
623 Processor has the CP15 register, which has MMU related registers.
629 Processor has the CP15 register, which has MPU related registers.
631 config CPU_USE_DOMAINS
634 This option enables or disables the use of domain switching
635 via the set_fs() function.
637 config CPU_V7M_NUM_IRQ
638 int "Number of external interrupts connected to the NVIC"
640 default 90 if ARCH_STM32
641 default 38 if ARCH_EFM32
642 default 112 if SOC_VF610
645 This option indicates the number of interrupts connected to the NVIC.
646 The value can be larger than the real number of interrupts supported
647 by the system, but must not be lower.
648 The default value is 240, corresponding to the maximum number of
649 interrupts supported by the NVIC on Cortex-M family.
651 If unsure, keep default value.
654 # CPU supports 36-bit I/O
659 comment "Processor Features"
662 bool "Support for the Large Physical Address Extension"
663 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
664 !CPU_32v4 && !CPU_32v3
666 Say Y if you have an ARMv7 processor supporting the LPAE page
667 table format and you would like to access memory beyond the
668 4GB limit. The resulting kernel image will not run on
669 processors without the LPA extension.
675 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
677 config ARCH_PHYS_ADDR_T_64BIT
680 config ARCH_DMA_ADDR_T_64BIT
684 bool "Support Thumb user binaries" if !CPU_THUMBONLY && EXPERT
685 depends on CPU_THUMB_CAPABLE
688 Say Y if you want to include kernel support for running user space
691 The Thumb instruction set is a compressed form of the standard ARM
692 instruction set resulting in smaller binaries at the expense of
693 slightly less efficient code.
695 If this option is disabled, and you run userspace that switches to
696 Thumb mode, signal handling will not work correctly, resulting in
697 segmentation faults or illegal instruction aborts.
699 If you don't know what this all is, saying Y is a safe choice.
702 bool "Enable ThumbEE CPU extension"
705 Say Y here if you have a CPU with the ThumbEE extension and code to
706 make use of it. Say N for code that can run on CPUs without ThumbEE.
713 Enable the kernel to make use of the ARM Virtualization
714 Extensions to install hypervisors without run-time firmware
717 A compliant bootloader is required in order to make maximum
718 use of this feature. Refer to Documentation/arm/Booting for
722 bool "Emulate SWP/SWPB instructions" if !SMP
725 select HAVE_PROC_CPU if PROC_FS
727 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
728 ARMv7 multiprocessing extensions introduce the ability to disable
729 these instructions, triggering an undefined instruction exception
730 when executed. Say Y here to enable software emulation of these
731 instructions for userspace (not kernel) using LDREX/STREX.
732 Also creates /proc/cpu/swp_emulation for statistics.
734 In some older versions of glibc [<=2.8] SWP is used during futex
735 trylock() operations with the assumption that the code will not
736 be preempted. This invalid assumption may be more likely to fail
737 with SWP emulation enabled, leading to deadlock of the user
740 NOTE: when accessing uncached shared regions, LDREX/STREX rely
741 on an external transaction monitoring block called a global
742 monitor to maintain update atomicity. If your system does not
743 implement a global monitor, this option can cause programs that
744 perform SWP operations to uncached memory to deadlock.
748 config CPU_BIG_ENDIAN
749 bool "Build big-endian kernel"
750 depends on ARCH_SUPPORTS_BIG_ENDIAN
752 Say Y if you plan on running a kernel in big-endian mode.
753 Note that your board must be properly built and your board
754 port must properly enable any big-endian related features
755 of your chipset/board/processor.
757 config CPU_ENDIAN_BE8
759 depends on CPU_BIG_ENDIAN
760 default CPU_V6 || CPU_V6K || CPU_V7
762 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
764 config CPU_ENDIAN_BE32
766 depends on CPU_BIG_ENDIAN
767 default !CPU_ENDIAN_BE8
769 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
771 config CPU_HIGH_VECTOR
772 depends on !MMU && CPU_CP15 && !CPU_ARM740T
773 bool "Select the High exception vector"
775 Say Y here to select high exception vector(0xFFFF0000~).
776 The exception vector can vary depending on the platform
777 design in nommu mode. If your platform needs to select
778 high exception vector, say Y.
779 Otherwise or if you are unsure, say N, and the low exception
780 vector (0x00000000~) will be used.
782 config CPU_ICACHE_DISABLE
783 bool "Disable I-Cache (I-bit)"
784 depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
786 Say Y here to disable the processor instruction cache. Unless
787 you have a reason not to or are unsure, say N.
789 config CPU_DCACHE_DISABLE
790 bool "Disable D-Cache (C-bit)"
791 depends on (CPU_CP15 && !SMP) || CPU_V7M
793 Say Y here to disable the processor data cache. Unless
794 you have a reason not to or are unsure, say N.
796 config CPU_DCACHE_SIZE
798 depends on CPU_ARM740T || CPU_ARM946E
799 default 0x00001000 if CPU_ARM740T
800 default 0x00002000 # default size for ARM946E-S
802 Some cores are synthesizable to have various sized cache. For
803 ARM946E-S case, it can vary from 0KB to 1MB.
804 To support such cache operations, it is efficient to know the size
806 If your SoC is configured to have a different size, define the value
807 here with proper conditions.
809 config CPU_DCACHE_WRITETHROUGH
810 bool "Force write through D-cache"
811 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
812 default y if CPU_ARM925T
814 Say Y here to use the data cache in writethrough mode. Unless you
815 specifically require this or are unsure, say N.
817 config CPU_CACHE_ROUND_ROBIN
818 bool "Round robin I and D cache replacement algorithm"
819 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
821 Say Y here to use the predictable round-robin cache replacement
822 policy. Unless you specifically require this or are unsure, say N.
824 config CPU_BPREDICT_DISABLE
825 bool "Disable branch prediction"
826 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
828 Say Y here to disable branch prediction. If unsure, say N.
833 config HARDEN_BRANCH_PREDICTOR
834 bool "Harden the branch predictor against aliasing attacks" if EXPERT
835 depends on CPU_SPECTRE
838 Speculation attacks against some high-performance processors rely
839 on being able to manipulate the branch predictor for a victim
840 context by executing aliasing branches in the attacker context.
841 Such attacks can be partially mitigated against by clearing
842 internal branch predictor state and limiting the prediction
843 logic in some situations.
845 This config option will take CPU-specific actions to harden
846 the branch predictor against aliasing attacks and may rely on
847 specific instruction sequences or control bits being set by
854 select NEED_KUSER_HELPERS
856 An SMP system using a pre-ARMv6 processor (there are apparently
857 a few prototypes like that in existence) and therefore access to
858 that required register must be emulated.
860 config NEED_KUSER_HELPERS
864 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
868 Warning: disabling this option may break user programs.
870 Provide kuser helpers in the vector page. The kernel provides
871 helper code to userspace in read only form at a fixed location
872 in the high vector page to allow userspace to be independent of
873 the CPU type fitted to the system. This permits binaries to be
874 run on ARMv4 through to ARMv7 without modification.
876 See Documentation/arm/kernel_user_helpers.txt for details.
878 However, the fixed address nature of these helpers can be used
879 by ROP (return orientated programming) authors when creating
882 If all of the binaries and libraries which run on your platform
883 are built specifically for your platform, and make no use of
884 these helpers, then you can turn this option off to hinder
885 such exploits. However, in that case, if a binary or library
886 relying on those helpers is run, it will receive a SIGILL signal,
887 which will terminate the program.
889 Say N here only if you are absolutely certain that you do not
890 need these helpers; otherwise, the safe option is to say Y.
893 bool "Enable VDSO for acceleration of some system calls"
894 depends on AEABI && MMU && CPU_V7
895 default y if ARM_ARCH_TIMER
896 select GENERIC_TIME_VSYSCALL
898 Place in the process address space an ELF shared object
899 providing fast implementations of gettimeofday and
900 clock_gettime. Systems that implement the ARM architected
901 timer will receive maximum benefit.
903 You must have glibc 2.22 or later for programs to seamlessly
904 take advantage of this.
906 config DMA_CACHE_RWFO
907 bool "Enable read/write for ownership DMA cache maintenance"
908 depends on CPU_V6K && SMP
911 The Snoop Control Unit on ARM11MPCore does not detect the
912 cache maintenance operations and the dma_{map,unmap}_area()
913 functions may leave stale cache entries on other CPUs. By
914 enabling this option, Read or Write For Ownership in the ARMv6
915 DMA cache maintenance functions is performed. These LDR/STR
916 instructions change the cache line state to shared or modified
917 so that the cache operation has the desired effect.
919 Note that the workaround is only valid on processors that do
920 not perform speculative loads into the D-cache. For such
921 processors, if cache maintenance operations are not broadcast
922 in hardware, other workarounds are needed (e.g. cache
923 maintenance broadcasting in software via FIQ).
928 config OUTER_CACHE_SYNC
932 The outer cache has a outer_cache_fns.sync function pointer
933 that can be used to drain the write buffer of the outer cache.
935 config CACHE_FEROCEON_L2
936 bool "Enable the Feroceon L2 cache controller"
937 depends on ARCH_MV78XX0 || ARCH_MVEBU
941 This option enables the Feroceon L2 cache controller.
943 config CACHE_FEROCEON_L2_WRITETHROUGH
944 bool "Force Feroceon L2 cache write through"
945 depends on CACHE_FEROCEON_L2
947 Say Y here to use the Feroceon L2 cache in writethrough mode.
948 Unless you specifically require this, say N for writeback mode.
950 config MIGHT_HAVE_CACHE_L2X0
953 This option should be selected by machines which have a L2x0
954 or PL310 cache controller, but where its use is optional.
956 The only effect of this option is to make CACHE_L2X0 and
957 related options available to the user for configuration.
959 Boards or SoCs which always require the cache controller
960 support to be present should select CACHE_L2X0 directly
961 instead of this option, thus preventing the user from
962 inadvertently configuring a broken kernel.
965 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
966 default MIGHT_HAVE_CACHE_L2X0
968 select OUTER_CACHE_SYNC
970 This option enables the L2x0 PrimeCell.
972 config CACHE_L2X0_PMU
973 bool "L2x0 performance monitor support" if CACHE_L2X0
974 depends on PERF_EVENTS
976 This option enables support for the performance monitoring features
977 of the L220 and PL310 outer cache controllers.
981 config PL310_ERRATA_588369
982 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
984 The PL310 L2 cache controller implements three types of Clean &
985 Invalidate maintenance operations: by Physical Address
986 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
987 They are architecturally defined to behave as the execution of a
988 clean operation followed immediately by an invalidate operation,
989 both performing to the same memory location. This functionality
990 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
991 as clean lines are not invalidated as a result of these operations.
993 config PL310_ERRATA_727915
994 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
996 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
997 operation (offset 0x7FC). This operation runs in background so that
998 PL310 can handle normal accesses while it is in progress. Under very
999 rare circumstances, due to this erratum, write data can be lost when
1000 PL310 treats a cacheable write transaction during a Clean &
1001 Invalidate by Way operation. Revisions prior to r3p1 are affected by
1002 this errata (fixed in r3p1).
1004 config PL310_ERRATA_753970
1005 bool "PL310 errata: cache sync operation may be faulty"
1007 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1009 Under some condition the effect of cache sync operation on
1010 the store buffer still remains when the operation completes.
1011 This means that the store buffer is always asked to drain and
1012 this prevents it from merging any further writes. The workaround
1013 is to replace the normal offset of cache sync operation (0x730)
1014 by another offset targeting an unmapped PL310 register 0x740.
1015 This has the same effect as the cache sync operation: store buffer
1016 drain and waiting for all buffers empty.
1018 config PL310_ERRATA_769419
1019 bool "PL310 errata: no automatic Store Buffer drain"
1021 On revisions of the PL310 prior to r3p2, the Store Buffer does
1022 not automatically drain. This can cause normal, non-cacheable
1023 writes to be retained when the memory system is idle, leading
1024 to suboptimal I/O performance for drivers using coherent DMA.
1025 This option adds a write barrier to the cpu_idle loop so that,
1026 on systems with an outer cache, the store buffer is drained
1031 config CACHE_TAUROS2
1032 bool "Enable the Tauros2 L2 cache controller"
1033 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
1037 This option enables the Tauros2 L2 cache controller (as
1040 config CACHE_UNIPHIER
1041 bool "Enable the UniPhier outer cache controller"
1042 depends on ARCH_UNIPHIER
1043 select ARM_L1_CACHE_SHIFT_7
1045 select OUTER_CACHE_SYNC
1047 This option enables the UniPhier outer cache (system cache)
1051 bool "Enable the L2 cache on XScale3"
1056 This option enables the L2 cache on XScale3.
1058 config ARM_L1_CACHE_SHIFT_6
1062 Setting ARM L1 cache line size to 64 Bytes.
1064 config ARM_L1_CACHE_SHIFT_7
1067 Setting ARM L1 cache line size to 128 Bytes.
1069 config ARM_L1_CACHE_SHIFT
1071 default 7 if ARM_L1_CACHE_SHIFT_7
1072 default 6 if ARM_L1_CACHE_SHIFT_6
1075 config ARM_DMA_MEM_BUFFERABLE
1076 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1077 default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
1079 Historically, the kernel has used strongly ordered mappings to
1080 provide DMA coherent memory. With the advent of ARMv7, mapping
1081 memory with differing types results in unpredictable behaviour,
1082 so on these CPUs, this option is forced on.
1084 Multiple mappings with differing attributes is also unpredictable
1085 on ARMv6 CPUs, but since they do not have aggressive speculative
1086 prefetch, no harm appears to occur.
1088 However, drivers may be missing the necessary barriers for ARMv6,
1089 and therefore turning this on may result in unpredictable driver
1090 behaviour. Therefore, we offer this as an option.
1092 On some of the beefier ARMv7-M machines (with DMA and write
1093 buffers) you likely want this enabled, while those that
1094 didn't need it until now also won't need it in the future.
1096 You are recommended say 'Y' here and debug any affected drivers.
1101 config ARCH_SUPPORTS_BIG_ENDIAN
1104 This option specifies the architecture can support big endian
1107 config DEBUG_ALIGN_RODATA
1108 bool "Make rodata strictly non-executable"
1109 depends on STRICT_KERNEL_RWX
1112 If this is set, rodata will be made explicitly non-executable. This
1113 provides protection on the rare chance that attackers might find and
1114 use ROP gadgets that exist in the rodata section. This adds an
1115 additional section-aligned split of rodata from kernel text so it
1116 can be made explicitly non-executable. This padding may waste memory
1117 space to gain the additional protection.