1 comment "Processor Type"
3 # Select CPU types depending on the architecture selected. This selects
4 # which CPUs we support in the kernel image, and the compiler instruction
14 select CPU_PABRT_LEGACY
16 A 32-bit RISC microprocessor based on the ARM7 processor core
17 which has no memory control unit and cache.
19 Say Y if you want support for the ARM7TDMI processor.
29 select CPU_COPY_V4WT if MMU
31 select CPU_PABRT_LEGACY
32 select CPU_TLB_V4WT if MMU
34 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
35 MMU built around an ARM7TDMI core.
37 Say Y if you want support for the ARM720T processor.
48 select CPU_PABRT_LEGACY
50 A 32-bit RISC processor with 8KB cache or 4KB variants,
51 write buffer and MPU(Protection Unit) built around
54 Say Y if you want support for the ARM740T processor.
64 select CPU_PABRT_LEGACY
66 A 32-bit RISC microprocessor based on the ARM9 processor core
67 which has no memory control unit and cache.
69 Say Y if you want support for the ARM9TDMI processor.
79 select CPU_COPY_V4WB if MMU
81 select CPU_PABRT_LEGACY
82 select CPU_TLB_V4WBI if MMU
84 The ARM920T is licensed to be produced by numerous vendors,
85 and is used in the Cirrus EP93xx and the Samsung S3C2410.
87 Say Y if you want support for the ARM920T processor.
97 select CPU_COPY_V4WB if MMU
99 select CPU_PABRT_LEGACY
100 select CPU_TLB_V4WBI if MMU
102 The ARM922T is a version of the ARM920T, but with smaller
103 instruction and data caches. It is used in Altera's
104 Excalibur XA device family and Micrel's KS8695 Centaur.
106 Say Y if you want support for the ARM922T processor.
114 select CPU_CACHE_V4WT
115 select CPU_CACHE_VIVT
116 select CPU_COPY_V4WB if MMU
118 select CPU_PABRT_LEGACY
119 select CPU_TLB_V4WBI if MMU
121 The ARM925T is a mix between the ARM920T and ARM926T, but with
122 different instruction and data caches. It is used in TI's OMAP
125 Say Y if you want support for the ARM925T processor.
132 select CPU_ABRT_EV5TJ
133 select CPU_CACHE_VIVT
134 select CPU_COPY_V4WB if MMU
136 select CPU_PABRT_LEGACY
137 select CPU_TLB_V4WBI if MMU
139 This is a variant of the ARM920. It has slightly different
140 instruction sequences for cache and TLB operations. Curiously,
141 there is no documentation on it at the ARM corporate website.
143 Say Y if you want support for the ARM926T processor.
152 select CPU_CACHE_VIVT
153 select CPU_COPY_FA if MMU
155 select CPU_PABRT_LEGACY
156 select CPU_TLB_FA if MMU
158 The FA526 is a version of the ARMv4 compatible processor with
159 Branch Target Buffer, Unified TLB and cache line size 16.
161 Say Y if you want support for the FA526 processor.
169 select CPU_ABRT_NOMMU
170 select CPU_CACHE_VIVT
172 select CPU_PABRT_LEGACY
174 ARM940T is a member of the ARM9TDMI family of general-
175 purpose microprocessors with MPU and separate 4KB
176 instruction and 4KB data cases, each with a 4-word line
179 Say Y if you want support for the ARM940T processor.
187 select CPU_ABRT_NOMMU
188 select CPU_CACHE_VIVT
190 select CPU_PABRT_LEGACY
192 ARM946E-S is a member of the ARM9E-S family of high-
193 performance, 32-bit system-on-chip processor solutions.
194 The TCM and ARMv5TE 32-bit instruction set is supported.
196 Say Y if you want support for the ARM946E-S processor.
199 # ARM1020 - needs validating
204 select CPU_CACHE_V4WT
205 select CPU_CACHE_VIVT
206 select CPU_COPY_V4WB if MMU
208 select CPU_PABRT_LEGACY
209 select CPU_TLB_V4WBI if MMU
211 The ARM1020 is the 32K cached version of the ARM10 processor,
212 with an addition of a floating-point unit.
214 Say Y if you want support for the ARM1020 processor.
217 # ARM1020E - needs validating
223 select CPU_CACHE_V4WT
224 select CPU_CACHE_VIVT
225 select CPU_COPY_V4WB if MMU
227 select CPU_PABRT_LEGACY
228 select CPU_TLB_V4WBI if MMU
235 select CPU_CACHE_VIVT
236 select CPU_COPY_V4WB if MMU # can probably do better
238 select CPU_PABRT_LEGACY
239 select CPU_TLB_V4WBI if MMU
241 The ARM1022E is an implementation of the ARMv5TE architecture
242 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
243 embedded trace macrocell, and a floating-point unit.
245 Say Y if you want support for the ARM1022E processor.
252 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
253 select CPU_CACHE_VIVT
254 select CPU_COPY_V4WB if MMU # can probably do better
256 select CPU_PABRT_LEGACY
257 select CPU_TLB_V4WBI if MMU
259 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
260 based upon the ARM10 integer core.
262 Say Y if you want support for the ARM1026EJ-S processor.
268 select CPU_32v3 if ARCH_RPC
269 select CPU_32v4 if !ARCH_RPC
271 select CPU_CACHE_V4WB
272 select CPU_CACHE_VIVT
273 select CPU_COPY_V4WB if MMU
275 select CPU_PABRT_LEGACY
276 select CPU_TLB_V4WB if MMU
278 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
279 is available at five speeds ranging from 100 MHz to 233 MHz.
280 More information is available at
281 <http://developer.intel.com/design/strong/sa110.htm>.
283 Say Y if you want support for the SA-110 processor.
291 select CPU_CACHE_V4WB
292 select CPU_CACHE_VIVT
294 select CPU_PABRT_LEGACY
295 select CPU_TLB_V4WB if MMU
302 select CPU_CACHE_VIVT
304 select CPU_PABRT_LEGACY
305 select CPU_TLB_V4WBI if MMU
307 # XScale Core Version 3
312 select CPU_CACHE_VIVT
314 select CPU_PABRT_LEGACY
315 select CPU_TLB_V4WBI if MMU
318 # Marvell PJ1 (Mohawk)
323 select CPU_CACHE_VIVT
324 select CPU_COPY_V4WB if MMU
326 select CPU_PABRT_LEGACY
327 select CPU_TLB_V4WBI if MMU
334 select CPU_CACHE_VIVT
335 select CPU_COPY_FEROCEON if MMU
337 select CPU_PABRT_LEGACY
338 select CPU_TLB_FEROCEON if MMU
340 config CPU_FEROCEON_OLD_ID
341 bool "Accept early Feroceon cores with an ARM926 ID"
342 depends on CPU_FEROCEON && !CPU_ARM926T
345 This enables the usage of some old Feroceon cores
346 for which the CPU ID is equal to the ARM926 ID.
347 Relevant for Feroceon-1850 and early Feroceon-2850.
365 select CPU_CACHE_VIPT
366 select CPU_COPY_V6 if MMU
368 select CPU_HAS_ASID if MMU
370 select CPU_TLB_V6 if MMU
379 select CPU_CACHE_VIPT
380 select CPU_COPY_V6 if MMU
382 select CPU_HAS_ASID if MMU
384 select CPU_TLB_V6 if MMU
393 select CPU_CACHE_VIPT
394 select CPU_COPY_V6 if MMU
395 select CPU_CP15_MMU if MMU
396 select CPU_CP15_MPU if !MMU
397 select CPU_HAS_ASID if MMU
399 select CPU_SPECTRE if MMU
400 select CPU_TLB_V7 if MMU
406 select CPU_ABRT_NOMMU
409 select CPU_PABRT_LEGACY
414 # There are no CPUs available with MMU that don't implement an ARM ISA:
417 Select this if your CPU doesn't support the 32 bit ARM instructions.
419 # Figure out what processor architecture version we should be using.
420 # This defines the compiler instruction set which depends on the machine type.
423 select CPU_USE_DOMAINS if MMU
424 select NEED_KUSER_HELPERS
425 select TLS_REG_EMUL if SMP || !MMU
426 select CPU_NO_EFFICIENT_FFS
430 select CPU_USE_DOMAINS if MMU
431 select NEED_KUSER_HELPERS
432 select TLS_REG_EMUL if SMP || !MMU
433 select CPU_NO_EFFICIENT_FFS
437 select CPU_USE_DOMAINS if MMU
438 select NEED_KUSER_HELPERS
439 select TLS_REG_EMUL if SMP || !MMU
440 select CPU_NO_EFFICIENT_FFS
444 select CPU_USE_DOMAINS if MMU
445 select NEED_KUSER_HELPERS
446 select TLS_REG_EMUL if SMP || !MMU
450 select TLS_REG_EMUL if !CPU_32v6K && !MMU
462 config CPU_ABRT_NOMMU
477 config CPU_ABRT_EV5TJ
486 config CPU_PABRT_LEGACY
499 config CPU_CACHE_V4WT
502 config CPU_CACHE_V4WB
514 config CPU_CACHE_VIVT
517 config CPU_CACHE_VIPT
527 # The copy-page model
534 config CPU_COPY_FEROCEON
543 # This selects the TLB model
547 ARM Architecture Version 4 TLB with writethrough cache.
552 ARM Architecture Version 4 TLB with writeback cache.
557 ARM Architecture Version 4 TLB with writeback cache and invalidate
558 instruction cache entry.
560 config CPU_TLB_FEROCEON
563 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
568 Faraday ARM FA526 architecture, unified TLB with writeback cache
569 and invalidate instruction cache entry. Branch target buffer is
578 config VERIFY_PERMISSION_FAULT
585 This indicates whether the CPU has the ASID register; used to
586 tag TLB and possibly cache entries.
591 Processor has the CP15 register.
597 Processor has the CP15 register, which has MMU related registers.
603 Processor has the CP15 register, which has MPU related registers.
605 config CPU_USE_DOMAINS
608 This option enables or disables the use of domain switching
609 via the set_fs() function.
611 config CPU_V7M_NUM_IRQ
612 int "Number of external interrupts connected to the NVIC"
614 default 90 if ARCH_STM32
615 default 38 if ARCH_EFM32
616 default 112 if SOC_VF610
619 This option indicates the number of interrupts connected to the NVIC.
620 The value can be larger than the real number of interrupts supported
621 by the system, but must not be lower.
622 The default value is 240, corresponding to the maximum number of
623 interrupts supported by the NVIC on Cortex-M family.
625 If unsure, keep default value.
628 # CPU supports 36-bit I/O
633 comment "Processor Features"
636 bool "Support for the Large Physical Address Extension"
637 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
638 !CPU_32v4 && !CPU_32v3
640 Say Y if you have an ARMv7 processor supporting the LPAE page
641 table format and you would like to access memory beyond the
642 4GB limit. The resulting kernel image will not run on
643 processors without the LPA extension.
649 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
651 config ARCH_PHYS_ADDR_T_64BIT
654 config ARCH_DMA_ADDR_T_64BIT
658 bool "Support Thumb user binaries" if !CPU_THUMBONLY
659 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
660 CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
661 CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
662 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
663 CPU_V7 || CPU_FEROCEON || CPU_V7M
666 Say Y if you want to include kernel support for running user space
669 The Thumb instruction set is a compressed form of the standard ARM
670 instruction set resulting in smaller binaries at the expense of
671 slightly less efficient code.
673 If you don't know what this all is, saying Y is a safe choice.
676 bool "Enable ThumbEE CPU extension"
679 Say Y here if you have a CPU with the ThumbEE extension and code to
680 make use of it. Say N for code that can run on CPUs without ThumbEE.
687 Enable the kernel to make use of the ARM Virtualization
688 Extensions to install hypervisors without run-time firmware
691 A compliant bootloader is required in order to make maximum
692 use of this feature. Refer to Documentation/arm/Booting for
696 bool "Emulate SWP/SWPB instructions" if !SMP
699 select HAVE_PROC_CPU if PROC_FS
701 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
702 ARMv7 multiprocessing extensions introduce the ability to disable
703 these instructions, triggering an undefined instruction exception
704 when executed. Say Y here to enable software emulation of these
705 instructions for userspace (not kernel) using LDREX/STREX.
706 Also creates /proc/cpu/swp_emulation for statistics.
708 In some older versions of glibc [<=2.8] SWP is used during futex
709 trylock() operations with the assumption that the code will not
710 be preempted. This invalid assumption may be more likely to fail
711 with SWP emulation enabled, leading to deadlock of the user
714 NOTE: when accessing uncached shared regions, LDREX/STREX rely
715 on an external transaction monitoring block called a global
716 monitor to maintain update atomicity. If your system does not
717 implement a global monitor, this option can cause programs that
718 perform SWP operations to uncached memory to deadlock.
722 config CPU_BIG_ENDIAN
723 bool "Build big-endian kernel"
724 depends on ARCH_SUPPORTS_BIG_ENDIAN
726 Say Y if you plan on running a kernel in big-endian mode.
727 Note that your board must be properly built and your board
728 port must properly enable any big-endian related features
729 of your chipset/board/processor.
731 config CPU_ENDIAN_BE8
733 depends on CPU_BIG_ENDIAN
734 default CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
736 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
738 config CPU_ENDIAN_BE32
740 depends on CPU_BIG_ENDIAN
741 default !CPU_ENDIAN_BE8
743 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
745 config CPU_HIGH_VECTOR
746 depends on !MMU && CPU_CP15 && !CPU_ARM740T
747 bool "Select the High exception vector"
749 Say Y here to select high exception vector(0xFFFF0000~).
750 The exception vector can vary depending on the platform
751 design in nommu mode. If your platform needs to select
752 high exception vector, say Y.
753 Otherwise or if you are unsure, say N, and the low exception
754 vector (0x00000000~) will be used.
756 config CPU_ICACHE_DISABLE
757 bool "Disable I-Cache (I-bit)"
758 depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
760 Say Y here to disable the processor instruction cache. Unless
761 you have a reason not to or are unsure, say N.
763 config CPU_DCACHE_DISABLE
764 bool "Disable D-Cache (C-bit)"
765 depends on (CPU_CP15 && !SMP) || CPU_V7M
767 Say Y here to disable the processor data cache. Unless
768 you have a reason not to or are unsure, say N.
770 config CPU_DCACHE_SIZE
772 depends on CPU_ARM740T || CPU_ARM946E
773 default 0x00001000 if CPU_ARM740T
774 default 0x00002000 # default size for ARM946E-S
776 Some cores are synthesizable to have various sized cache. For
777 ARM946E-S case, it can vary from 0KB to 1MB.
778 To support such cache operations, it is efficient to know the size
780 If your SoC is configured to have a different size, define the value
781 here with proper conditions.
783 config CPU_DCACHE_WRITETHROUGH
784 bool "Force write through D-cache"
785 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
786 default y if CPU_ARM925T
788 Say Y here to use the data cache in writethrough mode. Unless you
789 specifically require this or are unsure, say N.
791 config CPU_CACHE_ROUND_ROBIN
792 bool "Round robin I and D cache replacement algorithm"
793 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
795 Say Y here to use the predictable round-robin cache replacement
796 policy. Unless you specifically require this or are unsure, say N.
798 config CPU_BPREDICT_DISABLE
799 bool "Disable branch prediction"
800 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
802 Say Y here to disable branch prediction. If unsure, say N.
807 config HARDEN_BRANCH_PREDICTOR
808 bool "Harden the branch predictor against aliasing attacks" if EXPERT
809 depends on CPU_SPECTRE
812 Speculation attacks against some high-performance processors rely
813 on being able to manipulate the branch predictor for a victim
814 context by executing aliasing branches in the attacker context.
815 Such attacks can be partially mitigated against by clearing
816 internal branch predictor state and limiting the prediction
817 logic in some situations.
819 This config option will take CPU-specific actions to harden
820 the branch predictor against aliasing attacks and may rely on
821 specific instruction sequences or control bits being set by
828 select NEED_KUSER_HELPERS
830 An SMP system using a pre-ARMv6 processor (there are apparently
831 a few prototypes like that in existence) and therefore access to
832 that required register must be emulated.
834 config NEED_KUSER_HELPERS
838 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
842 Warning: disabling this option may break user programs.
844 Provide kuser helpers in the vector page. The kernel provides
845 helper code to userspace in read only form at a fixed location
846 in the high vector page to allow userspace to be independent of
847 the CPU type fitted to the system. This permits binaries to be
848 run on ARMv4 through to ARMv7 without modification.
850 See Documentation/arm/kernel_user_helpers.txt for details.
852 However, the fixed address nature of these helpers can be used
853 by ROP (return orientated programming) authors when creating
856 If all of the binaries and libraries which run on your platform
857 are built specifically for your platform, and make no use of
858 these helpers, then you can turn this option off to hinder
859 such exploits. However, in that case, if a binary or library
860 relying on those helpers is run, it will receive a SIGILL signal,
861 which will terminate the program.
863 Say N here only if you are absolutely certain that you do not
864 need these helpers; otherwise, the safe option is to say Y.
867 bool "Enable VDSO for acceleration of some system calls"
868 depends on AEABI && MMU && CPU_V7
869 default y if ARM_ARCH_TIMER
870 select GENERIC_TIME_VSYSCALL
872 Place in the process address space an ELF shared object
873 providing fast implementations of gettimeofday and
874 clock_gettime. Systems that implement the ARM architected
875 timer will receive maximum benefit.
877 You must have glibc 2.22 or later for programs to seamlessly
878 take advantage of this.
880 config DMA_CACHE_RWFO
881 bool "Enable read/write for ownership DMA cache maintenance"
882 depends on CPU_V6K && SMP
885 The Snoop Control Unit on ARM11MPCore does not detect the
886 cache maintenance operations and the dma_{map,unmap}_area()
887 functions may leave stale cache entries on other CPUs. By
888 enabling this option, Read or Write For Ownership in the ARMv6
889 DMA cache maintenance functions is performed. These LDR/STR
890 instructions change the cache line state to shared or modified
891 so that the cache operation has the desired effect.
893 Note that the workaround is only valid on processors that do
894 not perform speculative loads into the D-cache. For such
895 processors, if cache maintenance operations are not broadcast
896 in hardware, other workarounds are needed (e.g. cache
897 maintenance broadcasting in software via FIQ).
902 config OUTER_CACHE_SYNC
906 The outer cache has a outer_cache_fns.sync function pointer
907 that can be used to drain the write buffer of the outer cache.
909 config CACHE_FEROCEON_L2
910 bool "Enable the Feroceon L2 cache controller"
911 depends on ARCH_MV78XX0 || ARCH_MVEBU
915 This option enables the Feroceon L2 cache controller.
917 config CACHE_FEROCEON_L2_WRITETHROUGH
918 bool "Force Feroceon L2 cache write through"
919 depends on CACHE_FEROCEON_L2
921 Say Y here to use the Feroceon L2 cache in writethrough mode.
922 Unless you specifically require this, say N for writeback mode.
924 config MIGHT_HAVE_CACHE_L2X0
927 This option should be selected by machines which have a L2x0
928 or PL310 cache controller, but where its use is optional.
930 The only effect of this option is to make CACHE_L2X0 and
931 related options available to the user for configuration.
933 Boards or SoCs which always require the cache controller
934 support to be present should select CACHE_L2X0 directly
935 instead of this option, thus preventing the user from
936 inadvertently configuring a broken kernel.
939 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
940 default MIGHT_HAVE_CACHE_L2X0
942 select OUTER_CACHE_SYNC
944 This option enables the L2x0 PrimeCell.
946 config CACHE_L2X0_PMU
947 bool "L2x0 performance monitor support" if CACHE_L2X0
948 depends on PERF_EVENTS
950 This option enables support for the performance monitoring features
951 of the L220 and PL310 outer cache controllers.
955 config PL310_ERRATA_588369
956 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
958 The PL310 L2 cache controller implements three types of Clean &
959 Invalidate maintenance operations: by Physical Address
960 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
961 They are architecturally defined to behave as the execution of a
962 clean operation followed immediately by an invalidate operation,
963 both performing to the same memory location. This functionality
964 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
965 as clean lines are not invalidated as a result of these operations.
967 config PL310_ERRATA_727915
968 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
970 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
971 operation (offset 0x7FC). This operation runs in background so that
972 PL310 can handle normal accesses while it is in progress. Under very
973 rare circumstances, due to this erratum, write data can be lost when
974 PL310 treats a cacheable write transaction during a Clean &
975 Invalidate by Way operation. Revisions prior to r3p1 are affected by
976 this errata (fixed in r3p1).
978 config PL310_ERRATA_753970
979 bool "PL310 errata: cache sync operation may be faulty"
981 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
983 Under some condition the effect of cache sync operation on
984 the store buffer still remains when the operation completes.
985 This means that the store buffer is always asked to drain and
986 this prevents it from merging any further writes. The workaround
987 is to replace the normal offset of cache sync operation (0x730)
988 by another offset targeting an unmapped PL310 register 0x740.
989 This has the same effect as the cache sync operation: store buffer
990 drain and waiting for all buffers empty.
992 config PL310_ERRATA_769419
993 bool "PL310 errata: no automatic Store Buffer drain"
995 On revisions of the PL310 prior to r3p2, the Store Buffer does
996 not automatically drain. This can cause normal, non-cacheable
997 writes to be retained when the memory system is idle, leading
998 to suboptimal I/O performance for drivers using coherent DMA.
999 This option adds a write barrier to the cpu_idle loop so that,
1000 on systems with an outer cache, the store buffer is drained
1005 config CACHE_TAUROS2
1006 bool "Enable the Tauros2 L2 cache controller"
1007 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
1011 This option enables the Tauros2 L2 cache controller (as
1014 config CACHE_UNIPHIER
1015 bool "Enable the UniPhier outer cache controller"
1016 depends on ARCH_UNIPHIER
1019 select OUTER_CACHE_SYNC
1021 This option enables the UniPhier outer cache (system cache)
1025 bool "Enable the L2 cache on XScale3"
1030 This option enables the L2 cache on XScale3.
1032 config ARM_L1_CACHE_SHIFT_6
1036 Setting ARM L1 cache line size to 64 Bytes.
1038 config ARM_L1_CACHE_SHIFT
1040 default 6 if ARM_L1_CACHE_SHIFT_6
1043 config ARM_DMA_MEM_BUFFERABLE
1044 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
1045 default y if CPU_V6 || CPU_V6K || CPU_V7
1047 Historically, the kernel has used strongly ordered mappings to
1048 provide DMA coherent memory. With the advent of ARMv7, mapping
1049 memory with differing types results in unpredictable behaviour,
1050 so on these CPUs, this option is forced on.
1052 Multiple mappings with differing attributes is also unpredictable
1053 on ARMv6 CPUs, but since they do not have aggressive speculative
1054 prefetch, no harm appears to occur.
1056 However, drivers may be missing the necessary barriers for ARMv6,
1057 and therefore turning this on may result in unpredictable driver
1058 behaviour. Therefore, we offer this as an option.
1060 You are recommended say 'Y' here and debug any affected drivers.
1065 config ARCH_SUPPORTS_BIG_ENDIAN
1068 This option specifies the architecture can support big endian
1072 bool "Make kernel text and rodata read-only"
1073 depends on MMU && !XIP_KERNEL
1076 If this is set, kernel text and rodata memory will be made
1077 read-only, and non-text kernel memory will be made non-executable.
1078 The tradeoff is that each region is padded to section-size (1MiB)
1079 boundaries (because their permissions are different and splitting
1080 the 1M pages into 4K ones causes TLB performance problems), which
1083 config DEBUG_ALIGN_RODATA
1084 bool "Make rodata strictly non-executable"
1085 depends on DEBUG_RODATA
1088 If this is set, rodata will be made explicitly non-executable. This
1089 provides protection on the rare chance that attackers might find and
1090 use ROP gadgets that exist in the rodata section. This adds an
1091 additional section-aligned split of rodata from kernel text so it
1092 can be made explicitly non-executable. This padding may waste memory
1093 space to gain the additional protection.