1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
6 #include <linux/linkage.h>
8 #include <soc/tegra/flowctrl.h>
9 #include <soc/tegra/fuse.h>
11 #include <asm/asm-offsets.h>
12 #include <asm/assembler.h>
13 #include <asm/cache.h>
19 #define EMC_ADR_CFG 0x10
20 #define EMC_TIMING_CONTROL 0x28
22 #define EMC_SELF_REF 0xe0
24 #define EMC_FBIO_CFG5 0x104
25 #define EMC_AUTO_CAL_CONFIG 0x2a4
26 #define EMC_AUTO_CAL_INTERVAL 0x2a8
27 #define EMC_AUTO_CAL_STATUS 0x2ac
28 #define EMC_REQ_CTRL 0x2b0
29 #define EMC_CFG_DIG_DLL 0x2bc
30 #define EMC_EMC_STATUS 0x2b4
31 #define EMC_ZCAL_INTERVAL 0x2e0
32 #define EMC_ZQ_CAL 0x2ec
33 #define EMC_XM2VTTGENPADCTRL 0x310
34 #define EMC_XM2VTTGENPADCTRL2 0x314
37 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
39 #define PMC_PLLP_WB0_OVERRIDE 0xf8
40 #define PMC_IO_DPD_REQ 0x1b8
41 #define PMC_IO_DPD_STATUS 0x1bc
43 #define CLK_RESET_CCLK_BURST 0x20
44 #define CLK_RESET_CCLK_DIVIDER 0x24
45 #define CLK_RESET_SCLK_BURST 0x28
46 #define CLK_RESET_SCLK_DIVIDER 0x2c
48 #define CLK_RESET_PLLC_BASE 0x80
49 #define CLK_RESET_PLLC_MISC 0x8c
50 #define CLK_RESET_PLLM_BASE 0x90
51 #define CLK_RESET_PLLM_MISC 0x9c
52 #define CLK_RESET_PLLP_BASE 0xa0
53 #define CLK_RESET_PLLP_MISC 0xac
54 #define CLK_RESET_PLLA_BASE 0xb0
55 #define CLK_RESET_PLLA_MISC 0xbc
56 #define CLK_RESET_PLLX_BASE 0xe0
57 #define CLK_RESET_PLLX_MISC 0xe4
58 #define CLK_RESET_PLLX_MISC3 0x518
59 #define CLK_RESET_PLLX_MISC3_IDDQ 3
60 #define CLK_RESET_PLLM_MISC_IDDQ 5
61 #define CLK_RESET_PLLC_MISC_IDDQ 26
63 #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
65 #define MSELECT_CLKM (0x3 << 30)
67 #define LOCK_DELAY 50 /* safety delay after lock is detected */
69 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
71 .macro emc_device_mask, rd, base
72 ldr \rd, [\base, #EMC_ADR_CFG]
74 moveq \rd, #(0x1 << 8) @ just 1 device
75 movne \rd, #(0x3 << 8) @ 2 devices
78 .macro emc_timing_update, rd, base
80 str \rd, [\base, #EMC_TIMING_CONTROL]
82 ldr \rd, [\base, #EMC_EMC_STATUS]
83 tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
87 .macro pll_enable, rd, r_car_base, pll_base, pll_misc
88 ldr \rd, [\r_car_base, #\pll_base]
90 orreq \rd, \rd, #(1 << 30)
91 streq \rd, [\r_car_base, #\pll_base]
92 /* Enable lock detector */
94 ldr \rd, [\r_car_base, #\pll_misc]
95 bic \rd, \rd, #(1 << 18)
96 str \rd, [\r_car_base, #\pll_misc]
97 ldr \rd, [\r_car_base, #\pll_misc]
98 ldr \rd, [\r_car_base, #\pll_misc]
99 orr \rd, \rd, #(1 << 18)
100 str \rd, [\r_car_base, #\pll_misc]
104 .macro pll_locked, rd, r_car_base, pll_base
106 ldr \rd, [\r_car_base, #\pll_base]
111 .macro pll_iddq_exit, rd, car, iddq, iddq_bit
112 ldr \rd, [\car, #\iddq]
113 bic \rd, \rd, #(1<<\iddq_bit)
114 str \rd, [\car, #\iddq]
117 .macro pll_iddq_entry, rd, car, iddq, iddq_bit
118 ldr \rd, [\car, #\iddq]
119 orr \rd, \rd, #(1<<\iddq_bit)
120 str \rd, [\car, #\iddq]
123 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
125 * tegra30_hotplug_shutdown(void)
127 * Powergates the current CPU.
128 * Should never return.
130 ENTRY(tegra30_hotplug_shutdown)
131 /* Powergate this CPU */
132 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
133 bl tegra30_cpu_shutdown
134 ret lr @ should never get here
135 ENDPROC(tegra30_hotplug_shutdown)
138 * tegra30_cpu_shutdown(unsigned long flags)
140 * Puts the current CPU in wait-for-event mode on the flow controller
141 * and powergates it -- flags (in R0) indicate the request type.
144 * corrupts r0-r4, r10-r12
146 ENTRY(tegra30_cpu_shutdown)
148 tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
150 bne _no_cpu0_chk @ It's not Tegra30
153 reteq lr @ Must never be called for CPU 0
156 ldr r12, =TEGRA_FLOW_CTRL_VIRT
157 cpu_to_csr_reg r1, r3
158 add r1, r1, r12 @ virtual CSR address for this CPU
159 cpu_to_halt_reg r2, r3
160 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
163 * Clear this CPU's "event" and "interrupt" flags and power gate
164 * it when halting but not before it is in the "WFE" state.
167 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
170 moveq r4, #(1 << 4) @ wfe bitmap
171 movne r4, #(1 << 8) @ wfi bitmap
172 ARM( orr r12, r12, r4, lsl r3 )
173 THUMB( lsl r4, r4, r3 )
174 THUMB( orr r12, r12, r4 )
180 subs r3, r3, #1 @ delay as a part of wfe war.
182 cpsid a @ disable imprecise aborts.
183 ldr r3, [r1] @ read CSR
184 str r3, [r1] @ clear CSR
186 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
187 beq flow_ctrl_setting_for_lp2
189 /* flow controller set up for hotplug */
190 mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug
192 flow_ctrl_setting_for_lp2:
193 /* flow controller set up for LP2 */
195 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
196 movne r3, #FLOW_CTRL_WAITEVENT
197 orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
198 orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
208 wfeeq @ CPU should be power gated here
214 * 38 nop's, which fills rest of wfe cache line and
215 * 4 more cachelines with nop
220 b . @ should never get here
222 ENDPROC(tegra30_cpu_shutdown)
225 #ifdef CONFIG_PM_SLEEP
227 * tegra30_sleep_core_finish(unsigned long v2p)
229 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
230 * tegra30_tear_down_core in IRAM
232 ENTRY(tegra30_sleep_core_finish)
234 /* Flush, disable the L1 data cache and exit SMP */
235 mov r0, #TEGRA_FLUSH_CACHE_ALL
236 bl tegra_disable_clean_inv_dcache
240 * Preload all the address literals that are needed for the
241 * CPU power-gating process, to avoid loading from SDRAM which
242 * are not supported once SDRAM is put into self-refresh.
243 * LP0 / LP1 use physical address, since the MMU needs to be
244 * disabled before putting SDRAM into self-refresh to avoid
245 * memory access due to page table walks.
247 mov32 r4, TEGRA_PMC_BASE
248 mov32 r5, TEGRA_CLK_RESET_BASE
249 mov32 r6, TEGRA_FLOW_CTRL_BASE
250 mov32 r7, TEGRA_TMRUS_BASE
252 mov32 r3, tegra_shut_off_mmu
255 mov32 r0, tegra30_tear_down_core
256 mov32 r1, tegra30_iram_start
258 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
262 ENDPROC(tegra30_sleep_core_finish)
265 * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
267 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
269 ENTRY(tegra30_sleep_cpu_secondary_finish)
272 /* Flush and disable the L1 data cache */
273 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
274 bl tegra_disable_clean_inv_dcache
276 /* Powergate this CPU. */
277 mov r0, #0 @ power mode flags (!hotplug)
278 bl tegra30_cpu_shutdown
279 mov r0, #1 @ never return here
281 ENDPROC(tegra30_sleep_cpu_secondary_finish)
284 * tegra30_tear_down_cpu
286 * Switches the CPU to enter sleep.
288 ENTRY(tegra30_tear_down_cpu)
289 mov32 r6, TEGRA_FLOW_CTRL_BASE
291 b tegra30_enter_sleep
292 ENDPROC(tegra30_tear_down_cpu)
294 /* START OF ROUTINES COPIED TO IRAM */
295 .align L1_CACHE_SHIFT
296 .globl tegra30_iram_start
302 * reset vector for LP1 restore; copied into IRAM during suspend.
303 * Brings the system back up to a safe staring point (SDRAM out of
304 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
305 * system clock running on the same PLL that it suspended at), and
306 * jumps to tegra_resume to restore virtual addressing.
307 * The physical address of tegra_resume expected to be stored in
310 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
312 ENTRY(tegra30_lp1_reset)
314 * The CPU and system bus are running at 32KHz and executing from
315 * IRAM when this code is executed; immediately switch to CLKM and
316 * enable PLLP, PLLM, PLLC, PLLA and PLLX.
318 mov32 r0, TEGRA_CLK_RESET_BASE
321 str r1, [r0, #CLK_RESET_SCLK_BURST]
322 str r1, [r0, #CLK_RESET_CCLK_BURST]
324 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
325 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
327 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
329 beq _no_pll_iddq_exit
331 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
332 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
333 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
335 mov32 r7, TEGRA_TMRUS_BASE
338 wait_until r1, r7, r3
340 /* enable PLLM via PMC */
341 mov32 r2, TEGRA_PMC_BASE
342 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
343 orr r1, r1, #(1 << 12)
344 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
346 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
347 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
348 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
353 /* enable PLLM via PMC */
354 mov32 r2, TEGRA_PMC_BASE
355 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
356 orr r1, r1, #(1 << 12)
357 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
359 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
360 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
361 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
364 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
365 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
367 pll_locked r1, r0, CLK_RESET_PLLM_BASE
368 pll_locked r1, r0, CLK_RESET_PLLP_BASE
369 pll_locked r1, r0, CLK_RESET_PLLA_BASE
370 pll_locked r1, r0, CLK_RESET_PLLC_BASE
371 pll_locked r1, r0, CLK_RESET_PLLX_BASE
373 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
376 ldr r1, [r0, #CLK_RESET_PLLP_BASE]
377 bic r1, r1, #(1<<31) @ disable PllP bypass
378 str r1, [r0, #CLK_RESET_PLLP_BASE]
381 mov32 r7, TEGRA_TMRUS_BASE
383 add r1, r1, #LOCK_DELAY
384 wait_until r1, r7, r3
386 adr r5, tegra_sdram_pad_save
388 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
389 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
391 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
392 str r4, [r0, #CLK_RESET_SCLK_BURST]
395 movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX
396 movteq r4, #:upper16:((1 << 28) | (0x8))
397 movwne r4, #:lower16:((1 << 28) | (0xe))
398 movtne r4, #:upper16:((1 << 28) | (0xe))
399 str r4, [r0, #CLK_RESET_CCLK_BURST]
401 /* Restore pad power state to normal */
402 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
404 bic r1, r1, #(1 << 31)
405 orr r1, r1, #(1 << 30)
406 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
409 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
410 movteq r0, #:upper16:TEGRA_EMC_BASE
412 movweq r0, #:lower16:TEGRA_EMC0_BASE
413 movteq r0, #:upper16:TEGRA_EMC0_BASE
415 movweq r0, #:lower16:TEGRA124_EMC_BASE
416 movteq r0, #:upper16:TEGRA124_EMC_BASE
419 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
420 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
421 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
422 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
423 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
424 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
427 ldr r1, [r0, #EMC_CFG_DIG_DLL]
428 orr r1, r1, #(1 << 30) @ set DLL_RESET
429 str r1, [r0, #EMC_CFG_DIG_DLL]
431 emc_timing_update r1, r0
434 movweq r1, #:lower16:TEGRA_EMC1_BASE
435 movteq r1, #:upper16:TEGRA_EMC1_BASE
438 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
439 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
440 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
441 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
443 emc_wait_auto_cal_onetime:
444 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
445 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
446 bne emc_wait_auto_cal_onetime
448 ldr r1, [r0, #EMC_CFG]
449 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
450 str r1, [r0, #EMC_CFG]
453 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
456 streq r1, [r0, #EMC_NOP]
457 streq r1, [r0, #EMC_NOP]
459 emc_device_mask r1, r0
461 exit_selfrefresh_loop:
462 ldr r2, [r0, #EMC_EMC_STATUS]
464 bne exit_selfrefresh_loop
466 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
468 mov32 r7, TEGRA_TMRUS_BASE
469 ldr r2, [r0, #EMC_FBIO_CFG5]
471 and r2, r2, #3 @ check DRAM_TYPE
475 /* Issue a ZQ_CAL for dev0 - DDR3 */
476 mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1
477 str r2, [r0, #EMC_ZQ_CAL]
480 wait_until r2, r7, r3
485 /* Issue a ZQ_CAL for dev1 - DDR3 */
486 mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1
487 str r2, [r0, #EMC_ZQ_CAL]
490 wait_until r2, r7, r3
494 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
495 mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB
496 str r2, [r0, #EMC_MRW]
499 wait_until r2, r7, r3
504 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
505 mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB
506 str r2, [r0, #EMC_MRW]
509 wait_until r2, r7, r3
512 mov r1, #0 @ unstall all transactions
513 str r1, [r0, #EMC_REQ_CTRL]
514 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
515 str r1, [r0, #EMC_ZCAL_INTERVAL]
516 ldr r1, [r5, #0x0] @ restore EMC_CFG
517 str r1, [r0, #EMC_CFG]
519 emc_timing_update r1, r0
521 /* Tegra114 had dual EMC channel, now config the other one */
523 bne __no_dual_emc_chanl
524 mov32 r1, TEGRA_EMC1_BASE
528 bne exit_self_refresh
531 mov32 r0, TEGRA_PMC_BASE
532 ldr r0, [r0, #PMC_SCRATCH41]
533 ret r0 @ jump to tegra_resume
534 ENDPROC(tegra30_lp1_reset)
536 .align L1_CACHE_SHIFT
537 tegra30_sdram_pad_address:
538 .word TEGRA_EMC_BASE + EMC_CFG @0x0
539 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
540 .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
541 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
542 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
543 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
544 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
545 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
546 tegra30_sdram_pad_address_end:
548 tegra114_sdram_pad_address:
549 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
550 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
551 .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8
552 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc
553 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
554 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
555 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
556 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
557 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
558 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
559 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
560 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
561 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
562 tegra114_sdram_pad_adress_end:
564 tegra124_sdram_pad_address:
565 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
566 .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
567 .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
568 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
569 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
570 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
571 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
572 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
573 tegra124_sdram_pad_address_end:
575 tegra30_sdram_pad_size:
576 .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
578 tegra114_sdram_pad_size:
579 .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
581 .type tegra_sdram_pad_save, %object
582 tegra_sdram_pad_save:
583 .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
588 * tegra30_tear_down_core
590 * copied into and executed from IRAM
591 * puts memory in self-refresh for LP0 and LP1
593 tegra30_tear_down_core:
594 bl tegra30_sdram_self_refresh
595 bl tegra30_switch_cpu_to_clk32k
596 b tegra30_enter_sleep
599 * tegra30_switch_cpu_to_clk32k
601 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
602 * to the 32KHz clock.
603 * r4 = TEGRA_PMC_BASE
604 * r5 = TEGRA_CLK_RESET_BASE
605 * r6 = TEGRA_FLOW_CTRL_BASE
606 * r7 = TEGRA_TMRUS_BASE
609 tegra30_switch_cpu_to_clk32k:
611 * start by jumping to CLKM to safely disable PLLs, then jump to
615 str r0, [r5, #CLK_RESET_SCLK_BURST]
616 /* 2uS delay delay between changing SCLK and CCLK */
619 wait_until r1, r7, r9
620 str r0, [r5, #CLK_RESET_CCLK_BURST]
622 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
623 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
625 /* switch the clock source of mselect to be CLK_M */
626 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
627 orr r0, r0, #MSELECT_CLKM
628 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
630 /* 2uS delay delay between changing SCLK and disabling PLLs */
633 wait_until r1, r7, r9
635 /* disable PLLM via PMC in LP1 */
636 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
637 bic r0, r0, #(1 << 12)
638 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
640 /* disable PLLP, PLLA, PLLC and PLLX */
641 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
643 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
644 orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
645 bic r0, r0, #(1 << 30)
646 str r0, [r5, #CLK_RESET_PLLP_BASE]
647 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
648 bic r0, r0, #(1 << 30)
649 str r0, [r5, #CLK_RESET_PLLA_BASE]
650 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
651 bic r0, r0, #(1 << 30)
652 str r0, [r5, #CLK_RESET_PLLC_BASE]
653 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
654 bic r0, r0, #(1 << 30)
655 str r0, [r5, #CLK_RESET_PLLX_BASE]
659 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
663 mov r0, #0 /* brust policy = 32KHz */
664 str r0, [r5, #CLK_RESET_SCLK_BURST]
669 * tegra30_enter_sleep
671 * uses flow controller to enter sleep state
672 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
673 * executes from SDRAM with target state is LP2
674 * r6 = TEGRA_FLOW_CTRL_BASE
679 cpu_to_csr_reg r2, r1
681 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
682 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
685 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
687 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
688 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
689 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
691 cpu_to_halt_reg r2, r1
694 ldr r0, [r6, r2] /* memory barrier */
699 wfi /* CPU should be power gated here */
701 /* !!!FIXME!!! Implement halt failure handler */
705 * tegra30_sdram_self_refresh
707 * called with MMU off and caches disabled
708 * must be executed from IRAM
709 * r4 = TEGRA_PMC_BASE
710 * r5 = TEGRA_CLK_RESET_BASE
711 * r6 = TEGRA_FLOW_CTRL_BASE
712 * r7 = TEGRA_TMRUS_BASE
715 tegra30_sdram_self_refresh:
717 adr r8, tegra_sdram_pad_save
718 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
720 adreq r2, tegra30_sdram_pad_address
721 ldreq r3, tegra30_sdram_pad_size
723 adreq r2, tegra114_sdram_pad_address
724 ldreq r3, tegra114_sdram_pad_size
726 adreq r2, tegra124_sdram_pad_address
727 ldreq r3, tegra30_sdram_pad_size
732 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
735 str r1, [r8, r9] @ save the content of the addr
745 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
747 ldreq r0, =TEGRA_EMC0_BASE
749 ldreq r0, =TEGRA124_EMC_BASE
754 str r1, [r0, #EMC_ZCAL_INTERVAL]
755 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
756 ldr r1, [r0, #EMC_CFG]
757 bic r1, r1, #(1 << 28)
758 bicne r1, r1, #(1 << 29)
759 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
761 emc_timing_update r1, r0
765 wait_until r1, r7, r2
768 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
769 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
770 bne emc_wait_auto_cal
773 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
776 ldr r1, [r0, #EMC_EMC_STATUS]
781 str r1, [r0, #EMC_SELF_REF]
783 emc_device_mask r1, r0
786 ldr r2, [r0, #EMC_EMC_STATUS]
789 bne emcself @ loop until DDR in self-refresh
791 /* Put VTTGEN in the lowest power mode */
792 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
793 mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
795 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
796 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
798 orreq r1, r1, #7 @ set E_NO_VTTGEN
800 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
802 emc_timing_update r1, r0
804 /* Tegra114 had dual EMC channel, now config the other one */
806 bne no_dual_emc_chanl
807 mov32 r1, TEGRA_EMC1_BASE
810 bne enter_self_refresh
813 ldr r1, [r4, #PMC_CTRL]
814 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
817 * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
818 * and COMP in the lowest power mode when LP1.
821 str r1, [r4, #PMC_IO_DPD_REQ]
829 /* dummy symbol for end of IRAM */
830 .align L1_CACHE_SHIFT
831 .global tegra30_iram_end