2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/linkage.h>
19 #include <soc/tegra/fuse.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/assembler.h>
23 #include <asm/cache.h>
30 #define EMC_ADR_CFG 0x10
31 #define EMC_TIMING_CONTROL 0x28
32 #define EMC_REFRESH 0x70
34 #define EMC_SELF_REF 0xe0
36 #define EMC_FBIO_CFG5 0x104
37 #define EMC_AUTO_CAL_CONFIG 0x2a4
38 #define EMC_AUTO_CAL_INTERVAL 0x2a8
39 #define EMC_AUTO_CAL_STATUS 0x2ac
40 #define EMC_REQ_CTRL 0x2b0
41 #define EMC_CFG_DIG_DLL 0x2bc
42 #define EMC_EMC_STATUS 0x2b4
43 #define EMC_ZCAL_INTERVAL 0x2e0
44 #define EMC_ZQ_CAL 0x2ec
45 #define EMC_XM2VTTGENPADCTRL 0x310
46 #define EMC_XM2VTTGENPADCTRL2 0x314
49 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
51 #define PMC_PLLP_WB0_OVERRIDE 0xf8
52 #define PMC_IO_DPD_REQ 0x1b8
53 #define PMC_IO_DPD_STATUS 0x1bc
55 #define CLK_RESET_CCLK_BURST 0x20
56 #define CLK_RESET_CCLK_DIVIDER 0x24
57 #define CLK_RESET_SCLK_BURST 0x28
58 #define CLK_RESET_SCLK_DIVIDER 0x2c
60 #define CLK_RESET_PLLC_BASE 0x80
61 #define CLK_RESET_PLLC_MISC 0x8c
62 #define CLK_RESET_PLLM_BASE 0x90
63 #define CLK_RESET_PLLM_MISC 0x9c
64 #define CLK_RESET_PLLP_BASE 0xa0
65 #define CLK_RESET_PLLP_MISC 0xac
66 #define CLK_RESET_PLLA_BASE 0xb0
67 #define CLK_RESET_PLLA_MISC 0xbc
68 #define CLK_RESET_PLLX_BASE 0xe0
69 #define CLK_RESET_PLLX_MISC 0xe4
70 #define CLK_RESET_PLLX_MISC3 0x518
71 #define CLK_RESET_PLLX_MISC3_IDDQ 3
72 #define CLK_RESET_PLLM_MISC_IDDQ 5
73 #define CLK_RESET_PLLC_MISC_IDDQ 26
75 #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
77 #define MSELECT_CLKM (0x3 << 30)
79 #define LOCK_DELAY 50 /* safety delay after lock is detected */
81 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
83 .macro emc_device_mask, rd, base
84 ldr \rd, [\base, #EMC_ADR_CFG]
86 moveq \rd, #(0x1 << 8) @ just 1 device
87 movne \rd, #(0x3 << 8) @ 2 devices
90 .macro emc_timing_update, rd, base
92 str \rd, [\base, #EMC_TIMING_CONTROL]
94 ldr \rd, [\base, #EMC_EMC_STATUS]
95 tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
99 .macro pll_enable, rd, r_car_base, pll_base, pll_misc
100 ldr \rd, [\r_car_base, #\pll_base]
102 orreq \rd, \rd, #(1 << 30)
103 streq \rd, [\r_car_base, #\pll_base]
104 /* Enable lock detector */
106 ldr \rd, [\r_car_base, #\pll_misc]
107 bic \rd, \rd, #(1 << 18)
108 str \rd, [\r_car_base, #\pll_misc]
109 ldr \rd, [\r_car_base, #\pll_misc]
110 ldr \rd, [\r_car_base, #\pll_misc]
111 orr \rd, \rd, #(1 << 18)
112 str \rd, [\r_car_base, #\pll_misc]
116 .macro pll_locked, rd, r_car_base, pll_base
118 ldr \rd, [\r_car_base, #\pll_base]
123 .macro pll_iddq_exit, rd, car, iddq, iddq_bit
124 ldr \rd, [\car, #\iddq]
125 bic \rd, \rd, #(1<<\iddq_bit)
126 str \rd, [\car, #\iddq]
129 .macro pll_iddq_entry, rd, car, iddq, iddq_bit
130 ldr \rd, [\car, #\iddq]
131 orr \rd, \rd, #(1<<\iddq_bit)
132 str \rd, [\car, #\iddq]
135 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
137 * tegra30_hotplug_shutdown(void)
139 * Powergates the current CPU.
140 * Should never return.
142 ENTRY(tegra30_hotplug_shutdown)
143 /* Powergate this CPU */
144 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
145 bl tegra30_cpu_shutdown
146 ret lr @ should never get here
147 ENDPROC(tegra30_hotplug_shutdown)
150 * tegra30_cpu_shutdown(unsigned long flags)
152 * Puts the current CPU in wait-for-event mode on the flow controller
153 * and powergates it -- flags (in R0) indicate the request type.
156 * corrupts r0-r4, r10-r12
158 ENTRY(tegra30_cpu_shutdown)
160 tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
162 bne _no_cpu0_chk @ It's not Tegra30
165 reteq lr @ Must never be called for CPU 0
168 ldr r12, =TEGRA_FLOW_CTRL_VIRT
169 cpu_to_csr_reg r1, r3
170 add r1, r1, r12 @ virtual CSR address for this CPU
171 cpu_to_halt_reg r2, r3
172 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
175 * Clear this CPU's "event" and "interrupt" flags and power gate
176 * it when halting but not before it is in the "WFE" state.
179 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
182 moveq r4, #(1 << 4) @ wfe bitmap
183 movne r4, #(1 << 8) @ wfi bitmap
184 ARM( orr r12, r12, r4, lsl r3 )
185 THUMB( lsl r4, r4, r3 )
186 THUMB( orr r12, r12, r4 )
192 subs r3, r3, #1 @ delay as a part of wfe war.
194 cpsid a @ disable imprecise aborts.
195 ldr r3, [r1] @ read CSR
196 str r3, [r1] @ clear CSR
198 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
199 beq flow_ctrl_setting_for_lp2
201 /* flow controller set up for hotplug */
202 mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug
204 flow_ctrl_setting_for_lp2:
205 /* flow controller set up for LP2 */
207 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
208 movne r3, #FLOW_CTRL_WAITEVENT
209 orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
210 orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
220 wfeeq @ CPU should be power gated here
226 * 38 nop's, which fills rest of wfe cache line and
227 * 4 more cachelines with nop
232 b . @ should never get here
234 ENDPROC(tegra30_cpu_shutdown)
237 #ifdef CONFIG_PM_SLEEP
239 * tegra30_sleep_core_finish(unsigned long v2p)
241 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
242 * tegra30_tear_down_core in IRAM
244 ENTRY(tegra30_sleep_core_finish)
245 /* Flush, disable the L1 data cache and exit SMP */
246 bl tegra_disable_clean_inv_dcache
249 * Preload all the address literals that are needed for the
250 * CPU power-gating process, to avoid loading from SDRAM which
251 * are not supported once SDRAM is put into self-refresh.
252 * LP0 / LP1 use physical address, since the MMU needs to be
253 * disabled before putting SDRAM into self-refresh to avoid
254 * memory access due to page table walks.
256 mov32 r4, TEGRA_PMC_BASE
257 mov32 r5, TEGRA_CLK_RESET_BASE
258 mov32 r6, TEGRA_FLOW_CTRL_BASE
259 mov32 r7, TEGRA_TMRUS_BASE
261 mov32 r3, tegra_shut_off_mmu
264 mov32 r0, tegra30_tear_down_core
265 mov32 r1, tegra30_iram_start
267 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
271 ENDPROC(tegra30_sleep_core_finish)
274 * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
276 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
278 ENTRY(tegra30_sleep_cpu_secondary_finish)
281 /* Flush and disable the L1 data cache */
282 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
283 bl tegra_disable_clean_inv_dcache
285 /* Powergate this CPU. */
286 mov r0, #0 @ power mode flags (!hotplug)
287 bl tegra30_cpu_shutdown
288 mov r0, #1 @ never return here
290 ENDPROC(tegra30_sleep_cpu_secondary_finish)
293 * tegra30_tear_down_cpu
295 * Switches the CPU to enter sleep.
297 ENTRY(tegra30_tear_down_cpu)
298 mov32 r6, TEGRA_FLOW_CTRL_BASE
300 b tegra30_enter_sleep
301 ENDPROC(tegra30_tear_down_cpu)
303 /* START OF ROUTINES COPIED TO IRAM */
304 .align L1_CACHE_SHIFT
305 .globl tegra30_iram_start
311 * reset vector for LP1 restore; copied into IRAM during suspend.
312 * Brings the system back up to a safe staring point (SDRAM out of
313 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
314 * system clock running on the same PLL that it suspended at), and
315 * jumps to tegra_resume to restore virtual addressing.
316 * The physical address of tegra_resume expected to be stored in
319 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
321 ENTRY(tegra30_lp1_reset)
323 * The CPU and system bus are running at 32KHz and executing from
324 * IRAM when this code is executed; immediately switch to CLKM and
325 * enable PLLP, PLLM, PLLC, PLLA and PLLX.
327 mov32 r0, TEGRA_CLK_RESET_BASE
330 str r1, [r0, #CLK_RESET_SCLK_BURST]
331 str r1, [r0, #CLK_RESET_CCLK_BURST]
333 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
334 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
336 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
338 beq _no_pll_iddq_exit
340 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
341 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
342 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
344 mov32 r7, TEGRA_TMRUS_BASE
347 wait_until r1, r7, r3
349 /* enable PLLM via PMC */
350 mov32 r2, TEGRA_PMC_BASE
351 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
352 orr r1, r1, #(1 << 12)
353 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
355 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
356 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
357 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
362 /* enable PLLM via PMC */
363 mov32 r2, TEGRA_PMC_BASE
364 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
365 orr r1, r1, #(1 << 12)
366 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
368 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
369 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
370 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
373 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
374 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
376 pll_locked r1, r0, CLK_RESET_PLLM_BASE
377 pll_locked r1, r0, CLK_RESET_PLLP_BASE
378 pll_locked r1, r0, CLK_RESET_PLLA_BASE
379 pll_locked r1, r0, CLK_RESET_PLLC_BASE
380 pll_locked r1, r0, CLK_RESET_PLLX_BASE
382 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
385 ldr r1, [r0, #CLK_RESET_PLLP_BASE]
386 bic r1, r1, #(1<<31) @ disable PllP bypass
387 str r1, [r0, #CLK_RESET_PLLP_BASE]
390 mov32 r7, TEGRA_TMRUS_BASE
392 add r1, r1, #LOCK_DELAY
393 wait_until r1, r7, r3
395 adr r5, tegra_sdram_pad_save
397 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
398 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
400 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
401 str r4, [r0, #CLK_RESET_SCLK_BURST]
404 movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX
405 movteq r4, #:upper16:((1 << 28) | (0x8))
406 movwne r4, #:lower16:((1 << 28) | (0xe))
407 movtne r4, #:upper16:((1 << 28) | (0xe))
408 str r4, [r0, #CLK_RESET_CCLK_BURST]
410 /* Restore pad power state to normal */
411 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
413 bic r1, r1, #(1 << 31)
414 orr r1, r1, #(1 << 30)
415 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
418 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
419 movteq r0, #:upper16:TEGRA_EMC_BASE
421 movweq r0, #:lower16:TEGRA_EMC0_BASE
422 movteq r0, #:upper16:TEGRA_EMC0_BASE
424 movweq r0, #:lower16:TEGRA124_EMC_BASE
425 movteq r0, #:upper16:TEGRA124_EMC_BASE
428 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
429 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
430 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
431 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
432 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
433 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
436 ldr r1, [r0, #EMC_CFG_DIG_DLL]
437 orr r1, r1, #(1 << 30) @ set DLL_RESET
438 str r1, [r0, #EMC_CFG_DIG_DLL]
440 emc_timing_update r1, r0
443 movweq r1, #:lower16:TEGRA_EMC1_BASE
444 movteq r1, #:upper16:TEGRA_EMC1_BASE
447 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
448 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
449 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
450 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
452 emc_wait_auto_cal_onetime:
453 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
454 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
455 bne emc_wait_auto_cal_onetime
457 ldr r1, [r0, #EMC_CFG]
458 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
459 str r1, [r0, #EMC_CFG]
462 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
465 streq r1, [r0, #EMC_NOP]
466 streq r1, [r0, #EMC_NOP]
467 streq r1, [r0, #EMC_REFRESH]
469 emc_device_mask r1, r0
471 exit_selfrefresh_loop:
472 ldr r2, [r0, #EMC_EMC_STATUS]
474 bne exit_selfrefresh_loop
476 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
478 mov32 r7, TEGRA_TMRUS_BASE
479 ldr r2, [r0, #EMC_FBIO_CFG5]
481 and r2, r2, #3 @ check DRAM_TYPE
485 /* Issue a ZQ_CAL for dev0 - DDR3 */
486 mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1
487 str r2, [r0, #EMC_ZQ_CAL]
490 wait_until r2, r7, r3
495 /* Issue a ZQ_CAL for dev1 - DDR3 */
496 mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1
497 str r2, [r0, #EMC_ZQ_CAL]
500 wait_until r2, r7, r3
504 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
505 mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB
506 str r2, [r0, #EMC_MRW]
509 wait_until r2, r7, r3
514 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
515 mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB
516 str r2, [r0, #EMC_MRW]
519 wait_until r2, r7, r3
522 mov r1, #0 @ unstall all transactions
523 str r1, [r0, #EMC_REQ_CTRL]
524 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
525 str r1, [r0, #EMC_ZCAL_INTERVAL]
526 ldr r1, [r5, #0x0] @ restore EMC_CFG
527 str r1, [r0, #EMC_CFG]
529 /* Tegra114 had dual EMC channel, now config the other one */
531 bne __no_dual_emc_chanl
532 mov32 r1, TEGRA_EMC1_BASE
536 bne exit_self_refresh
539 mov32 r0, TEGRA_PMC_BASE
540 ldr r0, [r0, #PMC_SCRATCH41]
541 ret r0 @ jump to tegra_resume
542 ENDPROC(tegra30_lp1_reset)
544 .align L1_CACHE_SHIFT
545 tegra30_sdram_pad_address:
546 .word TEGRA_EMC_BASE + EMC_CFG @0x0
547 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
548 .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
549 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
550 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
551 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
552 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
553 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
554 tegra30_sdram_pad_address_end:
556 tegra114_sdram_pad_address:
557 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
558 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
559 .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8
560 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc
561 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
562 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
563 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
564 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
565 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
566 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
567 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
568 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
569 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
570 tegra114_sdram_pad_adress_end:
572 tegra124_sdram_pad_address:
573 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
574 .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
575 .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
576 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
577 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
578 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
579 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
580 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
581 tegra124_sdram_pad_address_end:
583 tegra30_sdram_pad_size:
584 .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
586 tegra114_sdram_pad_size:
587 .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
589 .type tegra_sdram_pad_save, %object
590 tegra_sdram_pad_save:
591 .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
596 * tegra30_tear_down_core
598 * copied into and executed from IRAM
599 * puts memory in self-refresh for LP0 and LP1
601 tegra30_tear_down_core:
602 bl tegra30_sdram_self_refresh
603 bl tegra30_switch_cpu_to_clk32k
604 b tegra30_enter_sleep
607 * tegra30_switch_cpu_to_clk32k
609 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
610 * to the 32KHz clock.
611 * r4 = TEGRA_PMC_BASE
612 * r5 = TEGRA_CLK_RESET_BASE
613 * r6 = TEGRA_FLOW_CTRL_BASE
614 * r7 = TEGRA_TMRUS_BASE
617 tegra30_switch_cpu_to_clk32k:
619 * start by jumping to CLKM to safely disable PLLs, then jump to
623 str r0, [r5, #CLK_RESET_SCLK_BURST]
624 /* 2uS delay delay between changing SCLK and CCLK */
627 wait_until r1, r7, r9
628 str r0, [r5, #CLK_RESET_CCLK_BURST]
630 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
631 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
633 /* switch the clock source of mselect to be CLK_M */
634 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
635 orr r0, r0, #MSELECT_CLKM
636 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
638 /* 2uS delay delay between changing SCLK and disabling PLLs */
641 wait_until r1, r7, r9
643 /* disable PLLM via PMC in LP1 */
644 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
645 bic r0, r0, #(1 << 12)
646 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
648 /* disable PLLP, PLLA, PLLC and PLLX */
649 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
651 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
652 orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
653 bic r0, r0, #(1 << 30)
654 str r0, [r5, #CLK_RESET_PLLP_BASE]
655 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
656 bic r0, r0, #(1 << 30)
657 str r0, [r5, #CLK_RESET_PLLA_BASE]
658 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
659 bic r0, r0, #(1 << 30)
660 str r0, [r5, #CLK_RESET_PLLC_BASE]
661 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
662 bic r0, r0, #(1 << 30)
663 str r0, [r5, #CLK_RESET_PLLX_BASE]
667 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
671 mov r0, #0 /* brust policy = 32KHz */
672 str r0, [r5, #CLK_RESET_SCLK_BURST]
677 * tegra30_enter_sleep
679 * uses flow controller to enter sleep state
680 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
681 * executes from SDRAM with target state is LP2
682 * r6 = TEGRA_FLOW_CTRL_BASE
687 cpu_to_csr_reg r2, r1
689 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
690 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
693 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
695 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
696 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
697 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
699 cpu_to_halt_reg r2, r1
702 ldr r0, [r6, r2] /* memory barrier */
707 wfi /* CPU should be power gated here */
709 /* !!!FIXME!!! Implement halt failure handler */
713 * tegra30_sdram_self_refresh
715 * called with MMU off and caches disabled
716 * must be executed from IRAM
717 * r4 = TEGRA_PMC_BASE
718 * r5 = TEGRA_CLK_RESET_BASE
719 * r6 = TEGRA_FLOW_CTRL_BASE
720 * r7 = TEGRA_TMRUS_BASE
723 tegra30_sdram_self_refresh:
725 adr r8, tegra_sdram_pad_save
726 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
728 adreq r2, tegra30_sdram_pad_address
729 ldreq r3, tegra30_sdram_pad_size
731 adreq r2, tegra114_sdram_pad_address
732 ldreq r3, tegra114_sdram_pad_size
734 adreq r2, tegra124_sdram_pad_address
735 ldreq r3, tegra30_sdram_pad_size
740 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
743 str r1, [r8, r9] @ save the content of the addr
753 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
755 ldreq r0, =TEGRA_EMC0_BASE
757 ldreq r0, =TEGRA124_EMC_BASE
762 str r1, [r0, #EMC_ZCAL_INTERVAL]
763 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
764 ldr r1, [r0, #EMC_CFG]
765 bic r1, r1, #(1 << 28)
766 bicne r1, r1, #(1 << 29)
767 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
769 emc_timing_update r1, r0
773 wait_until r1, r7, r2
776 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
777 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
778 bne emc_wait_auto_cal
781 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
784 ldr r1, [r0, #EMC_EMC_STATUS]
789 str r1, [r0, #EMC_SELF_REF]
791 emc_device_mask r1, r0
794 ldr r2, [r0, #EMC_EMC_STATUS]
797 bne emcself @ loop until DDR in self-refresh
799 /* Put VTTGEN in the lowest power mode */
800 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
801 mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
803 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
804 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
806 orreq r1, r1, #7 @ set E_NO_VTTGEN
808 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
810 emc_timing_update r1, r0
812 /* Tegra114 had dual EMC channel, now config the other one */
814 bne no_dual_emc_chanl
815 mov32 r1, TEGRA_EMC1_BASE
818 bne enter_self_refresh
821 ldr r1, [r4, #PMC_CTRL]
822 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
825 * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
826 * and COMP in the lowest power mode when LP1.
829 str r1, [r4, #PMC_IO_DPD_REQ]
837 /* dummy symbol for end of IRAM */
838 .align L1_CACHE_SHIFT
839 .global tegra30_iram_end