1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
6 #include <linux/linkage.h>
8 #include <soc/tegra/flowctrl.h>
9 #include <soc/tegra/fuse.h>
11 #include <asm/asm-offsets.h>
12 #include <asm/assembler.h>
13 #include <asm/cache.h>
19 #define EMC_ADR_CFG 0x10
20 #define EMC_TIMING_CONTROL 0x28
22 #define EMC_SELF_REF 0xe0
24 #define EMC_FBIO_CFG5 0x104
25 #define EMC_AUTO_CAL_CONFIG 0x2a4
26 #define EMC_AUTO_CAL_INTERVAL 0x2a8
27 #define EMC_AUTO_CAL_STATUS 0x2ac
28 #define EMC_REQ_CTRL 0x2b0
29 #define EMC_CFG_DIG_DLL 0x2bc
30 #define EMC_EMC_STATUS 0x2b4
31 #define EMC_ZCAL_INTERVAL 0x2e0
32 #define EMC_ZQ_CAL 0x2ec
33 #define EMC_XM2VTTGENPADCTRL 0x310
34 #define EMC_XM2VTTGENPADCTRL2 0x314
37 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
39 #define PMC_PLLP_WB0_OVERRIDE 0xf8
40 #define PMC_IO_DPD_REQ 0x1b8
41 #define PMC_IO_DPD_STATUS 0x1bc
43 #define CLK_RESET_CCLK_BURST 0x20
44 #define CLK_RESET_CCLK_DIVIDER 0x24
45 #define CLK_RESET_SCLK_BURST 0x28
46 #define CLK_RESET_SCLK_DIVIDER 0x2c
48 #define CLK_RESET_PLLC_BASE 0x80
49 #define CLK_RESET_PLLC_MISC 0x8c
50 #define CLK_RESET_PLLM_BASE 0x90
51 #define CLK_RESET_PLLM_MISC 0x9c
52 #define CLK_RESET_PLLP_BASE 0xa0
53 #define CLK_RESET_PLLP_MISC 0xac
54 #define CLK_RESET_PLLA_BASE 0xb0
55 #define CLK_RESET_PLLA_MISC 0xbc
56 #define CLK_RESET_PLLX_BASE 0xe0
57 #define CLK_RESET_PLLX_MISC 0xe4
58 #define CLK_RESET_PLLX_MISC3 0x518
59 #define CLK_RESET_PLLX_MISC3_IDDQ 3
60 #define CLK_RESET_PLLM_MISC_IDDQ 5
61 #define CLK_RESET_PLLC_MISC_IDDQ 26
62 #define CLK_RESET_PLLP_RESHIFT 0x528
63 #define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b
64 #define CLK_RESET_PLLP_RESHIFT_ENABLE 0x3
66 #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
68 #define MSELECT_CLKM (0x3 << 30)
70 #define LOCK_DELAY 50 /* safety delay after lock is detected */
72 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
74 #define PLLA_STORE_MASK (1 << 0)
75 #define PLLC_STORE_MASK (1 << 1)
76 #define PLLM_STORE_MASK (1 << 2)
77 #define PLLP_STORE_MASK (1 << 3)
78 #define PLLX_STORE_MASK (1 << 4)
79 #define PLLM_PMC_STORE_MASK (1 << 5)
81 .macro emc_device_mask, rd, base
82 ldr \rd, [\base, #EMC_ADR_CFG]
84 moveq \rd, #(0x1 << 8) @ just 1 device
85 movne \rd, #(0x3 << 8) @ 2 devices
88 .macro emc_timing_update, rd, base
90 str \rd, [\base, #EMC_TIMING_CONTROL]
92 ldr \rd, [\base, #EMC_EMC_STATUS]
93 tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
97 .macro test_pll_state, rd, test_mask
98 ldr \rd, tegra_pll_state
102 .macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask
103 ldr \rd, [\r_car_base, #\pll_base]
105 ldr \rd, tegra_pll_state
106 biceq \rd, \rd, #\pll_mask
107 orrne \rd, \rd, #\pll_mask
108 adr \tmp, tegra_pll_state
112 .macro store_pllm_pmc_state, rd, tmp, pmc_base
113 ldr \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE]
115 ldr \rd, tegra_pll_state
116 biceq \rd, \rd, #PLLM_PMC_STORE_MASK
117 orrne \rd, \rd, #PLLM_PMC_STORE_MASK
118 adr \tmp, tegra_pll_state
122 .macro pllm_pmc_enable, rd, pmc_base
123 test_pll_state \rd, PLLM_PMC_STORE_MASK
125 ldrne \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE]
126 orrne \rd, \rd, #(1 << 12)
127 strne \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE]
130 .macro pll_enable, rd, r_car_base, pll_base, pll_misc, test_mask
131 test_pll_state \rd, \test_mask
134 ldr \rd, [\r_car_base, #\pll_base]
136 orreq \rd, \rd, #(1 << 30)
137 streq \rd, [\r_car_base, #\pll_base]
138 /* Enable lock detector */
140 ldr \rd, [\r_car_base, #\pll_misc]
141 bic \rd, \rd, #(1 << 18)
142 str \rd, [\r_car_base, #\pll_misc]
143 ldr \rd, [\r_car_base, #\pll_misc]
144 ldr \rd, [\r_car_base, #\pll_misc]
145 orr \rd, \rd, #(1 << 18)
146 str \rd, [\r_car_base, #\pll_misc]
151 .macro pll_locked, rd, r_car_base, pll_base, test_mask
152 test_pll_state \rd, \test_mask
155 ldr \rd, [\r_car_base, #\pll_base]
161 .macro pll_iddq_exit, rd, car, iddq, iddq_bit
162 ldr \rd, [\car, #\iddq]
163 bic \rd, \rd, #(1<<\iddq_bit)
164 str \rd, [\car, #\iddq]
167 .macro pll_iddq_entry, rd, car, iddq, iddq_bit
168 ldr \rd, [\car, #\iddq]
169 orr \rd, \rd, #(1<<\iddq_bit)
170 str \rd, [\car, #\iddq]
173 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
175 * tegra30_hotplug_shutdown(void)
177 * Powergates the current CPU.
178 * Should never return.
180 ENTRY(tegra30_hotplug_shutdown)
181 /* Powergate this CPU */
182 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
183 bl tegra30_cpu_shutdown
184 ret lr @ should never get here
185 ENDPROC(tegra30_hotplug_shutdown)
188 * tegra30_cpu_shutdown(unsigned long flags)
190 * Puts the current CPU in wait-for-event mode on the flow controller
191 * and powergates it -- flags (in R0) indicate the request type.
194 * corrupts r0-r4, r10-r12
196 ENTRY(tegra30_cpu_shutdown)
198 tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
200 bne _no_cpu0_chk @ It's not Tegra30
203 reteq lr @ Must never be called for CPU 0
206 ldr r12, =TEGRA_FLOW_CTRL_VIRT
207 cpu_to_csr_reg r1, r3
208 add r1, r1, r12 @ virtual CSR address for this CPU
209 cpu_to_halt_reg r2, r3
210 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
213 * Clear this CPU's "event" and "interrupt" flags and power gate
214 * it when halting but not before it is in the "WFE" state.
217 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
220 moveq r4, #(1 << 4) @ wfe bitmap
221 movne r4, #(1 << 8) @ wfi bitmap
222 ARM( orr r12, r12, r4, lsl r3 )
223 THUMB( lsl r4, r4, r3 )
224 THUMB( orr r12, r12, r4 )
230 subs r3, r3, #1 @ delay as a part of wfe war.
232 cpsid a @ disable imprecise aborts.
233 ldr r3, [r1] @ read CSR
234 str r3, [r1] @ clear CSR
236 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
237 beq flow_ctrl_setting_for_lp2
239 /* flow controller set up for hotplug */
240 mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug
242 flow_ctrl_setting_for_lp2:
243 /* flow controller set up for LP2 */
245 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
246 movne r3, #FLOW_CTRL_WAITEVENT
247 orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
248 orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
258 wfeeq @ CPU should be power gated here
264 * 38 nop's, which fills rest of wfe cache line and
265 * 4 more cachelines with nop
270 b . @ should never get here
272 ENDPROC(tegra30_cpu_shutdown)
275 #ifdef CONFIG_PM_SLEEP
277 * tegra30_sleep_core_finish(unsigned long v2p)
279 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
280 * tegra30_tear_down_core in IRAM
282 ENTRY(tegra30_sleep_core_finish)
284 /* Flush, disable the L1 data cache and exit SMP */
285 mov r0, #TEGRA_FLUSH_CACHE_ALL
286 bl tegra_disable_clean_inv_dcache
290 * Preload all the address literals that are needed for the
291 * CPU power-gating process, to avoid loading from SDRAM which
292 * are not supported once SDRAM is put into self-refresh.
293 * LP0 / LP1 use physical address, since the MMU needs to be
294 * disabled before putting SDRAM into self-refresh to avoid
295 * memory access due to page table walks.
297 mov32 r4, TEGRA_PMC_BASE
298 mov32 r5, TEGRA_CLK_RESET_BASE
299 mov32 r6, TEGRA_FLOW_CTRL_BASE
300 mov32 r7, TEGRA_TMRUS_BASE
302 mov32 r3, tegra_shut_off_mmu
305 mov32 r0, tegra30_tear_down_core
306 mov32 r1, tegra30_iram_start
308 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
312 ENDPROC(tegra30_sleep_core_finish)
315 * tegra30_pm_secondary_cpu_suspend(unsigned long unused_arg)
317 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
319 ENTRY(tegra30_pm_secondary_cpu_suspend)
322 /* Flush and disable the L1 data cache */
323 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
324 bl tegra_disable_clean_inv_dcache
326 /* Powergate this CPU. */
327 mov r0, #0 @ power mode flags (!hotplug)
328 bl tegra30_cpu_shutdown
329 mov r0, #1 @ never return here
331 ENDPROC(tegra30_pm_secondary_cpu_suspend)
334 * tegra30_tear_down_cpu
336 * Switches the CPU to enter sleep.
338 ENTRY(tegra30_tear_down_cpu)
339 mov32 r6, TEGRA_FLOW_CTRL_BASE
341 b tegra30_enter_sleep
342 ENDPROC(tegra30_tear_down_cpu)
344 /* START OF ROUTINES COPIED TO IRAM */
345 .align L1_CACHE_SHIFT
346 .globl tegra30_iram_start
352 * reset vector for LP1 restore; copied into IRAM during suspend.
353 * Brings the system back up to a safe staring point (SDRAM out of
354 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
355 * system clock running on the same PLL that it suspended at), and
356 * jumps to tegra_resume to restore virtual addressing.
357 * The physical address of tegra_resume expected to be stored in
360 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
362 ENTRY(tegra30_lp1_reset)
364 * The CPU and system bus are running at 32KHz and executing from
365 * IRAM when this code is executed; immediately switch to CLKM and
366 * enable PLLP, PLLM, PLLC, PLLA and PLLX.
368 mov32 r0, TEGRA_CLK_RESET_BASE
371 str r1, [r0, #CLK_RESET_SCLK_BURST]
372 str r1, [r0, #CLK_RESET_CCLK_BURST]
374 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
375 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
377 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
379 beq _no_pll_iddq_exit
381 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
382 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
383 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
385 mov32 r7, TEGRA_TMRUS_BASE
388 wait_until r1, r7, r3
390 /* enable PLLM via PMC */
391 mov32 r2, TEGRA_PMC_BASE
392 pllm_pmc_enable r1, r2
394 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0, PLLM_STORE_MASK
395 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0, PLLC_STORE_MASK
396 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0, PLLX_STORE_MASK
401 /* enable PLLM via PMC */
402 mov32 r2, TEGRA_PMC_BASE
403 pllm_pmc_enable r1, r2
405 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC, PLLM_STORE_MASK
406 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC, PLLC_STORE_MASK
409 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC, PLLP_STORE_MASK
410 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC, PLLA_STORE_MASK
412 pll_locked r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
413 pll_locked r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
414 pll_locked r1, r0, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK
415 pll_locked r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
418 * CPUFreq driver could select other PLL for CPU. PLLX will be
419 * enabled by the Tegra30 CLK driver on an as-needed basis, see
420 * tegra30_cpu_clock_resume().
422 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
426 pll_locked r1, r0, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
428 ldr r1, [r0, #CLK_RESET_PLLP_BASE]
429 bic r1, r1, #(1<<31) @ disable PllP bypass
430 str r1, [r0, #CLK_RESET_PLLP_BASE]
432 mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
433 str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
436 mov32 r7, TEGRA_TMRUS_BASE
438 add r1, r1, #LOCK_DELAY
439 wait_until r1, r7, r3
441 adr r5, tegra_sdram_pad_save
443 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
444 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
446 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
447 str r4, [r0, #CLK_RESET_SCLK_BURST]
449 movw r4, #:lower16:((1 << 28) | (0x4)) @ burst policy is PLLP
450 movt r4, #:upper16:((1 << 28) | (0x4))
451 str r4, [r0, #CLK_RESET_CCLK_BURST]
453 /* Restore pad power state to normal */
454 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
456 bic r1, r1, #(1 << 31)
457 orr r1, r1, #(1 << 30)
458 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
461 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
462 movteq r0, #:upper16:TEGRA_EMC_BASE
464 movweq r0, #:lower16:TEGRA_EMC0_BASE
465 movteq r0, #:upper16:TEGRA_EMC0_BASE
467 movweq r0, #:lower16:TEGRA124_EMC_BASE
468 movteq r0, #:upper16:TEGRA124_EMC_BASE
471 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
472 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
473 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
474 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
475 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
476 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
479 ldr r1, [r0, #EMC_CFG_DIG_DLL]
480 orr r1, r1, #(1 << 30) @ set DLL_RESET
481 str r1, [r0, #EMC_CFG_DIG_DLL]
483 emc_timing_update r1, r0
486 movweq r1, #:lower16:TEGRA_EMC1_BASE
487 movteq r1, #:upper16:TEGRA_EMC1_BASE
490 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
491 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
492 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
493 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
495 emc_wait_auto_cal_onetime:
496 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
497 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
498 bne emc_wait_auto_cal_onetime
500 ldr r1, [r0, #EMC_CFG]
501 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
502 str r1, [r0, #EMC_CFG]
505 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
508 streq r1, [r0, #EMC_NOP]
509 streq r1, [r0, #EMC_NOP]
511 emc_device_mask r1, r0
513 exit_selfrefresh_loop:
514 ldr r2, [r0, #EMC_EMC_STATUS]
516 bne exit_selfrefresh_loop
518 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
520 mov32 r7, TEGRA_TMRUS_BASE
521 ldr r2, [r0, #EMC_FBIO_CFG5]
523 and r2, r2, #3 @ check DRAM_TYPE
527 /* Issue a ZQ_CAL for dev0 - DDR3 */
528 mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1
529 str r2, [r0, #EMC_ZQ_CAL]
532 wait_until r2, r7, r3
537 /* Issue a ZQ_CAL for dev1 - DDR3 */
538 mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1
539 str r2, [r0, #EMC_ZQ_CAL]
542 wait_until r2, r7, r3
546 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
547 mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB
548 str r2, [r0, #EMC_MRW]
551 wait_until r2, r7, r3
556 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
557 mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB
558 str r2, [r0, #EMC_MRW]
561 wait_until r2, r7, r3
564 mov r1, #0 @ unstall all transactions
565 str r1, [r0, #EMC_REQ_CTRL]
566 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
567 str r1, [r0, #EMC_ZCAL_INTERVAL]
568 ldr r1, [r5, #0x0] @ restore EMC_CFG
569 str r1, [r0, #EMC_CFG]
571 emc_timing_update r1, r0
573 /* Tegra114 had dual EMC channel, now config the other one */
575 bne __no_dual_emc_chanl
576 mov32 r1, TEGRA_EMC1_BASE
580 bne exit_self_refresh
583 mov32 r0, TEGRA_PMC_BASE
584 ldr r0, [r0, #PMC_SCRATCH41]
585 ret r0 @ jump to tegra_resume
586 ENDPROC(tegra30_lp1_reset)
588 .align L1_CACHE_SHIFT
589 tegra30_sdram_pad_address:
590 .word TEGRA_EMC_BASE + EMC_CFG @0x0
591 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
592 .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
593 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
594 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
595 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
596 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
597 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
598 tegra30_sdram_pad_address_end:
600 tegra114_sdram_pad_address:
601 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
602 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
603 .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8
604 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc
605 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
606 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
607 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
608 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
609 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
610 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
611 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
612 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
613 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
614 tegra114_sdram_pad_adress_end:
616 tegra124_sdram_pad_address:
617 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
618 .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
619 .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
620 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
621 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
622 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
623 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
624 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
625 tegra124_sdram_pad_address_end:
627 tegra30_sdram_pad_size:
628 .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
630 tegra114_sdram_pad_size:
631 .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
633 .type tegra_sdram_pad_save, %object
634 tegra_sdram_pad_save:
635 .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
643 * tegra30_tear_down_core
645 * copied into and executed from IRAM
646 * puts memory in self-refresh for LP0 and LP1
648 tegra30_tear_down_core:
649 bl tegra30_sdram_self_refresh
650 bl tegra30_switch_cpu_to_clk32k
651 b tegra30_enter_sleep
654 * tegra30_switch_cpu_to_clk32k
656 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
657 * to the 32KHz clock.
658 * r4 = TEGRA_PMC_BASE
659 * r5 = TEGRA_CLK_RESET_BASE
660 * r6 = TEGRA_FLOW_CTRL_BASE
661 * r7 = TEGRA_TMRUS_BASE
664 tegra30_switch_cpu_to_clk32k:
666 * start by jumping to CLKM to safely disable PLLs, then jump to
670 str r0, [r5, #CLK_RESET_SCLK_BURST]
671 /* 2uS delay delay between changing SCLK and CCLK */
674 wait_until r1, r7, r9
675 str r0, [r5, #CLK_RESET_CCLK_BURST]
677 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
678 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
680 /* switch the clock source of mselect to be CLK_M */
681 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
682 orr r0, r0, #MSELECT_CLKM
683 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
685 /* 2uS delay delay between changing SCLK and disabling PLLs */
688 wait_until r1, r7, r9
690 /* store enable-state of PLLs */
691 store_pll_state r0, r1, r5, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK
692 store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
693 store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK
694 store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK
695 store_pll_state r0, r1, r5, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK
696 store_pllm_pmc_state r0, r1, r4
698 /* disable PLLM via PMC in LP1 */
699 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
700 bic r0, r0, #(1 << 12)
701 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
703 /* disable PLLP, PLLA, PLLC and PLLX */
704 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
706 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
707 orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
708 bic r0, r0, #(1 << 30)
709 str r0, [r5, #CLK_RESET_PLLP_BASE]
711 mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
712 str r0, [r5, #CLK_RESET_PLLP_RESHIFT]
714 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
715 bic r0, r0, #(1 << 30)
716 str r0, [r5, #CLK_RESET_PLLA_BASE]
717 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
718 bic r0, r0, #(1 << 30)
719 str r0, [r5, #CLK_RESET_PLLC_BASE]
720 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
721 bic r0, r0, #(1 << 30)
722 str r0, [r5, #CLK_RESET_PLLX_BASE]
726 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
730 * Switch to clk_s (32KHz); bits 28:31=0
731 * Enable burst on CPU IRQ; bit 24=1
732 * Set IRQ burst clock source to clk_m; bits 10:8=0
735 str r0, [r5, #CLK_RESET_SCLK_BURST]
740 * tegra30_enter_sleep
742 * uses flow controller to enter sleep state
743 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
744 * executes from SDRAM with target state is LP2
745 * r6 = TEGRA_FLOW_CTRL_BASE
750 cpu_to_csr_reg r2, r1
752 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
753 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
756 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
758 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
759 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
760 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
762 cpu_to_halt_reg r2, r1
765 ldr r0, [r6, r2] /* memory barrier */
771 wfine /* CPU should be power gated here */
774 /* !!!FIXME!!! Implement halt failure handler */
778 * tegra30_sdram_self_refresh
780 * called with MMU off and caches disabled
781 * must be executed from IRAM
782 * r4 = TEGRA_PMC_BASE
783 * r5 = TEGRA_CLK_RESET_BASE
784 * r6 = TEGRA_FLOW_CTRL_BASE
785 * r7 = TEGRA_TMRUS_BASE
788 tegra30_sdram_self_refresh:
790 adr r8, tegra_sdram_pad_save
791 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
793 adreq r2, tegra30_sdram_pad_address
794 ldreq r3, tegra30_sdram_pad_size
796 adreq r2, tegra114_sdram_pad_address
797 ldreq r3, tegra114_sdram_pad_size
799 adreq r2, tegra124_sdram_pad_address
800 ldreq r3, tegra30_sdram_pad_size
805 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
808 str r1, [r8, r9] @ save the content of the addr
818 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
820 ldreq r0, =TEGRA_EMC0_BASE
822 ldreq r0, =TEGRA124_EMC_BASE
827 str r1, [r0, #EMC_ZCAL_INTERVAL]
828 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
829 ldr r1, [r0, #EMC_CFG]
830 bic r1, r1, #(1 << 28)
831 bicne r1, r1, #(1 << 29)
832 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
834 emc_timing_update r1, r0
838 wait_until r1, r7, r2
841 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
842 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
843 bne emc_wait_auto_cal
846 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
849 ldr r1, [r0, #EMC_EMC_STATUS]
854 str r1, [r0, #EMC_SELF_REF]
856 emc_device_mask r1, r0
859 ldr r2, [r0, #EMC_EMC_STATUS]
862 bne emcself @ loop until DDR in self-refresh
864 /* Put VTTGEN in the lowest power mode */
865 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
866 mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
868 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
869 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
871 orreq r1, r1, #7 @ set E_NO_VTTGEN
873 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
875 emc_timing_update r1, r0
877 /* Tegra114 had dual EMC channel, now config the other one */
879 bne no_dual_emc_chanl
880 mov32 r1, TEGRA_EMC1_BASE
883 bne enter_self_refresh
886 ldr r1, [r4, #PMC_CTRL]
887 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
890 * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
891 * and COMP in the lowest power mode when LP1.
894 str r1, [r4, #PMC_IO_DPD_REQ]
902 /* dummy symbol for end of IRAM */
903 .align L1_CACHE_SHIFT
904 .global tegra30_iram_end