GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / mach-sunxi / mc_smp.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2018 Chen-Yu Tsai
4  *
5  * Chen-Yu Tsai <wens@csie.org>
6  *
7  * arch/arm/mach-sunxi/mc_smp.c
8  *
9  * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and
10  * arch/arm/mach-hisi/platmcpm.c
11  * Cluster cache enable trampoline code adapted from MCPM framework
12  */
13
14 #include <linux/arm-cci.h>
15 #include <linux/cpu_pm.h>
16 #include <linux/delay.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/irqchip/arm-gic.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/smp.h>
24
25 #include <asm/cacheflush.h>
26 #include <asm/cp15.h>
27 #include <asm/cputype.h>
28 #include <asm/idmap.h>
29 #include <asm/smp_plat.h>
30 #include <asm/suspend.h>
31
32 #define SUNXI_CPUS_PER_CLUSTER          4
33 #define SUNXI_NR_CLUSTERS               2
34
35 #define POLL_USEC       100
36 #define TIMEOUT_USEC    100000
37
38 #define CPUCFG_CX_CTRL_REG0(c)          (0x10 * (c))
39 #define CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(n)   BIT(n)
40 #define CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE_ALL  0xf
41 #define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7   BIT(4)
42 #define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15  BIT(0)
43 #define CPUCFG_CX_CTRL_REG1(c)          (0x10 * (c) + 0x4)
44 #define CPUCFG_CX_CTRL_REG1_ACINACTM    BIT(0)
45 #define CPUCFG_CX_STATUS(c)             (0x30 + 0x4 * (c))
46 #define CPUCFG_CX_STATUS_STANDBYWFI(n)  BIT(16 + (n))
47 #define CPUCFG_CX_STATUS_STANDBYWFIL2   BIT(0)
48 #define CPUCFG_CX_RST_CTRL(c)           (0x80 + 0x4 * (c))
49 #define CPUCFG_CX_RST_CTRL_DBG_SOC_RST  BIT(24)
50 #define CPUCFG_CX_RST_CTRL_ETM_RST(n)   BIT(20 + (n))
51 #define CPUCFG_CX_RST_CTRL_ETM_RST_ALL  (0xf << 20)
52 #define CPUCFG_CX_RST_CTRL_DBG_RST(n)   BIT(16 + (n))
53 #define CPUCFG_CX_RST_CTRL_DBG_RST_ALL  (0xf << 16)
54 #define CPUCFG_CX_RST_CTRL_H_RST        BIT(12)
55 #define CPUCFG_CX_RST_CTRL_L2_RST       BIT(8)
56 #define CPUCFG_CX_RST_CTRL_CX_RST(n)    BIT(4 + (n))
57 #define CPUCFG_CX_RST_CTRL_CORE_RST(n)  BIT(n)
58 #define CPUCFG_CX_RST_CTRL_CORE_RST_ALL (0xf << 0)
59
60 #define PRCM_CPU_PO_RST_CTRL(c)         (0x4 + 0x4 * (c))
61 #define PRCM_CPU_PO_RST_CTRL_CORE(n)    BIT(n)
62 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL   0xf
63 #define PRCM_PWROFF_GATING_REG(c)       (0x100 + 0x4 * (c))
64 /* The power off register for clusters are different from a80 and a83t */
65 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I    BIT(0)
66 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I    BIT(4)
67 #define PRCM_PWROFF_GATING_REG_CORE(n)  BIT(n)
68 #define PRCM_PWR_SWITCH_REG(c, cpu)     (0x140 + 0x10 * (c) + 0x4 * (cpu))
69 #define PRCM_CPU_SOFT_ENTRY_REG         0x164
70
71 /* R_CPUCFG registers, specific to sun8i-a83t */
72 #define R_CPUCFG_CLUSTER_PO_RST_CTRL(c) (0x30 + (c) * 0x4)
73 #define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n)    BIT(n)
74 #define R_CPUCFG_CPU_SOFT_ENTRY_REG             0x01a4
75
76 #define CPU0_SUPPORT_HOTPLUG_MAGIC0     0xFA50392F
77 #define CPU0_SUPPORT_HOTPLUG_MAGIC1     0x790DCA3A
78
79 static void __iomem *cpucfg_base;
80 static void __iomem *prcm_base;
81 static void __iomem *sram_b_smp_base;
82 static void __iomem *r_cpucfg_base;
83
84 extern void sunxi_mc_smp_secondary_startup(void);
85 extern void sunxi_mc_smp_resume(void);
86 static bool is_a83t;
87
88 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
89 {
90         struct device_node *node;
91         int cpu = cluster * SUNXI_CPUS_PER_CLUSTER + core;
92
93         node = of_cpu_device_node_get(cpu);
94
95         /* In case of_cpu_device_node_get fails */
96         if (!node)
97                 node = of_get_cpu_node(cpu, NULL);
98
99         if (!node) {
100                 /*
101                  * There's no point in returning an error, since we
102                  * would be mid way in a core or cluster power sequence.
103                  */
104                 pr_err("%s: Couldn't get CPU cluster %u core %u device node\n",
105                        __func__, cluster, core);
106
107                 return false;
108         }
109
110         return of_device_is_compatible(node, "arm,cortex-a15");
111 }
112
113 static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster,
114                                       bool enable)
115 {
116         u32 reg;
117
118         /* control sequence from Allwinner A80 user manual v1.2 PRCM section */
119         reg = readl(prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
120         if (enable) {
121                 if (reg == 0x00) {
122                         pr_debug("power clamp for cluster %u cpu %u already open\n",
123                                  cluster, cpu);
124                         return 0;
125                 }
126
127                 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
128                 udelay(10);
129                 writel(0xfe, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
130                 udelay(10);
131                 writel(0xf8, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
132                 udelay(10);
133                 writel(0xf0, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
134                 udelay(10);
135                 writel(0x00, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
136                 udelay(10);
137         } else {
138                 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
139                 udelay(10);
140         }
141
142         return 0;
143 }
144
145 static void sunxi_cpu0_hotplug_support_set(bool enable)
146 {
147         if (enable) {
148                 writel(CPU0_SUPPORT_HOTPLUG_MAGIC0, sram_b_smp_base);
149                 writel(CPU0_SUPPORT_HOTPLUG_MAGIC1, sram_b_smp_base + 0x4);
150         } else {
151                 writel(0x0, sram_b_smp_base);
152                 writel(0x0, sram_b_smp_base + 0x4);
153         }
154 }
155
156 static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
157 {
158         u32 reg;
159
160         pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
161         if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
162                 return -EINVAL;
163
164         /* Set hotplug support magic flags for cpu0 */
165         if (cluster == 0 && cpu == 0)
166                 sunxi_cpu0_hotplug_support_set(true);
167
168         /* assert processor power-on reset */
169         reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
170         reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
171         writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
172
173         if (is_a83t) {
174                 /* assert cpu power-on reset */
175                 reg  = readl(r_cpucfg_base +
176                              R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
177                 reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
178                 writel(reg, r_cpucfg_base +
179                        R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
180                 udelay(10);
181         }
182
183         /* Cortex-A7: hold L1 reset disable signal low */
184         if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
185                 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
186                 reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(cpu);
187                 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
188         }
189
190         /* assert processor related resets */
191         reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
192         reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
193
194         /*
195          * Allwinner code also asserts resets for NEON on A15. According
196          * to ARM manuals, asserting power-on reset is sufficient.
197          */
198         if (!sunxi_core_is_cortex_a15(cpu, cluster))
199                 reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST(cpu);
200
201         writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
202
203         /* open power switch */
204         sunxi_cpu_power_switch_set(cpu, cluster, true);
205
206         /* Handle A83T bit swap */
207         if (is_a83t) {
208                 if (cpu == 0)
209                         cpu = 4;
210         }
211
212         /* clear processor power gate */
213         reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
214         reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
215         writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
216         udelay(20);
217
218         /* Handle A83T bit swap */
219         if (is_a83t) {
220                 if (cpu == 4)
221                         cpu = 0;
222         }
223
224         /* de-assert processor power-on reset */
225         reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
226         reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
227         writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
228
229         if (is_a83t) {
230                 reg  = readl(r_cpucfg_base +
231                              R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
232                 reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
233                 writel(reg, r_cpucfg_base +
234                        R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
235                 udelay(10);
236         }
237
238         /* de-assert all processor resets */
239         reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
240         reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
241         reg |= CPUCFG_CX_RST_CTRL_CORE_RST(cpu);
242         if (!sunxi_core_is_cortex_a15(cpu, cluster))
243                 reg |= CPUCFG_CX_RST_CTRL_ETM_RST(cpu);
244         else
245                 reg |= CPUCFG_CX_RST_CTRL_CX_RST(cpu); /* NEON */
246         writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
247
248         return 0;
249 }
250
251 static int sunxi_cluster_powerup(unsigned int cluster)
252 {
253         u32 reg;
254
255         pr_debug("%s: cluster %u\n", __func__, cluster);
256         if (cluster >= SUNXI_NR_CLUSTERS)
257                 return -EINVAL;
258
259         /* For A83T, assert cluster cores resets */
260         if (is_a83t) {
261                 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
262                 reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;   /* Core Reset    */
263                 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
264                 udelay(10);
265         }
266
267         /* assert ACINACTM */
268         reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
269         reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
270         writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
271
272         /* assert cluster processor power-on resets */
273         reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
274         reg &= ~PRCM_CPU_PO_RST_CTRL_CORE_ALL;
275         writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
276
277         /* assert cluster cores resets */
278         if (is_a83t) {
279                 reg  = readl(r_cpucfg_base +
280                              R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
281                 reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;
282                 writel(reg, r_cpucfg_base +
283                        R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
284                 udelay(10);
285         }
286
287         /* assert cluster resets */
288         reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
289         reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
290         reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST_ALL;
291         reg &= ~CPUCFG_CX_RST_CTRL_H_RST;
292         reg &= ~CPUCFG_CX_RST_CTRL_L2_RST;
293
294         /*
295          * Allwinner code also asserts resets for NEON on A15. According
296          * to ARM manuals, asserting power-on reset is sufficient.
297          */
298         if (!sunxi_core_is_cortex_a15(0, cluster))
299                 reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST_ALL;
300
301         writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
302
303         /* hold L1/L2 reset disable signals low */
304         reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
305         if (sunxi_core_is_cortex_a15(0, cluster)) {
306                 /* Cortex-A15: hold L2RSTDISABLE low */
307                 reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15;
308         } else {
309                 /* Cortex-A7: hold L1RSTDISABLE and L2RSTDISABLE low */
310                 reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE_ALL;
311                 reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7;
312         }
313         writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
314
315         /* clear cluster power gate */
316         reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
317         if (is_a83t)
318                 reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
319         else
320                 reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
321         writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
322         udelay(20);
323
324         /* de-assert cluster resets */
325         reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
326         reg |= CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
327         reg |= CPUCFG_CX_RST_CTRL_H_RST;
328         reg |= CPUCFG_CX_RST_CTRL_L2_RST;
329         writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
330
331         /* de-assert ACINACTM */
332         reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
333         reg &= ~CPUCFG_CX_CTRL_REG1_ACINACTM;
334         writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
335
336         return 0;
337 }
338
339 /*
340  * This bit is shared between the initial nocache_trampoline call to
341  * enable CCI-400 and proper cluster cache disable before power down.
342  */
343 static void sunxi_cluster_cache_disable_without_axi(void)
344 {
345         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
346                 /*
347                  * On the Cortex-A15 we need to disable
348                  * L2 prefetching before flushing the cache.
349                  */
350                 asm volatile(
351                 "mcr    p15, 1, %0, c15, c0, 3\n"
352                 "isb\n"
353                 "dsb"
354                 : : "r" (0x400));
355         }
356
357         /* Flush all cache levels for this cluster. */
358         v7_exit_coherency_flush(all);
359
360         /*
361          * Disable cluster-level coherency by masking
362          * incoming snoops and DVM messages:
363          */
364         cci_disable_port_by_cpu(read_cpuid_mpidr());
365 }
366
367 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
368 int sunxi_mc_smp_first_comer;
369
370 static DEFINE_SPINLOCK(boot_lock);
371
372 static bool sunxi_mc_smp_cluster_is_down(unsigned int cluster)
373 {
374         int i;
375
376         for (i = 0; i < SUNXI_CPUS_PER_CLUSTER; i++)
377                 if (sunxi_mc_smp_cpu_table[cluster][i])
378                         return false;
379         return true;
380 }
381
382 static void sunxi_mc_smp_secondary_init(unsigned int cpu)
383 {
384         /* Clear hotplug support magic flags for cpu0 */
385         if (cpu == 0)
386                 sunxi_cpu0_hotplug_support_set(false);
387 }
388
389 static int sunxi_mc_smp_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
390 {
391         unsigned int mpidr, cpu, cluster;
392
393         mpidr = cpu_logical_map(l_cpu);
394         cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
395         cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
396
397         if (!cpucfg_base)
398                 return -ENODEV;
399         if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER)
400                 return -EINVAL;
401
402         spin_lock_irq(&boot_lock);
403
404         if (sunxi_mc_smp_cpu_table[cluster][cpu])
405                 goto out;
406
407         if (sunxi_mc_smp_cluster_is_down(cluster)) {
408                 sunxi_mc_smp_first_comer = true;
409                 sunxi_cluster_powerup(cluster);
410         } else {
411                 sunxi_mc_smp_first_comer = false;
412         }
413
414         /* This is read by incoming CPUs with their cache and MMU disabled */
415         sync_cache_w(&sunxi_mc_smp_first_comer);
416         sunxi_cpu_powerup(cpu, cluster);
417
418 out:
419         sunxi_mc_smp_cpu_table[cluster][cpu]++;
420         spin_unlock_irq(&boot_lock);
421
422         return 0;
423 }
424
425 #ifdef CONFIG_HOTPLUG_CPU
426 static void sunxi_cluster_cache_disable(void)
427 {
428         unsigned int cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
429         u32 reg;
430
431         pr_debug("%s: cluster %u\n", __func__, cluster);
432
433         sunxi_cluster_cache_disable_without_axi();
434
435         /* last man standing, assert ACINACTM */
436         reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
437         reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
438         writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
439 }
440
441 static void sunxi_mc_smp_cpu_die(unsigned int l_cpu)
442 {
443         unsigned int mpidr, cpu, cluster;
444         bool last_man;
445
446         mpidr = cpu_logical_map(l_cpu);
447         cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
448         cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
449         pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
450
451         spin_lock(&boot_lock);
452         sunxi_mc_smp_cpu_table[cluster][cpu]--;
453         if (sunxi_mc_smp_cpu_table[cluster][cpu] == 1) {
454                 /* A power_up request went ahead of us. */
455                 pr_debug("%s: aborting due to a power up request\n",
456                          __func__);
457                 spin_unlock(&boot_lock);
458                 return;
459         } else if (sunxi_mc_smp_cpu_table[cluster][cpu] > 1) {
460                 pr_err("Cluster %d CPU%d boots multiple times\n",
461                        cluster, cpu);
462                 BUG();
463         }
464
465         last_man = sunxi_mc_smp_cluster_is_down(cluster);
466         spin_unlock(&boot_lock);
467
468         gic_cpu_if_down(0);
469         if (last_man)
470                 sunxi_cluster_cache_disable();
471         else
472                 v7_exit_coherency_flush(louis);
473
474         for (;;)
475                 wfi();
476 }
477
478 static int sunxi_cpu_powerdown(unsigned int cpu, unsigned int cluster)
479 {
480         u32 reg;
481         int gating_bit = cpu;
482
483         pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
484         if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
485                 return -EINVAL;
486
487         if (is_a83t && cpu == 0)
488                 gating_bit = 4;
489
490         /* gate processor power */
491         reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
492         reg |= PRCM_PWROFF_GATING_REG_CORE(gating_bit);
493         writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
494         udelay(20);
495
496         /* close power switch */
497         sunxi_cpu_power_switch_set(cpu, cluster, false);
498
499         return 0;
500 }
501
502 static int sunxi_cluster_powerdown(unsigned int cluster)
503 {
504         u32 reg;
505
506         pr_debug("%s: cluster %u\n", __func__, cluster);
507         if (cluster >= SUNXI_NR_CLUSTERS)
508                 return -EINVAL;
509
510         /* assert cluster resets or system will hang */
511         pr_debug("%s: assert cluster reset\n", __func__);
512         reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
513         reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
514         reg &= ~CPUCFG_CX_RST_CTRL_H_RST;
515         reg &= ~CPUCFG_CX_RST_CTRL_L2_RST;
516         writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
517
518         /* gate cluster power */
519         pr_debug("%s: gate cluster power\n", __func__);
520         reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
521         if (is_a83t)
522                 reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
523         else
524                 reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
525         writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
526         udelay(20);
527
528         return 0;
529 }
530
531 static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
532 {
533         unsigned int mpidr, cpu, cluster;
534         unsigned int tries, count;
535         int ret = 0;
536         u32 reg;
537
538         mpidr = cpu_logical_map(l_cpu);
539         cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
540         cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
541
542         /* This should never happen */
543         if (WARN_ON(cluster >= SUNXI_NR_CLUSTERS ||
544                     cpu >= SUNXI_CPUS_PER_CLUSTER))
545                 return 0;
546
547         /* wait for CPU core to die and enter WFI */
548         count = TIMEOUT_USEC / POLL_USEC;
549         spin_lock_irq(&boot_lock);
550         for (tries = 0; tries < count; tries++) {
551                 spin_unlock_irq(&boot_lock);
552                 usleep_range(POLL_USEC / 2, POLL_USEC);
553                 spin_lock_irq(&boot_lock);
554
555                 /*
556                  * If the user turns off a bunch of cores at the same
557                  * time, the kernel might call cpu_kill before some of
558                  * them are ready. This is because boot_lock serializes
559                  * both cpu_die and cpu_kill callbacks. Either one could
560                  * run first. We should wait for cpu_die to complete.
561                  */
562                 if (sunxi_mc_smp_cpu_table[cluster][cpu])
563                         continue;
564
565                 reg = readl(cpucfg_base + CPUCFG_CX_STATUS(cluster));
566                 if (reg & CPUCFG_CX_STATUS_STANDBYWFI(cpu))
567                         break;
568         }
569
570         if (tries >= count) {
571                 ret = ETIMEDOUT;
572                 goto out;
573         }
574
575         /* power down CPU core */
576         sunxi_cpu_powerdown(cpu, cluster);
577
578         if (!sunxi_mc_smp_cluster_is_down(cluster))
579                 goto out;
580
581         /* wait for cluster L2 WFI */
582         ret = readl_poll_timeout(cpucfg_base + CPUCFG_CX_STATUS(cluster), reg,
583                                  reg & CPUCFG_CX_STATUS_STANDBYWFIL2,
584                                  POLL_USEC, TIMEOUT_USEC);
585         if (ret) {
586                 /*
587                  * Ignore timeout on the cluster. Leaving the cluster on
588                  * will not affect system execution, just use a bit more
589                  * power. But returning an error here will only confuse
590                  * the user as the CPU has already been shutdown.
591                  */
592                 ret = 0;
593                 goto out;
594         }
595
596         /* Power down cluster */
597         sunxi_cluster_powerdown(cluster);
598
599 out:
600         spin_unlock_irq(&boot_lock);
601         pr_debug("%s: cluster %u cpu %u powerdown: %d\n",
602                  __func__, cluster, cpu, ret);
603         return !ret;
604 }
605
606 static bool sunxi_mc_smp_cpu_can_disable(unsigned int cpu)
607 {
608         /* CPU0 hotplug not handled for sun8i-a83t */
609         if (is_a83t)
610                 if (cpu == 0)
611                         return false;
612         return true;
613 }
614 #endif
615
616 static const struct smp_operations sunxi_mc_smp_smp_ops __initconst = {
617         .smp_secondary_init     = sunxi_mc_smp_secondary_init,
618         .smp_boot_secondary     = sunxi_mc_smp_boot_secondary,
619 #ifdef CONFIG_HOTPLUG_CPU
620         .cpu_die                = sunxi_mc_smp_cpu_die,
621         .cpu_kill               = sunxi_mc_smp_cpu_kill,
622         .cpu_can_disable        = sunxi_mc_smp_cpu_can_disable,
623 #endif
624 };
625
626 static bool __init sunxi_mc_smp_cpu_table_init(void)
627 {
628         unsigned int mpidr, cpu, cluster;
629
630         mpidr = read_cpuid_mpidr();
631         cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
632         cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
633
634         if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER) {
635                 pr_err("%s: boot CPU is out of bounds!\n", __func__);
636                 return false;
637         }
638         sunxi_mc_smp_cpu_table[cluster][cpu] = 1;
639         return true;
640 }
641
642 /*
643  * Adapted from arch/arm/common/mc_smp_entry.c
644  *
645  * We need the trampoline code to enable CCI-400 on the first cluster
646  */
647 typedef typeof(cpu_reset) phys_reset_t;
648
649 static int __init nocache_trampoline(unsigned long __unused)
650 {
651         phys_reset_t phys_reset;
652
653         setup_mm_for_reboot();
654         sunxi_cluster_cache_disable_without_axi();
655
656         phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
657         phys_reset(__pa_symbol(sunxi_mc_smp_resume), false);
658         BUG();
659 }
660
661 static int __init sunxi_mc_smp_loopback(void)
662 {
663         int ret;
664
665         /*
666          * We're going to soft-restart the current CPU through the
667          * low-level MCPM code by leveraging the suspend/resume
668          * infrastructure. Let's play it safe by using cpu_pm_enter()
669          * in case the CPU init code path resets the VFP or similar.
670          */
671         sunxi_mc_smp_first_comer = true;
672         local_irq_disable();
673         local_fiq_disable();
674         ret = cpu_pm_enter();
675         if (!ret) {
676                 ret = cpu_suspend(0, nocache_trampoline);
677                 cpu_pm_exit();
678         }
679         local_fiq_enable();
680         local_irq_enable();
681         sunxi_mc_smp_first_comer = false;
682
683         return ret;
684 }
685
686 /*
687  * This holds any device nodes that we requested resources for,
688  * so that we may easily release resources in the error path.
689  */
690 struct sunxi_mc_smp_nodes {
691         struct device_node *prcm_node;
692         struct device_node *cpucfg_node;
693         struct device_node *sram_node;
694         struct device_node *r_cpucfg_node;
695 };
696
697 /* This structure holds SoC-specific bits tied to an enable-method string. */
698 struct sunxi_mc_smp_data {
699         const char *enable_method;
700         int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
701         bool is_a83t;
702 };
703
704 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
705 {
706         of_node_put(nodes->prcm_node);
707         of_node_put(nodes->cpucfg_node);
708         of_node_put(nodes->sram_node);
709         of_node_put(nodes->r_cpucfg_node);
710         memset(nodes, 0, sizeof(*nodes));
711 }
712
713 static int __init sun9i_a80_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
714 {
715         nodes->prcm_node = of_find_compatible_node(NULL, NULL,
716                                                    "allwinner,sun9i-a80-prcm");
717         if (!nodes->prcm_node) {
718                 pr_err("%s: PRCM not available\n", __func__);
719                 return -ENODEV;
720         }
721
722         nodes->cpucfg_node = of_find_compatible_node(NULL, NULL,
723                                                      "allwinner,sun9i-a80-cpucfg");
724         if (!nodes->cpucfg_node) {
725                 pr_err("%s: CPUCFG not available\n", __func__);
726                 return -ENODEV;
727         }
728
729         nodes->sram_node = of_find_compatible_node(NULL, NULL,
730                                                    "allwinner,sun9i-a80-smp-sram");
731         if (!nodes->sram_node) {
732                 pr_err("%s: Secure SRAM not available\n", __func__);
733                 return -ENODEV;
734         }
735
736         return 0;
737 }
738
739 static int __init sun8i_a83t_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
740 {
741         nodes->prcm_node = of_find_compatible_node(NULL, NULL,
742                                                    "allwinner,sun8i-a83t-r-ccu");
743         if (!nodes->prcm_node) {
744                 pr_err("%s: PRCM not available\n", __func__);
745                 return -ENODEV;
746         }
747
748         nodes->cpucfg_node = of_find_compatible_node(NULL, NULL,
749                                                      "allwinner,sun8i-a83t-cpucfg");
750         if (!nodes->cpucfg_node) {
751                 pr_err("%s: CPUCFG not available\n", __func__);
752                 return -ENODEV;
753         }
754
755         nodes->r_cpucfg_node = of_find_compatible_node(NULL, NULL,
756                                                        "allwinner,sun8i-a83t-r-cpucfg");
757         if (!nodes->r_cpucfg_node) {
758                 pr_err("%s: RCPUCFG not available\n", __func__);
759                 return -ENODEV;
760         }
761
762         return 0;
763 }
764
765 static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] __initconst = {
766         {
767                 .enable_method  = "allwinner,sun9i-a80-smp",
768                 .get_smp_nodes  = sun9i_a80_get_smp_nodes,
769         },
770         {
771                 .enable_method  = "allwinner,sun8i-a83t-smp",
772                 .get_smp_nodes  = sun8i_a83t_get_smp_nodes,
773                 .is_a83t        = true,
774         },
775 };
776
777 static int __init sunxi_mc_smp_init(void)
778 {
779         struct sunxi_mc_smp_nodes nodes = { 0 };
780         struct device_node *node;
781         struct resource res;
782         void __iomem *addr;
783         int i, ret;
784
785         /*
786          * Don't bother checking the "cpus" node, as an enable-method
787          * property in that node is undocumented.
788          */
789         node = of_cpu_device_node_get(0);
790         if (!node)
791                 return -ENODEV;
792
793         /*
794          * We can't actually use the enable-method magic in the kernel.
795          * Our loopback / trampoline code uses the CPU suspend framework,
796          * which requires the identity mapping be available. It would not
797          * yet be available if we used the .init_cpus or .prepare_cpus
798          * callbacks in smp_operations, which we would use if we were to
799          * use CPU_METHOD_OF_DECLARE
800          */
801         for (i = 0; i < ARRAY_SIZE(sunxi_mc_smp_data); i++) {
802                 ret = of_property_match_string(node, "enable-method",
803                                                sunxi_mc_smp_data[i].enable_method);
804                 if (!ret)
805                         break;
806         }
807
808         is_a83t = sunxi_mc_smp_data[i].is_a83t;
809
810         of_node_put(node);
811         if (ret)
812                 return -ENODEV;
813
814         if (!sunxi_mc_smp_cpu_table_init())
815                 return -EINVAL;
816
817         if (!cci_probed()) {
818                 pr_err("%s: CCI-400 not available\n", __func__);
819                 return -ENODEV;
820         }
821
822         /* Get needed device tree nodes */
823         ret = sunxi_mc_smp_data[i].get_smp_nodes(&nodes);
824         if (ret)
825                 goto err_put_nodes;
826
827         /*
828          * Unfortunately we can not request the I/O region for the PRCM.
829          * It is shared with the PRCM clock.
830          */
831         prcm_base = of_iomap(nodes.prcm_node, 0);
832         if (!prcm_base) {
833                 pr_err("%s: failed to map PRCM registers\n", __func__);
834                 ret = -ENOMEM;
835                 goto err_put_nodes;
836         }
837
838         cpucfg_base = of_io_request_and_map(nodes.cpucfg_node, 0,
839                                             "sunxi-mc-smp");
840         if (IS_ERR(cpucfg_base)) {
841                 ret = PTR_ERR(cpucfg_base);
842                 pr_err("%s: failed to map CPUCFG registers: %d\n",
843                        __func__, ret);
844                 goto err_unmap_prcm;
845         }
846
847         if (is_a83t) {
848                 r_cpucfg_base = of_io_request_and_map(nodes.r_cpucfg_node,
849                                                       0, "sunxi-mc-smp");
850                 if (IS_ERR(r_cpucfg_base)) {
851                         ret = PTR_ERR(r_cpucfg_base);
852                         pr_err("%s: failed to map R-CPUCFG registers\n",
853                                __func__);
854                         goto err_unmap_release_cpucfg;
855                 }
856         } else {
857                 sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0,
858                                                         "sunxi-mc-smp");
859                 if (IS_ERR(sram_b_smp_base)) {
860                         ret = PTR_ERR(sram_b_smp_base);
861                         pr_err("%s: failed to map secure SRAM\n", __func__);
862                         goto err_unmap_release_cpucfg;
863                 }
864         }
865
866         /* Configure CCI-400 for boot cluster */
867         ret = sunxi_mc_smp_loopback();
868         if (ret) {
869                 pr_err("%s: failed to configure boot cluster: %d\n",
870                        __func__, ret);
871                 goto err_unmap_release_sram_rcpucfg;
872         }
873
874         /* We don't need the device nodes anymore */
875         sunxi_mc_smp_put_nodes(&nodes);
876
877         /* Set the hardware entry point address */
878         if (is_a83t)
879                 addr = r_cpucfg_base + R_CPUCFG_CPU_SOFT_ENTRY_REG;
880         else
881                 addr = prcm_base + PRCM_CPU_SOFT_ENTRY_REG;
882         writel(__pa_symbol(sunxi_mc_smp_secondary_startup), addr);
883
884         /* Actually enable multi cluster SMP */
885         smp_set_ops(&sunxi_mc_smp_smp_ops);
886
887         pr_info("sunxi multi cluster SMP support installed\n");
888
889         return 0;
890
891 err_unmap_release_sram_rcpucfg:
892         if (is_a83t) {
893                 iounmap(r_cpucfg_base);
894                 of_address_to_resource(nodes.r_cpucfg_node, 0, &res);
895         } else {
896                 iounmap(sram_b_smp_base);
897                 of_address_to_resource(nodes.sram_node, 0, &res);
898         }
899         release_mem_region(res.start, resource_size(&res));
900 err_unmap_release_cpucfg:
901         iounmap(cpucfg_base);
902         of_address_to_resource(nodes.cpucfg_node, 0, &res);
903         release_mem_region(res.start, resource_size(&res));
904 err_unmap_prcm:
905         iounmap(prcm_base);
906 err_put_nodes:
907         sunxi_mc_smp_put_nodes(&nodes);
908         return ret;
909 }
910
911 early_initcall(sunxi_mc_smp_init);