GNU Linux-libre 4.19.314-gnu1
[releases.git] / arch / arm / mach-sa1100 / jornada720.c
1 /*
2  * linux/arch/arm/mach-sa1100/jornada720.c
3  *
4  * HP Jornada720 init code
5  *
6  * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
7  * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
8  *  Copyright (C) 2005 Michael Gernoth <michael@gernoth.net>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  *
14  */
15
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/tty.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/machine.h>
21 #include <linux/platform_data/sa11x0-serial.h>
22 #include <linux/platform_device.h>
23 #include <linux/ioport.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/partitions.h>
26 #include <video/s1d13xxxfb.h>
27
28 #include <asm/hardware/sa1111.h>
29 #include <asm/page.h>
30 #include <asm/mach-types.h>
31 #include <asm/setup.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/flash.h>
34 #include <asm/mach/map.h>
35
36 #include <mach/hardware.h>
37 #include <mach/irqs.h>
38
39 #include "generic.h"
40
41 /*
42  * HP Documentation referred in this file:
43  * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt
44  */
45
46 /* line 110 of HP's doc */
47 #define TUCR_VAL        0x20000400
48
49 /* memory space (line 52 of HP's doc) */
50 #define SA1111REGSTART  0x40000000
51 #define SA1111REGLEN    0x00002000
52 #define EPSONREGSTART   0x48000000
53 #define EPSONREGLEN     0x00100000
54 #define EPSONFBSTART    0x48200000
55 /* 512kB framebuffer */
56 #define EPSONFBLEN      512*1024
57
58 static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
59         /* line 344 of HP's doc */
60         {0x0001,0x00},  // Miscellaneous Register
61         {0x01FC,0x00},  // Display Mode Register
62         {0x0004,0x00},  // General IO Pins Configuration Register 0
63         {0x0005,0x00},  // General IO Pins Configuration Register 1
64         {0x0008,0x00},  // General IO Pins Control Register 0
65         {0x0009,0x00},  // General IO Pins Control Register 1
66         {0x0010,0x01},  // Memory Clock Configuration Register
67         {0x0014,0x11},  // LCD Pixel Clock Configuration Register
68         {0x0018,0x01},  // CRT/TV Pixel Clock Configuration Register
69         {0x001C,0x01},  // MediaPlug Clock Configuration Register
70         {0x001E,0x01},  // CPU To Memory Wait State Select Register
71         {0x0020,0x00},  // Memory Configuration Register
72         {0x0021,0x45},  // DRAM Refresh Rate Register
73         {0x002A,0x01},  // DRAM Timings Control Register 0
74         {0x002B,0x03},  // DRAM Timings Control Register 1
75         {0x0030,0x1c},  // Panel Type Register
76         {0x0031,0x00},  // MOD Rate Register
77         {0x0032,0x4F},  // LCD Horizontal Display Width Register
78         {0x0034,0x07},  // LCD Horizontal Non-Display Period Register
79         {0x0035,0x01},  // TFT FPLINE Start Position Register
80         {0x0036,0x0B},  // TFT FPLINE Pulse Width Register
81         {0x0038,0xEF},  // LCD Vertical Display Height Register 0
82         {0x0039,0x00},  // LCD Vertical Display Height Register 1
83         {0x003A,0x13},  // LCD Vertical Non-Display Period Register
84         {0x003B,0x0B},  // TFT FPFRAME Start Position Register
85         {0x003C,0x01},  // TFT FPFRAME Pulse Width Register
86         {0x0040,0x05},  // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
87         {0x0041,0x00},  // LCD Miscellaneous Register
88         {0x0042,0x00},  // LCD Display Start Address Register 0
89         {0x0043,0x00},  // LCD Display Start Address Register 1
90         {0x0044,0x00},  // LCD Display Start Address Register 2
91         {0x0046,0x80},  // LCD Memory Address Offset Register 0
92         {0x0047,0x02},  // LCD Memory Address Offset Register 1
93         {0x0048,0x00},  // LCD Pixel Panning Register
94         {0x004A,0x00},  // LCD Display FIFO High Threshold Control Register
95         {0x004B,0x00},  // LCD Display FIFO Low Threshold Control Register
96         {0x0050,0x4F},  // CRT/TV Horizontal Display Width Register
97         {0x0052,0x13},  // CRT/TV Horizontal Non-Display Period Register
98         {0x0053,0x01},  // CRT/TV HRTC Start Position Register
99         {0x0054,0x0B},  // CRT/TV HRTC Pulse Width Register
100         {0x0056,0xDF},  // CRT/TV Vertical Display Height Register 0
101         {0x0057,0x01},  // CRT/TV Vertical Display Height Register 1
102         {0x0058,0x2B},  // CRT/TV Vertical Non-Display Period Register
103         {0x0059,0x09},  // CRT/TV VRTC Start Position Register
104         {0x005A,0x01},  // CRT/TV VRTC Pulse Width Register
105         {0x005B,0x10},  // TV Output Control Register
106         {0x0060,0x03},  // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
107         {0x0062,0x00},  // CRT/TV Display Start Address Register 0
108         {0x0063,0x00},  // CRT/TV Display Start Address Register 1
109         {0x0064,0x00},  // CRT/TV Display Start Address Register 2
110         {0x0066,0x40},  // CRT/TV Memory Address Offset Register 0
111         {0x0067,0x01},  // CRT/TV Memory Address Offset Register 1
112         {0x0068,0x00},  // CRT/TV Pixel Panning Register
113         {0x006A,0x00},  // CRT/TV Display FIFO High Threshold Control Register
114         {0x006B,0x00},  // CRT/TV Display FIFO Low Threshold Control Register
115         {0x0070,0x00},  // LCD Ink/Cursor Control Register
116         {0x0071,0x01},  // LCD Ink/Cursor Start Address Register
117         {0x0072,0x00},  // LCD Cursor X Position Register 0
118         {0x0073,0x00},  // LCD Cursor X Position Register 1
119         {0x0074,0x00},  // LCD Cursor Y Position Register 0
120         {0x0075,0x00},  // LCD Cursor Y Position Register 1
121         {0x0076,0x00},  // LCD Ink/Cursor Blue Color 0 Register
122         {0x0077,0x00},  // LCD Ink/Cursor Green Color 0 Register
123         {0x0078,0x00},  // LCD Ink/Cursor Red Color 0 Register
124         {0x007A,0x1F},  // LCD Ink/Cursor Blue Color 1 Register
125         {0x007B,0x3F},  // LCD Ink/Cursor Green Color 1 Register
126         {0x007C,0x1F},  // LCD Ink/Cursor Red Color 1 Register
127         {0x007E,0x00},  // LCD Ink/Cursor FIFO Threshold Register
128         {0x0080,0x00},  // CRT/TV Ink/Cursor Control Register
129         {0x0081,0x01},  // CRT/TV Ink/Cursor Start Address Register
130         {0x0082,0x00},  // CRT/TV Cursor X Position Register 0
131         {0x0083,0x00},  // CRT/TV Cursor X Position Register 1
132         {0x0084,0x00},  // CRT/TV Cursor Y Position Register 0
133         {0x0085,0x00},  // CRT/TV Cursor Y Position Register 1
134         {0x0086,0x00},  // CRT/TV Ink/Cursor Blue Color 0 Register
135         {0x0087,0x00},  // CRT/TV Ink/Cursor Green Color 0 Register
136         {0x0088,0x00},  // CRT/TV Ink/Cursor Red Color 0 Register
137         {0x008A,0x1F},  // CRT/TV Ink/Cursor Blue Color 1 Register
138         {0x008B,0x3F},  // CRT/TV Ink/Cursor Green Color 1 Register
139         {0x008C,0x1F},  // CRT/TV Ink/Cursor Red Color 1 Register
140         {0x008E,0x00},  // CRT/TV Ink/Cursor FIFO Threshold Register
141         {0x0100,0x00},  // BitBlt Control Register 0
142         {0x0101,0x00},  // BitBlt Control Register 1
143         {0x0102,0x00},  // BitBlt ROP Code/Color Expansion Register
144         {0x0103,0x00},  // BitBlt Operation Register
145         {0x0104,0x00},  // BitBlt Source Start Address Register 0
146         {0x0105,0x00},  // BitBlt Source Start Address Register 1
147         {0x0106,0x00},  // BitBlt Source Start Address Register 2
148         {0x0108,0x00},  // BitBlt Destination Start Address Register 0
149         {0x0109,0x00},  // BitBlt Destination Start Address Register 1
150         {0x010A,0x00},  // BitBlt Destination Start Address Register 2
151         {0x010C,0x00},  // BitBlt Memory Address Offset Register 0
152         {0x010D,0x00},  // BitBlt Memory Address Offset Register 1
153         {0x0110,0x00},  // BitBlt Width Register 0
154         {0x0111,0x00},  // BitBlt Width Register 1
155         {0x0112,0x00},  // BitBlt Height Register 0
156         {0x0113,0x00},  // BitBlt Height Register 1
157         {0x0114,0x00},  // BitBlt Background Color Register 0
158         {0x0115,0x00},  // BitBlt Background Color Register 1
159         {0x0118,0x00},  // BitBlt Foreground Color Register 0
160         {0x0119,0x00},  // BitBlt Foreground Color Register 1
161         {0x01E0,0x00},  // Look-Up Table Mode Register
162         {0x01E2,0x00},  // Look-Up Table Address Register
163         /* not sure, wouldn't like to mess with the driver */
164         {0x01E4,0x00},  // Look-Up Table Data Register
165         /* jornada doc says 0x00, but I trust the driver */
166         {0x01F0,0x10},  // Power Save Configuration Register
167         {0x01F1,0x00},  // Power Save Status Register
168         {0x01F4,0x00},  // CPU-to-Memory Access Watchdog Timer Register
169         {0x01FC,0x01},  // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
170 };
171
172 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
173         .initregs               = s1d13xxxfb_initregs,
174         .initregssize           = ARRAY_SIZE(s1d13xxxfb_initregs),
175         .platform_init_video    = NULL
176 };
177
178 static struct resource s1d13xxxfb_resources[] = {
179         [0] = DEFINE_RES_MEM(EPSONFBSTART, EPSONFBLEN),
180         [1] = DEFINE_RES_MEM(EPSONREGSTART, EPSONREGLEN),
181 };
182
183 static struct platform_device s1d13xxxfb_device = {
184         .name           = S1D_DEVICENAME,
185         .id             = 0,
186         .dev            = {
187                 .platform_data  = &s1d13xxxfb_data,
188         },
189         .num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
190         .resource       = s1d13xxxfb_resources,
191 };
192
193 static struct resource sa1111_resources[] = {
194         [0] = DEFINE_RES_MEM(SA1111REGSTART, SA1111REGLEN),
195         [1] = DEFINE_RES_IRQ(IRQ_GPIO1),
196 };
197
198 static struct sa1111_platform_data sa1111_info = {
199         .disable_devs   = SA1111_DEVID_PS2_MSE,
200 };
201
202 static u64 sa1111_dmamask = 0xffffffffUL;
203
204 static struct platform_device sa1111_device = {
205         .name           = "sa1111",
206         .id             = 0,
207         .dev            = {
208                 .dma_mask = &sa1111_dmamask,
209                 .coherent_dma_mask = 0xffffffff,
210                 .platform_data = &sa1111_info,
211         },
212         .num_resources  = ARRAY_SIZE(sa1111_resources),
213         .resource       = sa1111_resources,
214 };
215
216 static struct platform_device jornada_ssp_device = {
217         .name           = "jornada_ssp",
218         .id             = -1,
219 };
220
221 static struct resource jornada_kbd_resources[] = {
222         DEFINE_RES_IRQ(IRQ_GPIO0),
223 };
224
225 static struct platform_device jornada_kbd_device = {
226         .name           = "jornada720_kbd",
227         .id             = -1,
228         .num_resources  = ARRAY_SIZE(jornada_kbd_resources),
229         .resource       = jornada_kbd_resources,
230 };
231
232 static struct gpiod_lookup_table jornada_ts_gpiod_table = {
233         .dev_id         = "jornada_ts",
234         .table          = {
235                 GPIO_LOOKUP("gpio", 9, "penup", GPIO_ACTIVE_HIGH),
236         },
237 };
238
239 static struct platform_device jornada_ts_device = {
240         .name           = "jornada_ts",
241         .id             = -1,
242 };
243
244 static struct platform_device *devices[] __initdata = {
245         &sa1111_device,
246         &jornada_ssp_device,
247         &s1d13xxxfb_device,
248         &jornada_kbd_device,
249         &jornada_ts_device,
250 };
251
252 static int __init jornada720_init(void)
253 {
254         int ret = -ENODEV;
255
256         if (machine_is_jornada720()) {
257                 /* we want to use gpio20 as input to drive the clock of our uart 3 */
258                 GPDR |= GPIO_GPIO20;    /* Clear gpio20 pin as input */
259                 TUCR = TUCR_VAL;
260                 GPSR = GPIO_GPIO20;     /* start gpio20 pin */
261                 udelay(1);
262                 GPCR = GPIO_GPIO20;     /* stop gpio20 */
263                 udelay(1);
264                 GPSR = GPIO_GPIO20;     /* restart gpio20 */
265                 udelay(20);             /* give it some time to restart */
266
267                 gpiod_add_lookup_table(&jornada_ts_gpiod_table);
268
269                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
270         }
271
272         return ret;
273 }
274
275 arch_initcall(jornada720_init);
276
277 static struct map_desc jornada720_io_desc[] __initdata = {
278         {       /* Epson registers */
279                 .virtual        = 0xf0000000,
280                 .pfn            = __phys_to_pfn(EPSONREGSTART),
281                 .length         = EPSONREGLEN,
282                 .type           = MT_DEVICE
283         }, {    /* Epson frame buffer */
284                 .virtual        = 0xf1000000,
285                 .pfn            = __phys_to_pfn(EPSONFBSTART),
286                 .length         = EPSONFBLEN,
287                 .type           = MT_DEVICE
288         }
289 };
290
291 static void __init jornada720_map_io(void)
292 {
293         sa1100_map_io();
294         iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc));
295
296         sa1100_register_uart(0, 3);
297         sa1100_register_uart(1, 1);
298 }
299
300 static struct mtd_partition jornada720_partitions[] = {
301         {
302                 .name           = "JORNADA720 boot firmware",
303                 .size           = 0x00040000,
304                 .offset         = 0,
305                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
306         }, {
307                 .name           = "JORNADA720 kernel",
308                 .size           = 0x000c0000,
309                 .offset         = 0x00040000,
310         }, {
311                 .name           = "JORNADA720 params",
312                 .size           = 0x00040000,
313                 .offset         = 0x00100000,
314         }, {
315                 .name           = "JORNADA720 initrd",
316                 .size           = 0x00100000,
317                 .offset         = 0x00140000,
318         }, {
319                 .name           = "JORNADA720 root cramfs",
320                 .size           = 0x00300000,
321                 .offset         = 0x00240000,
322         }, {
323                 .name           = "JORNADA720 usr cramfs",
324                 .size           = 0x00800000,
325                 .offset         = 0x00540000,
326         }, {
327                 .name           = "JORNADA720 usr local",
328                 .size           = 0, /* will expand to the end of the flash */
329                 .offset         = 0x00d00000,
330         }
331 };
332
333 static void jornada720_set_vpp(int vpp)
334 {
335         if (vpp)
336                 /* enabling flash write (line 470 of HP's doc) */
337                 PPSR |= PPC_LDD7;
338         else
339                 /* disabling flash write (line 470 of HP's doc) */
340                 PPSR &= ~PPC_LDD7;
341         PPDR |= PPC_LDD7;
342 }
343
344 static struct flash_platform_data jornada720_flash_data = {
345         .map_name       = "cfi_probe",
346         .set_vpp        = jornada720_set_vpp,
347         .parts          = jornada720_partitions,
348         .nr_parts       = ARRAY_SIZE(jornada720_partitions),
349 };
350
351 static struct resource jornada720_flash_resource =
352         DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
353
354 static void __init jornada720_mach_init(void)
355 {
356         sa11x0_register_mtd(&jornada720_flash_data, &jornada720_flash_resource, 1);
357 }
358
359 MACHINE_START(JORNADA720, "HP Jornada 720")
360         /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
361         .atag_offset    = 0x100,
362         .map_io         = jornada720_map_io,
363         .nr_irqs        = SA1100_NR_IRQS,
364         .init_irq       = sa1100_init_irq,
365         .init_time      = sa1100_timer_init,
366         .init_machine   = jornada720_mach_init,
367         .init_late      = sa11x0_init_late,
368 #ifdef CONFIG_SA1111
369         .dma_zone_size  = SZ_1M,
370 #endif
371         .restart        = sa11x0_restart,
372 MACHINE_END