1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2011 Samsung Electronics Co.Ltd
4 // Author: Joonyoung Shim <jy0922.shim@samsung.com>
7 #include <linux/delay.h>
10 #include <linux/platform_device.h>
15 #include "regs-sys-s3c64xx.h"
16 #include "regs-usb-hsotg-phy-s3c64xx.h"
18 enum samsung_usb_phy_type {
23 static int s3c_usb_otgphy_init(struct platform_device *pdev)
28 writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
30 /* set clock frequency for PLL */
31 phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
33 xusbxti = clk_get(&pdev->dev, "xusbxti");
34 if (!IS_ERR(xusbxti)) {
35 switch (clk_get_rate(xusbxti)) {
37 phyclk |= S3C_PHYCLK_CLKSEL_12M;
40 phyclk |= S3C_PHYCLK_CLKSEL_24M;
44 /* default reference clock */
50 /* TODO: select external clock/oscillator */
51 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
53 /* set to normal OTG PHY */
54 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
57 /* reset OTG PHY and Link */
58 writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
60 udelay(20); /* at-least 10uS */
61 writel(0, S3C_RSTCON);
66 static int s3c_usb_otgphy_exit(struct platform_device *pdev)
68 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
69 S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
71 writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
76 int s3c_usb_phy_init(struct platform_device *pdev, int type)
78 if (type == USB_PHY_TYPE_DEVICE)
79 return s3c_usb_otgphy_init(pdev);
84 int s3c_usb_phy_exit(struct platform_device *pdev, int type)
86 if (type == USB_PHY_TYPE_DEVICE)
87 return s3c_usb_otgphy_exit(pdev);