arch/arm/mach-s3c/mach-bast.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2003-2008 Simtec Electronics
   4 //   Ben Dooks <ben@simtec.co.uk>
   5 //
   6 // http://www.simtec.co.uk/products/EB2410ITX/
   7
   8 #include <linux/kernel.h>
   9 #include <linux/types.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/list.h>
  12 #include <linux/timer.h>
  13 #include <linux/init.h>
  14 #include <linux/gpio.h>
  15 #include <linux/syscore_ops.h>
  16 #include <linux/serial_core.h>
  17 #include <linux/serial_s3c.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/dm9000.h>
  20 #include <linux/ata_platform.h>
  21 #include <linux/i2c.h>
  22 #include <linux/io.h>
  23 #include <linux/serial_8250.h>
  24
  25 #include <linux/mtd/mtd.h>
  26 #include <linux/mtd/rawnand.h>
  27 #include <linux/mtd/nand-ecc-sw-hamming.h>
  28 #include <linux/mtd/partitions.h>
  29
  30 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
  31 #include <linux/platform_data/hwmon-s3c.h>
  32 #include <linux/platform_data/i2c-s3c2410.h>
  33 #include <linux/platform_data/mtd-nand-s3c2410.h>
  34
  35 #include <net/ax88796.h>
  36
  37 #include <asm/irq.h>
  38 #include <asm/mach/arch.h>
  39 #include <asm/mach/map.h>
  40 #include <asm/mach/irq.h>
  41 #include <asm/mach-types.h>
  42
  43 #include <linux/platform_data/fb-s3c2410.h>
  44 #include "regs-gpio.h"
  45 #include "gpio-samsung.h"
  46
  47 #include "cpu.h"
  48 #include <linux/soc/samsung/s3c-cpu-freq.h>
  49 #include "devs.h"
  50 #include "gpio-cfg.h"
  51
  52 #include "bast.h"
  53 #include "s3c24xx.h"
  54 #include "simtec.h"
  55
  56 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
  57
  58 /* macros for virtual address mods for the io space entries */
  59 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
  60 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
  61 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
  62 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
  63
  64 /* macros to modify the physical addresses for io space */
  65
  66 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
  67 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
  68 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
  69 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
  70
  71 static struct map_desc bast_iodesc[] __initdata = {
  72   /* ISA IO areas */
  73   {
  74           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  75           .pfn          = PA_CS2(BAST_PA_ISAIO),
  76           .length       = SZ_16M,
  77           .type         = MT_DEVICE,
  78   },
  79   /* bast CPLD control registers, and external interrupt controls */
  80   {
  81           .virtual      = (u32)BAST_VA_CTRL1,
  82           .pfn          = __phys_to_pfn(BAST_PA_CTRL1),
  83           .length       = SZ_1M,
  84           .type         = MT_DEVICE,
  85   }, {
  86           .virtual      = (u32)BAST_VA_CTRL2,
  87           .pfn          = __phys_to_pfn(BAST_PA_CTRL2),
  88           .length       = SZ_1M,
  89           .type         = MT_DEVICE,
  90   }, {
  91           .virtual      = (u32)BAST_VA_CTRL3,
  92           .pfn          = __phys_to_pfn(BAST_PA_CTRL3),
  93           .length       = SZ_1M,
  94           .type         = MT_DEVICE,
  95   }, {
  96           .virtual      = (u32)BAST_VA_CTRL4,
  97           .pfn          = __phys_to_pfn(BAST_PA_CTRL4),
  98           .length       = SZ_1M,
  99           .type         = MT_DEVICE,
 100   },
 101   /* PC104 IRQ mux */
 102   {
 103           .virtual      = (u32)BAST_VA_PC104_IRQREQ,
 104           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
 105           .length       = SZ_1M,
 106           .type         = MT_DEVICE,
 107   }, {
 108           .virtual      = (u32)BAST_VA_PC104_IRQRAW,
 109           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
 110           .length       = SZ_1M,
 111           .type         = MT_DEVICE,
 112   }, {
 113           .virtual      = (u32)BAST_VA_PC104_IRQMASK,
 114           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
 115           .length       = SZ_1M,
 116           .type         = MT_DEVICE,
 117   },
 118
 119   /* peripheral space... one for each of fast/slow/byte/16bit */
 120   /* note, ide is only decoded in word space, even though some registers
 121    * are only 8bit */
 122
 123   /* slow, byte */
 124   { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 125   { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 126   { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 127
 128   /* slow, word */
 129   { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 130   { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 131   { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 132
 133   /* fast, byte */
 134   { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 135   { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 136   { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 137
 138   /* fast, word */
 139   { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 140   { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 141   { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 142 };
 143
 144 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 145 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 146 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 147
 148 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 149         [0] = {
 150                 .hwport      = 0,
 151                 .flags       = 0,
 152                 .ucon        = UCON,
 153                 .ulcon       = ULCON,
 154                 .ufcon       = UFCON,
 155         },
 156         [1] = {
 157                 .hwport      = 1,
 158                 .flags       = 0,
 159                 .ucon        = UCON,
 160                 .ulcon       = ULCON,
 161                 .ufcon       = UFCON,
 162         },
 163         /* port 2 is not actually used */
 164         [2] = {
 165                 .hwport      = 2,
 166                 .flags       = 0,
 167                 .ucon        = UCON,
 168                 .ulcon       = ULCON,
 169                 .ufcon       = UFCON,
 170         }
 171 };
 172
 173 /* NAND Flash on BAST board */
 174
 175 #ifdef CONFIG_PM
 176 static int bast_pm_suspend(void)
 177 {
 178         /* ensure that an nRESET is not generated on resume. */
 179         gpio_direction_output(S3C2410_GPA(21), 1);
 180         return 0;
 181 }
 182
 183 static void bast_pm_resume(void)
 184 {
 185         s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 186 }
 187
 188 #else
 189 #define bast_pm_suspend NULL
 190 #define bast_pm_resume NULL
 191 #endif
 192
 193 static struct syscore_ops bast_pm_syscore_ops = {
 194         .suspend        = bast_pm_suspend,
 195         .resume         = bast_pm_resume,
 196 };
 197
 198 static int smartmedia_map[] = { 0 };
 199 static int chip0_map[] = { 1 };
 200 static int chip1_map[] = { 2 };
 201 static int chip2_map[] = { 3 };
 202
 203 static struct mtd_partition __initdata bast_default_nand_part[] = {
 204         [0] = {
 205                 .name   = "Boot Agent",
 206                 .size   = SZ_16K,
 207                 .offset = 0,
 208         },
 209         [1] = {
 210                 .name   = "/boot",
 211                 .size   = SZ_4M - SZ_16K,
 212                 .offset = SZ_16K,
 213         },
 214         [2] = {
 215                 .name   = "user",
 216                 .offset = SZ_4M,
 217                 .size   = MTDPART_SIZ_FULL,
 218         }
 219 };
 220
 221 /* the bast has 4 selectable slots for nand-flash, the three
 222  * on-board chip areas, as well as the external SmartMedia
 223  * slot.
 224  *
 225  * Note, there is no current hot-plug support for the SmartMedia
 226  * socket.
 227 */
 228
 229 static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
 230         [0] = {
 231                 .name           = "SmartMedia",
 232                 .nr_chips       = 1,
 233                 .nr_map         = smartmedia_map,
 234                 .options        = NAND_SCAN_SILENT_NODEV,
 235                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 236                 .partitions     = bast_default_nand_part,
 237         },
 238         [1] = {
 239                 .name           = "chip0",
 240                 .nr_chips       = 1,
 241                 .nr_map         = chip0_map,
 242                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 243                 .partitions     = bast_default_nand_part,
 244         },
 245         [2] = {
 246                 .name           = "chip1",
 247                 .nr_chips       = 1,
 248                 .nr_map         = chip1_map,
 249                 .options        = NAND_SCAN_SILENT_NODEV,
 250                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 251                 .partitions     = bast_default_nand_part,
 252         },
 253         [3] = {
 254                 .name           = "chip2",
 255                 .nr_chips       = 1,
 256                 .nr_map         = chip2_map,
 257                 .options        = NAND_SCAN_SILENT_NODEV,
 258                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 259                 .partitions     = bast_default_nand_part,
 260         }
 261 };
 262
 263 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
 264 {
 265         unsigned int tmp;
 266
 267         slot = set->nr_map[slot] & 3;
 268
 269         pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
 270                  slot, set, set->nr_map);
 271
 272         tmp = __raw_readb(BAST_VA_CTRL2);
 273         tmp &= BAST_CPLD_CTLR2_IDERST;
 274         tmp |= slot;
 275         tmp |= BAST_CPLD_CTRL2_WNAND;
 276
 277         pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
 278
 279         __raw_writeb(tmp, BAST_VA_CTRL2);
 280 }
 281
 282 static struct s3c2410_platform_nand __initdata bast_nand_info = {
 283         .tacls          = 30,
 284         .twrph0         = 60,
 285         .twrph1         = 60,
 286         .nr_sets        = ARRAY_SIZE(bast_nand_sets),
 287         .sets           = bast_nand_sets,
 288         .select_chip    = bast_nand_select,
 289         .engine_type    = NAND_ECC_ENGINE_TYPE_SOFT,
 290 };
 291
 292 /* DM9000 */
 293
 294 static struct resource bast_dm9k_resource[] = {
 295         [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
 296         [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
 297         [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
 298                                         | IORESOURCE_IRQ_HIGHLEVEL),
 299 };
 300
 301 /* for the moment we limit ourselves to 16bit IO until some
 302  * better IO routines can be written and tested
 303 */
 304
 305 static struct dm9000_plat_data bast_dm9k_platdata = {
 306         .flags          = DM9000_PLATF_16BITONLY,
 307 };
 308
 309 static struct platform_device bast_device_dm9k = {
 310         .name           = "dm9000",
 311         .id             = 0,
 312         .num_resources  = ARRAY_SIZE(bast_dm9k_resource),
 313         .resource       = bast_dm9k_resource,
 314         .dev            = {
 315                 .platform_data = &bast_dm9k_platdata,
 316         }
 317 };
 318
 319 /* serial devices */
 320
 321 #define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
 322 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
 323 #define SERIAL_CLK   (1843200)
 324
 325 static struct plat_serial8250_port bast_sio_data[] = {
 326         [0] = {
 327                 .mapbase        = SERIAL_BASE + 0x2f8,
 328                 .irq            = BAST_IRQ_PCSERIAL1,
 329                 .flags          = SERIAL_FLAGS,
 330                 .iotype         = UPIO_MEM,
 331                 .regshift       = 0,
 332                 .uartclk        = SERIAL_CLK,
 333         },
 334         [1] = {
 335                 .mapbase        = SERIAL_BASE + 0x3f8,
 336                 .irq            = BAST_IRQ_PCSERIAL2,
 337                 .flags          = SERIAL_FLAGS,
 338                 .iotype         = UPIO_MEM,
 339                 .regshift       = 0,
 340                 .uartclk        = SERIAL_CLK,
 341         },
 342         { }
 343 };
 344
 345 static struct platform_device bast_sio = {
 346         .name                   = "serial8250",
 347         .id                     = PLAT8250_DEV_PLATFORM,
 348         .dev                    = {
 349                 .platform_data  = &bast_sio_data,
 350         },
 351 };
 352
 353 /* we have devices on the bus which cannot work much over the
 354  * standard 100KHz i2c bus frequency
 355 */
 356
 357 static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
 358         .flags          = 0,
 359         .slave_addr     = 0x10,
 360         .frequency      = 100*1000,
 361 };
 362
 363 /* Asix AX88796 10/100 ethernet controller */
 364
 365 static struct ax_plat_data bast_asix_platdata = {
 366         .flags          = AXFLG_MAC_FROMDEV,
 367         .wordlength     = 2,
 368         .dcr_val        = 0x48,
 369         .rcr_val        = 0x40,
 370 };
 371
 372 static struct resource bast_asix_resource[] = {
 373         [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
 374         [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
 375         [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX),
 376 };
 377
 378 static struct platform_device bast_device_asix = {
 379         .name           = "ax88796",
 380         .id             = 0,
 381         .num_resources  = ARRAY_SIZE(bast_asix_resource),
 382         .resource       = bast_asix_resource,
 383         .dev            = {
 384                 .platform_data = &bast_asix_platdata
 385         }
 386 };
 387
 388 /* Asix AX88796 10/100 ethernet controller parallel port */
 389
 390 static struct resource bast_asixpp_resource[] = {
 391         [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \
 392                                         0x30 * 0x20),
 393 };
 394
 395 static struct platform_device bast_device_axpp = {
 396         .name           = "ax88796-pp",
 397         .id             = 0,
 398         .num_resources  = ARRAY_SIZE(bast_asixpp_resource),
 399         .resource       = bast_asixpp_resource,
 400 };
 401
 402 /* LCD/VGA controller */
 403
 404 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
 405         {
 406                 .type           = S3C2410_LCDCON1_TFT,
 407                 .width          = 640,
 408                 .height         = 480,
 409
 410                 .pixclock       = 33333,
 411                 .xres           = 640,
 412                 .yres           = 480,
 413                 .bpp            = 4,
 414                 .left_margin    = 40,
 415                 .right_margin   = 20,
 416                 .hsync_len      = 88,
 417                 .upper_margin   = 30,
 418                 .lower_margin   = 32,
 419                 .vsync_len      = 3,
 420
 421                 .lcdcon5        = 0x00014b02,
 422         },
 423         {
 424                 .type           = S3C2410_LCDCON1_TFT,
 425                 .width          = 640,
 426                 .height         = 480,
 427
 428                 .pixclock       = 33333,
 429                 .xres           = 640,
 430                 .yres           = 480,
 431                 .bpp            = 8,
 432                 .left_margin    = 40,
 433                 .right_margin   = 20,
 434                 .hsync_len      = 88,
 435                 .upper_margin   = 30,
 436                 .lower_margin   = 32,
 437                 .vsync_len      = 3,
 438
 439                 .lcdcon5        = 0x00014b02,
 440         },
 441         {
 442                 .type           = S3C2410_LCDCON1_TFT,
 443                 .width          = 640,
 444                 .height         = 480,
 445
 446                 .pixclock       = 33333,
 447                 .xres           = 640,
 448                 .yres           = 480,
 449                 .bpp            = 16,
 450                 .left_margin    = 40,
 451                 .right_margin   = 20,
 452                 .hsync_len      = 88,
 453                 .upper_margin   = 30,
 454                 .lower_margin   = 32,
 455                 .vsync_len      = 3,
 456
 457                 .lcdcon5        = 0x00014b02,
 458         },
 459 };
 460
 461 /* LCD/VGA controller */
 462
 463 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
 464
 465         .displays = bast_lcd_info,
 466         .num_displays = ARRAY_SIZE(bast_lcd_info),
 467         .default_display = 1,
 468 };
 469
 470 /* I2C devices fitted. */
 471
 472 static struct i2c_board_info bast_i2c_devs[] __initdata = {
 473         {
 474                 I2C_BOARD_INFO("tlv320aic23", 0x1a),
 475         }, {
 476                 I2C_BOARD_INFO("simtec-pmu", 0x6b),
 477         }, {
 478                 I2C_BOARD_INFO("ch7013", 0x75),
 479         },
 480 };
 481
 482 static struct s3c_hwmon_pdata bast_hwmon_info = {
 483         /* LCD contrast (0-6.6V) */
 484         .in[0] = &(struct s3c_hwmon_chcfg) {
 485                 .name           = "lcd-contrast",
 486                 .mult           = 3300,
 487                 .div            = 512,
 488         },
 489         /* LED current feedback */
 490         .in[1] = &(struct s3c_hwmon_chcfg) {
 491                 .name           = "led-feedback",
 492                 .mult           = 3300,
 493                 .div            = 1024,
 494         },
 495         /* LCD feedback (0-6.6V) */
 496         .in[2] = &(struct s3c_hwmon_chcfg) {
 497                 .name           = "lcd-feedback",
 498                 .mult           = 3300,
 499                 .div            = 512,
 500         },
 501         /* Vcore (1.8-2.0V), Vref 3.3V  */
 502         .in[3] = &(struct s3c_hwmon_chcfg) {
 503                 .name           = "vcore",
 504                 .mult           = 3300,
 505                 .div            = 1024,
 506         },
 507 };
 508
 509 /* Standard BAST devices */
 510 // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
 511
 512 static struct platform_device *bast_devices[] __initdata = {
 513         &s3c2410_device_dclk,
 514         &s3c_device_ohci,
 515         &s3c_device_lcd,
 516         &s3c_device_wdt,
 517         &s3c_device_i2c0,
 518         &s3c_device_rtc,
 519         &s3c_device_nand,
 520         &s3c_device_adc,
 521         &s3c_device_hwmon,
 522         &bast_device_dm9k,
 523         &bast_device_asix,
 524         &bast_device_axpp,
 525         &bast_sio,
 526 };
 527
 528 static struct s3c_cpufreq_board __initdata bast_cpufreq = {
 529         .refresh        = 7800, /* 7.8usec */
 530         .auto_io        = 1,
 531         .need_io        = 1,
 532 };
 533
 534 static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
 535         .have_mic       = 1,
 536         .have_lout      = 1,
 537 };
 538
 539 static void __init bast_map_io(void)
 540 {
 541         s3c_hwmon_set_platdata(&bast_hwmon_info);
 542
 543         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
 544         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
 545         s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
 546 }
 547
 548 static void __init bast_init_time(void)
 549 {
 550         s3c2410_init_clocks(12000000);
 551         s3c24xx_timer_init();
 552 }
 553
 554 static void __init bast_init(void)
 555 {
 556         register_syscore_ops(&bast_pm_syscore_ops);
 557
 558         s3c_i2c0_set_platdata(&bast_i2c_info);
 559         s3c_nand_set_platdata(&bast_nand_info);
 560         s3c24xx_fb_set_platdata(&bast_fb_info);
 561         platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
 562
 563         i2c_register_board_info(0, bast_i2c_devs,
 564                                 ARRAY_SIZE(bast_i2c_devs));
 565
 566         usb_simtec_init();
 567         nor_simtec_init();
 568         simtec_audio_add(NULL, true, &bast_audio);
 569
 570         WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
 571
 572         s3c_cpufreq_setboard(&bast_cpufreq);
 573 }
 574
 575 MACHINE_START(BAST, "Simtec-BAST")
 576         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 577         .atag_offset    = 0x100,
 578         .nr_irqs        = NR_IRQS_S3C2410,
 579         .map_io         = bast_map_io,
 580         .init_irq       = s3c2410_init_irq,
 581         .init_machine   = bast_init,
 582         .init_time      = bast_init_time,
 583 MACHINE_END