1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Intel Reference Systems cplds
5 * Copyright (C) 2014 Robert Jarzmik
7 * Cplds motherboard driver, supporting lubbock and mainstone SoC board.
10 #include <linux/bitops.h>
11 #include <linux/gpio.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/mfd/core.h>
18 #include <linux/module.h>
19 #include <linux/of_platform.h>
21 #define FPGA_IRQ_MASK_EN 0x0
22 #define FPGA_IRQ_SET_CLR 0x10
24 #define CPLDS_NB_IRQ 32
29 unsigned int irq_mask;
30 struct gpio_desc *gpio0;
31 struct irq_domain *irqdomain;
34 static irqreturn_t cplds_irq_handler(int in_irq, void *d)
36 struct cplds *fpga = d;
37 unsigned long pending;
41 pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask;
42 for_each_set_bit(bit, &pending, CPLDS_NB_IRQ)
43 generic_handle_domain_irq(fpga->irqdomain, bit);
49 static void cplds_irq_mask(struct irq_data *d)
51 struct cplds *fpga = irq_data_get_irq_chip_data(d);
52 unsigned int cplds_irq = irqd_to_hwirq(d);
53 unsigned int bit = BIT(cplds_irq);
55 fpga->irq_mask &= ~bit;
56 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
59 static void cplds_irq_unmask(struct irq_data *d)
61 struct cplds *fpga = irq_data_get_irq_chip_data(d);
62 unsigned int cplds_irq = irqd_to_hwirq(d);
63 unsigned int set, bit = BIT(cplds_irq);
65 set = readl(fpga->base + FPGA_IRQ_SET_CLR);
66 writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR);
68 fpga->irq_mask |= bit;
69 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
72 static struct irq_chip cplds_irq_chip = {
74 .irq_ack = cplds_irq_mask,
75 .irq_mask = cplds_irq_mask,
76 .irq_unmask = cplds_irq_unmask,
77 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
80 static int cplds_irq_domain_map(struct irq_domain *d, unsigned int irq,
81 irq_hw_number_t hwirq)
83 struct cplds *fpga = d->host_data;
85 irq_set_chip_and_handler(irq, &cplds_irq_chip, handle_level_irq);
86 irq_set_chip_data(irq, fpga);
91 static const struct irq_domain_ops cplds_irq_domain_ops = {
92 .xlate = irq_domain_xlate_twocell,
93 .map = cplds_irq_domain_map,
96 static int cplds_resume(struct platform_device *pdev)
98 struct cplds *fpga = platform_get_drvdata(pdev);
100 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
105 static int cplds_probe(struct platform_device *pdev)
107 struct resource *res;
111 unsigned long irqflags = 0;
113 fpga = devm_kzalloc(&pdev->dev, sizeof(*fpga), GFP_KERNEL);
117 fpga->irq = platform_get_irq(pdev, 0);
121 base_irq = platform_get_irq(pdev, 1);
125 ret = devm_irq_alloc_descs(&pdev->dev, base_irq, base_irq, CPLDS_NB_IRQ, 0);
130 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
131 fpga->base = devm_ioremap_resource(&pdev->dev, res);
132 if (IS_ERR(fpga->base))
133 return PTR_ERR(fpga->base);
135 platform_set_drvdata(pdev, fpga);
137 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
138 writel(0, fpga->base + FPGA_IRQ_SET_CLR);
140 irqflags = irq_get_trigger_type(fpga->irq);
141 ret = devm_request_irq(&pdev->dev, fpga->irq, cplds_irq_handler,
142 irqflags, dev_name(&pdev->dev), fpga);
144 return -EPROBE_DEFER;
147 dev_err(&pdev->dev, "couldn't request main irq%d: %d\n",
152 irq_set_irq_wake(fpga->irq, 1);
154 fpga->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
157 &cplds_irq_domain_ops,
160 fpga->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
162 &cplds_irq_domain_ops,
164 if (!fpga->irqdomain)
170 static int cplds_remove(struct platform_device *pdev)
172 struct cplds *fpga = platform_get_drvdata(pdev);
174 irq_set_chip_and_handler(fpga->irq, NULL, NULL);
179 static const struct of_device_id cplds_id_table[] = {
180 { .compatible = "intel,lubbock-cplds-irqs", },
181 { .compatible = "intel,mainstone-cplds-irqs", },
184 MODULE_DEVICE_TABLE(of, cplds_id_table);
186 static struct platform_driver cplds_driver = {
188 .name = "pxa_cplds_irqs",
189 .of_match_table = of_match_ptr(cplds_id_table),
191 .probe = cplds_probe,
192 .remove = cplds_remove,
193 .resume = cplds_resume,
196 module_platform_driver(cplds_driver);
198 MODULE_DESCRIPTION("PXA Cplds interrupts driver");
199 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
200 MODULE_LICENSE("GPL");