1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/pxa3xx.c
5 * code specific to pxa3xx aka Monahans
7 * Copyright (C) 2006 Marvell International Ltd.
9 * 2007-09-02: eric miao <eric.miao@marvell.com>
12 #include <linux/dmaengine.h>
13 #include <linux/dma/pxa-dma.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/gpio-pxa.h>
19 #include <linux/platform_device.h>
20 #include <linux/irq.h>
21 #include <linux/irqchip.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/platform_data/i2c-pxa.h>
26 #include <linux/platform_data/mmp_dma.h>
27 #include <linux/soc/pxa/cpu.h>
28 #include <linux/clk/pxa.h>
30 #include <asm/mach/map.h>
31 #include <asm/suspend.h>
32 #include "pxa3xx-regs.h"
34 #include <linux/platform_data/usb-ohci-pxa27x.h>
43 #define PECR_IE(n) ((1 << ((n) * 2)) << 28)
44 #define PECR_IS(n) ((1 << ((n) * 2)) << 29)
46 extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
49 * NAND NFC: DFI bus arbitration subset
51 #define NDCR (*(volatile u32 __iomem*)(NAND_VIRT + 0))
52 #define NDCR_ND_ARB_EN (1 << 12)
53 #define NDCR_ND_ARB_CNTL (1 << 19)
55 #define CKEN_BOOT 11 /* < Boot rom clock enable */
56 #define CKEN_TPM 19 /* < TPM clock enable */
57 #define CKEN_HSIO2 41 /* < HSIO2 clock enable */
61 #define ISRAM_START 0x5c000000
62 #define ISRAM_SIZE SZ_256K
64 static void __iomem *sram;
65 static unsigned long wakeup_src;
68 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
69 * memory controller has to be reinitialised, so we place some code
70 * in the SRAM to perform this function.
72 * We disable FIQs across the standby - otherwise, we might receive a
73 * FIQ while the SDRAM is unavailable.
75 static void pxa3xx_cpu_standby(unsigned int pwrmode)
77 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
79 memcpy_toio(sram + 0x8000, pm_enter_standby_start,
80 pm_enter_standby_end - pm_enter_standby_start);
98 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
99 * PXA3xx development kits assumes that the resuming process continues
100 * with the address stored within the first 4 bytes of SDRAM. The PSPR
101 * register is used privately by BootROM and OBM, and _must_ be set to
102 * 0x5c014000 for the moment.
104 static void pxa3xx_cpu_pm_suspend(void)
106 volatile unsigned long *p = (volatile void *)0xc0000000;
107 unsigned long saved_data = *p;
108 #ifndef CONFIG_IWMMXT
111 asm volatile(".arch_extension xscale\n\t"
112 "mra %Q0, %R0, acc0" : "=r" (acc0));
115 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
116 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
117 CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
119 /* clear and setup wakeup source */
125 PCFR |= (1u << 13); /* L1_DIS */
126 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
130 /* overwrite with the resume address */
131 *p = __pa_symbol(cpu_resume);
133 cpu_suspend(0, pxa3xx_finish_suspend);
139 #ifndef CONFIG_IWMMXT
140 asm volatile(".arch_extension xscale\n\t"
141 "mar acc0, %Q0, %R0" : "=r" (acc0));
145 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
148 * Don't sleep if no wakeup sources are defined
150 if (wakeup_src == 0) {
151 printk(KERN_ERR "Not suspending: no wakeup sources\n");
156 case PM_SUSPEND_STANDBY:
157 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
161 pxa3xx_cpu_pm_suspend();
166 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
168 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
171 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
172 .valid = pxa3xx_cpu_pm_valid,
173 .enter = pxa3xx_cpu_pm_enter,
176 static void __init pxa3xx_init_pm(void)
178 sram = ioremap(ISRAM_START, ISRAM_SIZE);
180 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
185 * Since we copy wakeup code into the SRAM, we need to ensure
186 * that it is preserved over the low power modes. Note: bit 8
187 * is undocumented in the developer manual, but must be set.
189 AD1R |= ADXR_L2 | ADXR_R0;
190 AD2R |= ADXR_L2 | ADXR_R0;
191 AD3R |= ADXR_L2 | ADXR_R0;
194 * Clear the resume enable registers.
201 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
204 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
206 unsigned long flags, mask = 0;
210 mask = ADXER_MFP_WSSP3;
223 mask = ADXER_MFP_WAC97;
229 mask = ADXER_MFP_WSSP2;
232 mask = ADXER_MFP_WI2C;
235 mask = ADXER_MFP_WUART3;
238 mask = ADXER_MFP_WUART2;
241 mask = ADXER_MFP_WUART1;
244 mask = ADXER_MFP_WMMC1;
247 mask = ADXER_MFP_WSSP1;
253 mask = ADXER_MFP_WSSP4;
262 mask = ADXER_MFP_WMMC2;
265 mask = ADXER_MFP_WFLASH;
271 mask = ADXER_WEXTWAKE0;
274 mask = ADXER_WEXTWAKE1;
277 mask = ADXER_MFP_GEN12;
283 local_irq_save(flags);
288 local_irq_restore(flags);
293 static inline void pxa3xx_init_pm(void) {}
294 #define pxa3xx_set_wake NULL
297 static void pxa_ack_ext_wakeup(struct irq_data *d)
299 PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
302 static void pxa_mask_ext_wakeup(struct irq_data *d)
305 PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
308 static void pxa_unmask_ext_wakeup(struct irq_data *d)
311 PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
314 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
316 if (flow_type & IRQ_TYPE_EDGE_RISING)
317 PWER |= 1 << (d->irq - IRQ_WAKEUP0);
319 if (flow_type & IRQ_TYPE_EDGE_FALLING)
320 PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
325 static struct irq_chip pxa_ext_wakeup_chip = {
327 .irq_ack = pxa_ack_ext_wakeup,
328 .irq_mask = pxa_mask_ext_wakeup,
329 .irq_unmask = pxa_unmask_ext_wakeup,
330 .irq_set_type = pxa_set_ext_wakeup_type,
333 static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
338 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
339 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
341 irq_clear_status_flags(irq, IRQ_NOREQUEST);
344 pxa_ext_wakeup_chip.irq_set_wake = fn;
347 static void __init __pxa3xx_init_irq(void)
349 /* enable CP6 access */
351 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
353 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
355 pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
358 void __init pxa3xx_init_irq(void)
361 pxa_init_irq(56, pxa3xx_set_wake);
365 static int __init __init
366 pxa3xx_dt_init_irq(struct device_node *node, struct device_node *parent)
369 pxa_dt_irq_init(pxa3xx_set_wake);
370 set_handle_irq(ichp_handle_irq);
374 IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq);
375 #endif /* CONFIG_OF */
377 static struct map_desc pxa3xx_io_desc[] __initdata = {
379 .virtual = (unsigned long)SMEMC_VIRT,
380 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
381 .length = SMEMC_SIZE,
384 .virtual = (unsigned long)NAND_VIRT,
385 .pfn = __phys_to_pfn(NAND_PHYS),
391 void __init pxa3xx_map_io(void)
394 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
395 pxa3xx_get_clk_frequency_khz(1);
399 * device registration specific to PXA3xx.
402 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
404 pxa_register_device(&pxa3xx_device_i2c_power, info);
407 static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
408 .irq_base = PXA_GPIO_TO_IRQ(0),
411 static struct platform_device *devices[] __initdata = {
415 &pxa_device_asoc_ssp1,
416 &pxa_device_asoc_ssp2,
417 &pxa_device_asoc_ssp3,
418 &pxa_device_asoc_ssp4,
419 &pxa_device_asoc_platform,
429 static const struct dma_slave_map pxa3xx_slave_map[] = {
430 /* PXA25x, PXA27x and PXA3xx common entries */
431 { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
432 { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
433 { "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
434 PDMA_FILTER_PARAM(LOWEST, 10) },
435 { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
436 { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
437 { "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
438 { "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
439 { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
440 { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
441 { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
442 { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
443 { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
444 { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
445 { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) },
446 { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) },
448 /* PXA3xx specific map */
449 { "pxa-ssp-dai.3", "rx", PDMA_FILTER_PARAM(LOWEST, 2) },
450 { "pxa-ssp-dai.3", "tx", PDMA_FILTER_PARAM(LOWEST, 3) },
451 { "pxa2xx-mci.1", "rx", PDMA_FILTER_PARAM(LOWEST, 93) },
452 { "pxa2xx-mci.1", "tx", PDMA_FILTER_PARAM(LOWEST, 94) },
453 { "pxa3xx-nand", "data", PDMA_FILTER_PARAM(LOWEST, 97) },
454 { "pxa2xx-mci.2", "rx", PDMA_FILTER_PARAM(LOWEST, 100) },
455 { "pxa2xx-mci.2", "tx", PDMA_FILTER_PARAM(LOWEST, 101) },
458 static struct mmp_dma_platdata pxa3xx_dma_pdata = {
460 .nb_requestors = 100,
461 .slave_map = pxa3xx_slave_map,
462 .slave_map_cnt = ARRAY_SIZE(pxa3xx_slave_map),
465 static int __init pxa3xx_init(void)
469 if (cpu_is_pxa3xx()) {
471 pxa_register_wdt(ARSR);
474 * clear RDH bit every time after reset
476 * Note: the last 3 bits DxS are write-1-to-clear so carefully
477 * preserve them here in case they will be referenced later
479 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
482 * Disable DFI bus arbitration, to prevent a system bus lock if
483 * somebody disables the NAND clock (unused clock) while this
486 NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL;
490 enable_irq_wake(IRQ_WAKEUP0);
492 enable_irq_wake(IRQ_WAKEUP1);
494 register_syscore_ops(&pxa_irq_syscore_ops);
495 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
497 if (of_have_populated_dt())
500 pxa2xx_set_dmac_info(&pxa3xx_dma_pdata);
501 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
504 if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
505 platform_device_add_data(&pxa3xx_device_gpio,
507 sizeof(pxa3xx_gpio_pdata));
508 ret = platform_device_register(&pxa3xx_device_gpio);
515 postcore_initcall(pxa3xx_init);