2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
6 * Copyright (C) 2009 Nokia Corporation
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
18 * Some parts based off of TI's 24xx code:
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
42 #include <linux/platform_device.h>
43 #include <linux/platform_data/dmtimer-omap.h>
44 #include <linux/sched_clock.h>
46 #include <asm/mach/time.h>
47 #include <asm/smp_twd.h>
49 #include "omap_hwmod.h"
50 #include "omap_device.h"
51 #include <plat/counter-32k.h>
52 #include <plat/dmtimer.h>
58 #include "powerdomain.h"
59 #include "omap-secure.h"
61 #define REALTIME_COUNTER_BASE 0x48243200
62 #define INCREMENTER_NUMERATOR_OFFSET 0x10
63 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
64 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
68 static struct omap_dm_timer clkev;
69 static struct clock_event_device clockevent_gpt;
71 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
72 static unsigned long arch_timer_freq;
74 void set_cntfreq(void)
76 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
80 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
82 struct clock_event_device *evt = &clockevent_gpt;
84 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
86 evt->event_handler(evt);
90 static struct irqaction omap2_gp_timer_irq = {
92 .flags = IRQF_TIMER | IRQF_IRQPOLL,
93 .handler = omap2_gp_timer_interrupt,
96 static int omap2_gp_timer_set_next_event(unsigned long cycles,
97 struct clock_event_device *evt)
99 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
100 0xffffffff - cycles, OMAP_TIMER_POSTED);
105 static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
107 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
111 static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
115 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
117 period = clkev.rate / HZ;
119 /* Looks like we need to first set the load value separately */
120 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
122 __omap_dm_timer_load_start(&clkev,
123 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
124 0xffffffff - period, OMAP_TIMER_POSTED);
128 static struct clock_event_device clockevent_gpt = {
129 .features = CLOCK_EVT_FEAT_PERIODIC |
130 CLOCK_EVT_FEAT_ONESHOT,
132 .set_next_event = omap2_gp_timer_set_next_event,
133 .set_state_shutdown = omap2_gp_timer_shutdown,
134 .set_state_periodic = omap2_gp_timer_set_periodic,
135 .set_state_oneshot = omap2_gp_timer_shutdown,
136 .tick_resume = omap2_gp_timer_shutdown,
139 static const struct of_device_id omap_timer_match[] __initconst = {
140 { .compatible = "ti,omap2420-timer", },
141 { .compatible = "ti,omap3430-timer", },
142 { .compatible = "ti,omap4430-timer", },
143 { .compatible = "ti,omap5430-timer", },
144 { .compatible = "ti,dm814-timer", },
145 { .compatible = "ti,dm816-timer", },
146 { .compatible = "ti,am335x-timer", },
147 { .compatible = "ti,am335x-timer-1ms", },
152 * omap_get_timer_dt - get a timer using device-tree
153 * @match - device-tree match structure for matching a device type
154 * @property - optional timer property to match
156 * Helper function to get a timer during early boot using device-tree for use
157 * as kernel system timer. Optionally, the property argument can be used to
158 * select a timer with a specific property. Once a timer is found then mark
159 * the timer node in device-tree as disabled, to prevent the kernel from
160 * registering this timer as a platform device and so no one else can use it.
162 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
163 const char *property)
165 struct device_node *np;
167 for_each_matching_node(np, match) {
168 if (!of_device_is_available(np))
171 if (property && !of_get_property(np, property, NULL))
174 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
175 of_get_property(np, "ti,timer-dsp", NULL) ||
176 of_get_property(np, "ti,timer-pwm", NULL) ||
177 of_get_property(np, "ti,timer-secure", NULL)))
180 if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
181 struct property *prop;
183 prop = kzalloc(sizeof(*prop), GFP_KERNEL);
186 prop->name = "status";
187 prop->value = "disabled";
188 prop->length = strlen(prop->value);
189 of_add_property(np, prop);
198 * omap_dmtimer_init - initialisation function when device tree is used
200 * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
201 * cannot be used by the kernel as they are reserved. Therefore, to prevent the
202 * kernel registering these devices remove them dynamically from the device
205 static void __init omap_dmtimer_init(void)
207 struct device_node *np;
209 if (!cpu_is_omap34xx() && !soc_is_dra7xx())
212 /* If we are a secure device, remove any secure timer nodes */
213 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
214 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
220 * omap_dm_timer_get_errata - get errata flags for a timer
222 * Get the timer errata flags that are specific to the OMAP device being used.
224 static u32 __init omap_dm_timer_get_errata(void)
226 if (cpu_is_omap24xx())
229 return OMAP_TIMER_ERRATA_I103_I767;
232 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
233 const char *fck_source,
234 const char *property,
235 const char **timer_name,
238 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
239 const char *oh_name = NULL;
240 struct device_node *np;
241 struct omap_hwmod *oh;
242 struct resource irq, mem;
246 if (of_have_populated_dt()) {
247 np = omap_get_timer_dt(omap_timer_match, property);
251 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
255 timer->irq = irq_of_parse_and_map(np, 0);
259 timer->io_base = of_iomap(np, 0);
263 if (omap_dm_timer_reserve_systimer(timer->id))
266 sprintf(name, "timer%d", timer->id);
270 oh = omap_hwmod_lookup(oh_name);
274 *timer_name = oh->name;
276 if (!of_have_populated_dt()) {
277 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
281 timer->irq = irq.start;
283 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
288 /* Static mapping, never released */
289 timer->io_base = ioremap(mem.start, mem.end - mem.start);
295 omap_hwmod_setup_one(oh_name);
297 /* After the dmtimer is using hwmod these clocks won't be needed */
298 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
299 if (IS_ERR(timer->fclk))
300 return PTR_ERR(timer->fclk);
302 src = clk_get(NULL, fck_source);
306 WARN(clk_set_parent(timer->fclk, src) < 0,
307 "Cannot set timer parent clock, no PLL clock driver?");
311 omap_hwmod_enable(oh);
312 __omap_dm_timer_init_regs(timer);
315 __omap_dm_timer_enable_posted(timer);
317 /* Check that the intended posted configuration matches the actual */
318 if (posted != timer->posted)
321 timer->rate = clk_get_rate(timer->fclk);
327 #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
328 void tick_broadcast(const struct cpumask *mask)
333 static void __init omap2_gp_clockevent_init(int gptimer_id,
334 const char *fck_source,
335 const char *property)
339 clkev.id = gptimer_id;
340 clkev.errata = omap_dm_timer_get_errata();
343 * For clock-event timers we never read the timer counter and
344 * so we are not impacted by errata i103 and i767. Therefore,
345 * we can safely ignore this errata for clock-event timers.
347 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
349 res = omap_dm_timer_init_one(&clkev, fck_source, property,
350 &clockevent_gpt.name, OMAP_TIMER_POSTED);
353 omap2_gp_timer_irq.dev_id = &clkev;
354 setup_irq(clkev.irq, &omap2_gp_timer_irq);
356 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
358 clockevent_gpt.cpumask = cpu_possible_mask;
359 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
360 clockevents_config_and_register(&clockevent_gpt, clkev.rate,
361 3, /* Timer internal resynch latency */
364 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
368 /* Clocksource code */
369 static struct omap_dm_timer clksrc;
370 static bool use_gptimer_clksrc __initdata;
375 static cycle_t clocksource_read_cycles(struct clocksource *cs)
377 return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
378 OMAP_TIMER_NONPOSTED);
381 static struct clocksource clocksource_gpt = {
383 .read = clocksource_read_cycles,
384 .mask = CLOCKSOURCE_MASK(32),
385 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
388 static u64 notrace dmtimer_read_sched_clock(void)
391 return __omap_dm_timer_read_counter(&clksrc,
392 OMAP_TIMER_NONPOSTED);
397 static const struct of_device_id omap_counter_match[] __initconst = {
398 { .compatible = "ti,omap-counter32k", },
402 /* Setup free-running counter for clocksource */
403 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
406 struct device_node *np = NULL;
407 struct omap_hwmod *oh;
408 const char *oh_name = "counter_32k";
411 * If device-tree is present, then search the DT blob
412 * to see if the 32kHz counter is supported.
414 if (of_have_populated_dt()) {
415 np = omap_get_timer_dt(omap_counter_match, NULL);
419 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
425 * First check hwmod data is available for sync32k counter
427 oh = omap_hwmod_lookup(oh_name);
428 if (!oh || oh->slaves_cnt == 0)
431 omap_hwmod_setup_one(oh_name);
433 ret = omap_hwmod_enable(oh);
435 pr_warn("%s: failed to enable counter_32k module (%d)\n",
440 if (!of_have_populated_dt()) {
443 vbase = omap_hwmod_get_mpu_rt_va(oh);
445 ret = omap_init_clocksource_32k(vbase);
447 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
455 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
456 const char *fck_source,
457 const char *property)
461 clksrc.id = gptimer_id;
462 clksrc.errata = omap_dm_timer_get_errata();
464 res = omap_dm_timer_init_one(&clksrc, fck_source, property,
465 &clocksource_gpt.name,
466 OMAP_TIMER_NONPOSTED);
469 __omap_dm_timer_load_start(&clksrc,
470 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
471 OMAP_TIMER_NONPOSTED);
472 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
474 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
475 pr_err("Could not register clocksource %s\n",
476 clocksource_gpt.name);
478 pr_info("OMAP clocksource: %s at %lu Hz\n",
479 clocksource_gpt.name, clksrc.rate);
482 static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
483 const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
484 const char *clksrc_prop, bool gptimer)
488 omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
490 /* Enable the use of clocksource="gp_timer" kernel parameter */
491 if (use_gptimer_clksrc || gptimer)
492 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
495 omap2_sync32k_clocksource_init();
498 void __init omap_init_time(void)
500 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
501 2, "timer_sys_ck", NULL, false);
506 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
507 void __init omap3_secure_sync32k_timer_init(void)
509 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
510 2, "timer_sys_ck", NULL, false);
514 #endif /* CONFIG_ARCH_OMAP3 */
516 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
517 defined(CONFIG_SOC_AM43XX)
518 void __init omap3_gptimer_timer_init(void)
520 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
521 1, "timer_sys_ck", "ti,timer-alwon", true);
522 if (of_have_populated_dt())
527 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
528 defined(CONFIG_SOC_DRA7XX)
529 static void __init omap4_sync32k_timer_init(void)
531 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
532 2, "sys_clkin_ck", NULL, false);
535 void __init omap4_local_timer_init(void)
537 omap4_sync32k_timer_init();
542 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
545 * The realtime counter also called master counter, is a free-running
546 * counter, which is related to real time. It produces the count used
547 * by the CPU local timer peripherals in the MPU cluster. The timer counts
548 * at a rate of 6.144 MHz. Because the device operates on different clocks
549 * in different power modes, the master counter shifts operation between
550 * clocks, adjusting the increment per clock in hardware accordingly to
551 * maintain a constant count rate.
553 static void __init realtime_counter_init(void)
555 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
557 static struct clk *sys_clk;
560 unsigned long long num, den;
562 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
564 pr_err("%s: ioremap failed\n", __func__);
567 sys_clk = clk_get(NULL, "sys_clkin");
568 if (IS_ERR(sys_clk)) {
569 pr_err("%s: failed to get system clock handle\n", __func__);
574 rate = clk_get_rate(sys_clk);
576 if (soc_is_dra7xx()) {
578 * Errata i856 says the 32.768KHz crystal does not start at
579 * power on, so the CPU falls back to an emulated 32KHz clock
580 * based on sysclk / 610 instead. This causes the master counter
581 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
582 * (OR sysclk * 75 / 244)
584 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
585 * Of course any board built without a populated 32.768KHz
586 * crystal would also need this fix even if the CPU is fixed
589 * Either case can be detected by using the two speedselect bits
590 * If they are not 0, then the 32.768KHz clock driving the
591 * coarse counter that corrects the fine counter every time it
592 * ticks is actually rate/610 rather than 32.768KHz and we
593 * should compensate to avoid the 570ppm (at 20MHz, much worse
594 * at other rates) too fast system time.
596 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
597 if (reg & DRA7_SPEEDSELECT_MASK) {
604 /* Numerator/denumerator values refer TRM Realtime Counter section */
632 /* Program it for 38.4 MHz */
639 /* Program numerator and denumerator registers */
640 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
641 NUMERATOR_DENUMERATOR_MASK;
643 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
645 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
646 NUMERATOR_DENUMERATOR_MASK;
648 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
650 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
657 void __init omap5_realtime_timer_init(void)
659 omap4_sync32k_timer_init();
660 realtime_counter_init();
664 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
667 * omap_timer_init - build and register timer device with an
668 * associated timer hwmod
669 * @oh: timer hwmod pointer to be used to build timer device
670 * @user: parameter that can be passed from calling hwmod API
672 * Called by omap_hwmod_for_each_by_class to register each of the timer
673 * devices present in the system. The number of timer devices is known
674 * by parsing through the hwmod database for a given class name. At the
675 * end of function call memory is allocated for timer device and it is
676 * registered to the framework ready to be proved by the driver.
678 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
682 char *name = "omap_timer";
683 struct dmtimer_platform_data *pdata;
684 struct platform_device *pdev;
685 struct omap_timer_capability_dev_attr *timer_dev_attr;
687 pr_debug("%s: %s\n", __func__, oh->name);
689 /* on secure device, do not register secure timer */
690 timer_dev_attr = oh->dev_attr;
691 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
692 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
695 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
697 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
702 * Extract the IDs from name field in hwmod database
703 * and use the same for constructing ids' for the
704 * timer devices. In a way, we are avoiding usage of
705 * static variable witin the function to do the same.
706 * CAUTION: We have to be careful and make sure the
707 * name in hwmod database does not change in which case
708 * we might either make corresponding change here or
709 * switch back static variable mechanism.
711 sscanf(oh->name, "timer%2d", &id);
714 pdata->timer_capability = timer_dev_attr->timer_capability;
716 pdata->timer_errata = omap_dm_timer_get_errata();
717 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
719 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata));
722 pr_err("%s: Can't build omap_device for %s: %s.\n",
723 __func__, name, oh->name);
733 * omap2_dm_timer_init - top level regular device initialization
735 * Uses dedicated hwmod api to parse through hwmod database for
736 * given class name and then build and register the timer device.
738 static int __init omap2_dm_timer_init(void)
742 /* If dtb is there, the devices will be created dynamically */
743 if (of_have_populated_dt())
746 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
748 pr_err("%s: device registration failed.\n", __func__);
754 omap_arch_initcall(omap2_dm_timer_init);
757 * omap2_override_clocksource - clocksource override with user configuration
759 * Allows user to override default clocksource, using kernel parameter
760 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
762 * Note that, here we are using same standard kernel parameter "clocksource=",
763 * and not introducing any OMAP specific interface.
765 static int __init omap2_override_clocksource(char *str)
770 * For OMAP architecture, we only have two options
771 * - sync_32k (default)
772 * - gp_timer (sys_clk based)
774 if (!strcmp(str, "gp_timer"))
775 use_gptimer_clksrc = true;
779 early_param("clocksource", omap2_override_clocksource);