2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
6 * Copyright (C) 2009 Nokia Corporation
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
18 * Some parts based off of TI's 24xx code:
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
42 #include <linux/platform_device.h>
43 #include <linux/platform_data/dmtimer-omap.h>
44 #include <linux/sched_clock.h>
45 #include <linux/cpu.h>
47 #include <asm/mach/time.h>
49 #include "omap_hwmod.h"
50 #include "omap_device.h"
51 #include <plat/counter-32k.h>
52 #include <clocksource/timer-ti-dm.h>
57 #include "powerdomain.h"
58 #include "omap-secure.h"
60 #define REALTIME_COUNTER_BASE 0x48243200
61 #define INCREMENTER_NUMERATOR_OFFSET 0x10
62 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
63 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
67 /* Clockevent hwmod for am335x and am437x suspend */
68 static struct omap_hwmod *clockevent_gpt_hwmod;
70 /* Clockesource hwmod for am437x suspend */
71 static struct omap_hwmod *clocksource_gpt_hwmod;
73 struct dmtimer_clockevent {
74 struct clock_event_device dev;
75 struct omap_dm_timer timer;
78 static struct dmtimer_clockevent clockevent;
80 static struct omap_dm_timer *to_dmtimer(struct clock_event_device *clockevent)
82 struct dmtimer_clockevent *clkevt =
83 container_of(clockevent, struct dmtimer_clockevent, dev);
84 struct omap_dm_timer *timer = &clkevt->timer;
89 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
90 static unsigned long arch_timer_freq;
92 void set_cntfreq(void)
94 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
98 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
100 struct dmtimer_clockevent *clkevt = dev_id;
101 struct clock_event_device *evt = &clkevt->dev;
102 struct omap_dm_timer *timer = &clkevt->timer;
104 __omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW);
105 evt->event_handler(evt);
109 static int omap2_gp_timer_set_next_event(unsigned long cycles,
110 struct clock_event_device *evt)
112 struct omap_dm_timer *timer = to_dmtimer(evt);
114 __omap_dm_timer_load_start(timer, OMAP_TIMER_CTRL_ST,
115 0xffffffff - cycles, OMAP_TIMER_POSTED);
120 static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
122 struct omap_dm_timer *timer = to_dmtimer(evt);
124 __omap_dm_timer_stop(timer, OMAP_TIMER_POSTED, timer->rate);
129 static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
131 struct omap_dm_timer *timer = to_dmtimer(evt);
134 __omap_dm_timer_stop(timer, OMAP_TIMER_POSTED, timer->rate);
136 period = timer->rate / HZ;
138 /* Looks like we need to first set the load value separately */
139 __omap_dm_timer_write(timer, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
141 __omap_dm_timer_load_start(timer,
142 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
143 0xffffffff - period, OMAP_TIMER_POSTED);
147 static void omap_clkevt_idle(struct clock_event_device *unused)
149 if (!clockevent_gpt_hwmod)
152 omap_hwmod_idle(clockevent_gpt_hwmod);
155 static void omap_clkevt_unidle(struct clock_event_device *evt)
157 struct omap_dm_timer *timer = to_dmtimer(evt);
159 if (!clockevent_gpt_hwmod)
162 omap_hwmod_enable(clockevent_gpt_hwmod);
163 __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW);
166 static const struct of_device_id omap_timer_match[] __initconst = {
167 { .compatible = "ti,omap2420-timer", },
168 { .compatible = "ti,omap3430-timer", },
169 { .compatible = "ti,omap4430-timer", },
170 { .compatible = "ti,omap5430-timer", },
171 { .compatible = "ti,dm814-timer", },
172 { .compatible = "ti,dm816-timer", },
173 { .compatible = "ti,am335x-timer", },
174 { .compatible = "ti,am335x-timer-1ms", },
178 static int omap_timer_add_disabled_property(struct device_node *np)
180 struct property *prop;
182 prop = kzalloc(sizeof(*prop), GFP_KERNEL);
186 prop->name = "status";
187 prop->value = "disabled";
188 prop->length = strlen(prop->value);
190 return of_add_property(np, prop);
193 static int omap_timer_update_dt(struct device_node *np)
197 if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
198 error = omap_timer_add_disabled_property(np);
203 /* No parent interconnect target module configured? */
204 if (of_get_property(np, "ti,hwmods", NULL))
207 /* Tag parent interconnect target module disabled */
208 error = omap_timer_add_disabled_property(np->parent);
216 * omap_get_timer_dt - get a timer using device-tree
217 * @match - device-tree match structure for matching a device type
218 * @property - optional timer property to match
220 * Helper function to get a timer during early boot using device-tree for use
221 * as kernel system timer. Optionally, the property argument can be used to
222 * select a timer with a specific property. Once a timer is found then mark
223 * the timer node in device-tree as disabled, to prevent the kernel from
224 * registering this timer as a platform device and so no one else can use it.
226 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
227 const char *property)
229 struct device_node *np;
232 for_each_matching_node(np, match) {
233 if (!of_device_is_available(np))
236 if (property && !of_get_property(np, property, NULL))
239 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
240 of_get_property(np, "ti,timer-dsp", NULL) ||
241 of_get_property(np, "ti,timer-pwm", NULL) ||
242 of_get_property(np, "ti,timer-secure", NULL)))
245 error = omap_timer_update_dt(np);
246 WARN(error, "%s: Could not update dt: %i\n", __func__, error);
255 * omap_dmtimer_init - initialisation function when device tree is used
257 * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
258 * cannot be used by the kernel as they are reserved. Therefore, to prevent the
259 * kernel registering these devices remove them dynamically from the device
262 static void __init omap_dmtimer_init(void)
264 struct device_node *np;
266 if (!cpu_is_omap34xx() && !soc_is_dra7xx())
269 /* If we are a secure device, remove any secure timer nodes */
270 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
271 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
277 * omap_dm_timer_get_errata - get errata flags for a timer
279 * Get the timer errata flags that are specific to the OMAP device being used.
281 static u32 __init omap_dm_timer_get_errata(void)
283 if (cpu_is_omap24xx())
286 return OMAP_TIMER_ERRATA_I103_I767;
289 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
290 const char *fck_source,
291 const char *property,
292 const char **timer_name,
295 const char *oh_name = NULL;
296 struct device_node *np;
297 struct omap_hwmod *oh;
301 np = omap_get_timer_dt(omap_timer_match, property);
305 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
307 of_property_read_string_index(np->parent, "ti,hwmods", 0,
313 timer->irq = irq_of_parse_and_map(np, 0);
317 timer->io_base = of_iomap(np, 0);
319 timer->fclk = of_clk_get_by_name(np, "fck");
323 oh = omap_hwmod_lookup(oh_name);
327 *timer_name = oh->name;
332 omap_hwmod_setup_one(oh_name);
334 /* After the dmtimer is using hwmod these clocks won't be needed */
335 if (IS_ERR_OR_NULL(timer->fclk))
336 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
337 if (IS_ERR(timer->fclk))
338 return PTR_ERR(timer->fclk);
340 src = clk_get(NULL, fck_source);
344 WARN(clk_set_parent(timer->fclk, src) < 0,
345 "Cannot set timer parent clock, no PLL clock driver?");
349 omap_hwmod_enable(oh);
350 __omap_dm_timer_init_regs(timer);
353 __omap_dm_timer_enable_posted(timer);
355 /* Check that the intended posted configuration matches the actual */
356 if (posted != timer->posted)
359 timer->rate = clk_get_rate(timer->fclk);
365 #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
366 void tick_broadcast(const struct cpumask *mask)
371 static void __init dmtimer_clkevt_init_common(struct dmtimer_clockevent *clkevt,
373 const char *fck_source,
374 unsigned int features,
375 const struct cpumask *cpumask,
376 const char *property,
377 int rating, const char *name)
379 struct omap_dm_timer *timer = &clkevt->timer;
382 timer->id = gptimer_id;
383 timer->errata = omap_dm_timer_get_errata();
384 clkevt->dev.features = features;
385 clkevt->dev.rating = rating;
386 clkevt->dev.set_next_event = omap2_gp_timer_set_next_event;
387 clkevt->dev.set_state_shutdown = omap2_gp_timer_shutdown;
388 clkevt->dev.set_state_periodic = omap2_gp_timer_set_periodic;
389 clkevt->dev.set_state_oneshot = omap2_gp_timer_shutdown;
390 clkevt->dev.tick_resume = omap2_gp_timer_shutdown;
393 * For clock-event timers we never read the timer counter and
394 * so we are not impacted by errata i103 and i767. Therefore,
395 * we can safely ignore this errata for clock-event timers.
397 __omap_dm_timer_override_errata(timer, OMAP_TIMER_ERRATA_I103_I767);
399 res = omap_dm_timer_init_one(timer, fck_source, property,
400 &clkevt->dev.name, OMAP_TIMER_POSTED);
403 clkevt->dev.cpumask = cpumask;
404 clkevt->dev.irq = omap_dm_timer_get_irq(timer);
406 if (request_irq(clkevt->dev.irq, omap2_gp_timer_interrupt,
407 IRQF_TIMER | IRQF_IRQPOLL, name, clkevt))
408 pr_err("Failed to request irq %d (gp_timer)\n", clkevt->dev.irq);
410 __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW);
412 if (soc_is_am33xx() || soc_is_am43xx()) {
413 clkevt->dev.suspend = omap_clkevt_idle;
414 clkevt->dev.resume = omap_clkevt_unidle;
416 clockevent_gpt_hwmod =
417 omap_hwmod_lookup(clkevt->dev.name);
420 pr_info("OMAP clockevent source: %s at %lu Hz\n", clkevt->dev.name,
424 static DEFINE_PER_CPU(struct dmtimer_clockevent, dmtimer_percpu_timer);
426 static int omap_gptimer_starting_cpu(unsigned int cpu)
428 struct dmtimer_clockevent *clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
429 struct clock_event_device *dev = &clkevt->dev;
430 struct omap_dm_timer *timer = &clkevt->timer;
432 clockevents_config_and_register(dev, timer->rate, 3, ULONG_MAX);
433 irq_force_affinity(dev->irq, cpumask_of(cpu));
438 static int __init dmtimer_percpu_quirk_init(void)
440 struct dmtimer_clockevent *clkevt;
441 struct clock_event_device *dev;
442 struct device_node *arm_timer;
443 struct omap_dm_timer *timer;
446 arm_timer = of_find_compatible_node(NULL, NULL, "arm,armv7-timer");
447 if (of_device_is_available(arm_timer)) {
448 pr_warn_once("ARM architected timer wrap issue i940 detected\n");
452 for_each_possible_cpu(cpu) {
453 clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
455 timer = &clkevt->timer;
457 dmtimer_clkevt_init_common(clkevt, 0, "timer_sys_ck",
458 CLOCK_EVT_FEAT_ONESHOT,
460 "assigned-clock-parents",
461 500, "percpu timer");
464 cpuhp_setup_state(CPUHP_AP_OMAP_DM_TIMER_STARTING,
465 "clockevents/omap/gptimer:starting",
466 omap_gptimer_starting_cpu, NULL);
471 /* Clocksource code */
472 static struct omap_dm_timer clksrc;
473 static bool use_gptimer_clksrc __initdata;
478 static u64 clocksource_read_cycles(struct clocksource *cs)
480 return (u64)__omap_dm_timer_read_counter(&clksrc,
481 OMAP_TIMER_NONPOSTED);
484 static struct clocksource clocksource_gpt = {
486 .read = clocksource_read_cycles,
487 .mask = CLOCKSOURCE_MASK(32),
488 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
491 static u64 notrace dmtimer_read_sched_clock(void)
494 return __omap_dm_timer_read_counter(&clksrc,
495 OMAP_TIMER_NONPOSTED);
500 static const struct of_device_id omap_counter_match[] __initconst = {
501 { .compatible = "ti,omap-counter32k", },
505 /* Setup free-running counter for clocksource */
506 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
509 struct device_node *np = NULL;
510 struct omap_hwmod *oh;
511 const char *oh_name = "counter_32k";
514 * See if the 32kHz counter is supported.
516 np = omap_get_timer_dt(omap_counter_match, NULL);
520 of_property_read_string_index(np->parent, "ti,hwmods", 0, &oh_name);
522 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
528 * First check hwmod data is available for sync32k counter
530 oh = omap_hwmod_lookup(oh_name);
531 if (!oh || oh->slaves_cnt == 0)
534 omap_hwmod_setup_one(oh_name);
536 ret = omap_hwmod_enable(oh);
538 pr_warn("%s: failed to enable counter_32k module (%d)\n",
546 static unsigned int omap2_gptimer_clksrc_load;
548 static void omap2_gptimer_clksrc_suspend(struct clocksource *unused)
550 omap2_gptimer_clksrc_load =
551 __omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED);
553 omap_hwmod_idle(clocksource_gpt_hwmod);
556 static void omap2_gptimer_clksrc_resume(struct clocksource *unused)
558 omap_hwmod_enable(clocksource_gpt_hwmod);
560 __omap_dm_timer_load_start(&clksrc,
561 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
562 omap2_gptimer_clksrc_load,
563 OMAP_TIMER_NONPOSTED);
566 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
567 const char *fck_source,
568 const char *property)
572 clksrc.id = gptimer_id;
573 clksrc.errata = omap_dm_timer_get_errata();
575 res = omap_dm_timer_init_one(&clksrc, fck_source, property,
576 &clocksource_gpt.name,
577 OMAP_TIMER_NONPOSTED);
579 if (soc_is_am43xx()) {
580 clocksource_gpt.suspend = omap2_gptimer_clksrc_suspend;
581 clocksource_gpt.resume = omap2_gptimer_clksrc_resume;
583 clocksource_gpt_hwmod =
584 omap_hwmod_lookup(clocksource_gpt.name);
589 __omap_dm_timer_load_start(&clksrc,
590 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
591 OMAP_TIMER_NONPOSTED);
592 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
594 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
595 pr_err("Could not register clocksource %s\n",
596 clocksource_gpt.name);
598 pr_info("OMAP clocksource: %s at %lu Hz\n",
599 clocksource_gpt.name, clksrc.rate);
602 static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
603 const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
604 const char *clksrc_prop, bool gptimer)
608 dmtimer_clkevt_init_common(&clockevent, clkev_nr, clkev_src,
609 CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
610 cpu_possible_mask, clkev_prop, 300, "clockevent");
611 clockevents_config_and_register(&clockevent.dev, clockevent.timer.rate,
612 3, /* Timer internal resynch latency */
616 dmtimer_percpu_quirk_init();
618 /* Enable the use of clocksource="gp_timer" kernel parameter */
619 if (use_gptimer_clksrc || gptimer)
620 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
623 omap2_sync32k_clocksource_init();
626 void __init omap_init_time(void)
628 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
629 2, "timer_sys_ck", NULL, false);
634 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
635 void __init omap3_secure_sync32k_timer_init(void)
637 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
638 2, "timer_sys_ck", NULL, false);
642 #endif /* CONFIG_ARCH_OMAP3 */
644 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
645 defined(CONFIG_SOC_AM43XX) || defined(CONFIG_SOC_DRA7XX)
646 void __init omap3_gptimer_timer_init(void)
648 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
649 1, "timer_sys_ck", "ti,timer-alwon", true);
650 if (of_have_populated_dt())
655 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
656 defined(CONFIG_SOC_DRA7XX)
657 static void __init omap4_sync32k_timer_init(void)
659 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
660 2, "sys_clkin_ck", NULL, false);
663 void __init omap4_local_timer_init(void)
665 omap4_sync32k_timer_init();
670 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
673 * The realtime counter also called master counter, is a free-running
674 * counter, which is related to real time. It produces the count used
675 * by the CPU local timer peripherals in the MPU cluster. The timer counts
676 * at a rate of 6.144 MHz. Because the device operates on different clocks
677 * in different power modes, the master counter shifts operation between
678 * clocks, adjusting the increment per clock in hardware accordingly to
679 * maintain a constant count rate.
681 static void __init realtime_counter_init(void)
683 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
685 static struct clk *sys_clk;
688 unsigned long long num, den;
690 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
692 pr_err("%s: ioremap failed\n", __func__);
695 sys_clk = clk_get(NULL, "sys_clkin");
696 if (IS_ERR(sys_clk)) {
697 pr_err("%s: failed to get system clock handle\n", __func__);
702 rate = clk_get_rate(sys_clk);
705 if (soc_is_dra7xx()) {
707 * Errata i856 says the 32.768KHz crystal does not start at
708 * power on, so the CPU falls back to an emulated 32KHz clock
709 * based on sysclk / 610 instead. This causes the master counter
710 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
711 * (OR sysclk * 75 / 244)
713 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
714 * Of course any board built without a populated 32.768KHz
715 * crystal would also need this fix even if the CPU is fixed
718 * Either case can be detected by using the two speedselect bits
719 * If they are not 0, then the 32.768KHz clock driving the
720 * coarse counter that corrects the fine counter every time it
721 * ticks is actually rate/610 rather than 32.768KHz and we
722 * should compensate to avoid the 570ppm (at 20MHz, much worse
723 * at other rates) too fast system time.
725 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
726 if (reg & DRA7_SPEEDSELECT_MASK) {
733 /* Numerator/denumerator values refer TRM Realtime Counter section */
761 /* Program it for 38.4 MHz */
768 /* Program numerator and denumerator registers */
769 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
770 NUMERATOR_DENUMERATOR_MASK;
772 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
774 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
775 NUMERATOR_DENUMERATOR_MASK;
777 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
779 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
786 void __init omap5_realtime_timer_init(void)
788 omap4_sync32k_timer_init();
789 realtime_counter_init();
793 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
796 * omap2_override_clocksource - clocksource override with user configuration
798 * Allows user to override default clocksource, using kernel parameter
799 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
801 * Note that, here we are using same standard kernel parameter "clocksource=",
802 * and not introducing any OMAP specific interface.
804 static int __init omap2_override_clocksource(char *str)
809 * For OMAP architecture, we only have two options
810 * - sync_32k (default)
811 * - gp_timer (sys_clk based)
813 if (!strcmp(str, "gp_timer"))
814 use_gptimer_clksrc = true;
818 early_param("clocksource", omap2_override_clocksource);