arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39 #include <linux/of.h>
  40 #include <linux/of_address.h>
  41 #include <linux/of_irq.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/platform_data/dmtimer-omap.h>
  44 #include <linux/sched_clock.h>
  45 #include <linux/cpu.h>
  46
  47 #include <asm/mach/time.h>
  48 #include <asm/smp_twd.h>
  49
  50 #include "omap_hwmod.h"
  51 #include "omap_device.h"
  52 #include <plat/counter-32k.h>
  53 #include <clocksource/timer-ti-dm.h>
  54
  55 #include "soc.h"
  56 #include "common.h"
  57 #include "control.h"
  58 #include "powerdomain.h"
  59 #include "omap-secure.h"
  60
  61 #define REALTIME_COUNTER_BASE                           0x48243200
  62 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
  63 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
  64 #define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
  65
  66 /* Clockevent code */
  67
  68 /* Clockevent hwmod for am335x and am437x suspend */
  69 static struct omap_hwmod *clockevent_gpt_hwmod;
  70
  71 /* Clockesource hwmod for am437x suspend */
  72 static struct omap_hwmod *clocksource_gpt_hwmod;
  73
  74 struct dmtimer_clockevent {
  75         struct clock_event_device dev;
  76         struct omap_dm_timer timer;
  77 };
  78
  79 static struct dmtimer_clockevent clockevent;
  80
  81 static struct omap_dm_timer *to_dmtimer(struct clock_event_device *clockevent)
  82 {
  83         struct dmtimer_clockevent *clkevt =
  84                 container_of(clockevent, struct dmtimer_clockevent, dev);
  85         struct omap_dm_timer *timer = &clkevt->timer;
  86
  87         return timer;
  88 }
  89
  90 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
  91 static unsigned long arch_timer_freq;
  92
  93 void set_cntfreq(void)
  94 {
  95         omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
  96 }
  97 #endif
  98
  99 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 100 {
 101         struct dmtimer_clockevent *clkevt = dev_id;
 102         struct clock_event_device *evt = &clkevt->dev;
 103         struct omap_dm_timer *timer = &clkevt->timer;
 104
 105         __omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW);
 106         evt->event_handler(evt);
 107         return IRQ_HANDLED;
 108 }
 109
 110 static int omap2_gp_timer_set_next_event(unsigned long cycles,
 111                                          struct clock_event_device *evt)
 112 {
 113         struct omap_dm_timer *timer = to_dmtimer(evt);
 114
 115         __omap_dm_timer_load_start(timer, OMAP_TIMER_CTRL_ST,
 116                                    0xffffffff - cycles, OMAP_TIMER_POSTED);
 117
 118         return 0;
 119 }
 120
 121 static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
 122 {
 123         struct omap_dm_timer *timer = to_dmtimer(evt);
 124
 125         __omap_dm_timer_stop(timer, OMAP_TIMER_POSTED, timer->rate);
 126
 127         return 0;
 128 }
 129
 130 static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
 131 {
 132         struct omap_dm_timer *timer = to_dmtimer(evt);
 133         u32 period;
 134
 135         __omap_dm_timer_stop(timer, OMAP_TIMER_POSTED, timer->rate);
 136
 137         period = timer->rate / HZ;
 138         period -= 1;
 139         /* Looks like we need to first set the load value separately */
 140         __omap_dm_timer_write(timer, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
 141                               OMAP_TIMER_POSTED);
 142         __omap_dm_timer_load_start(timer,
 143                                    OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 144                                    0xffffffff - period, OMAP_TIMER_POSTED);
 145         return 0;
 146 }
 147
 148 static void omap_clkevt_idle(struct clock_event_device *unused)
 149 {
 150         if (!clockevent_gpt_hwmod)
 151                 return;
 152
 153         omap_hwmod_idle(clockevent_gpt_hwmod);
 154 }
 155
 156 static void omap_clkevt_unidle(struct clock_event_device *evt)
 157 {
 158         struct omap_dm_timer *timer = to_dmtimer(evt);
 159
 160         if (!clockevent_gpt_hwmod)
 161                 return;
 162
 163         omap_hwmod_enable(clockevent_gpt_hwmod);
 164         __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW);
 165 }
 166
 167 static const struct of_device_id omap_timer_match[] __initconst = {
 168         { .compatible = "ti,omap2420-timer", },
 169         { .compatible = "ti,omap3430-timer", },
 170         { .compatible = "ti,omap4430-timer", },
 171         { .compatible = "ti,omap5430-timer", },
 172         { .compatible = "ti,dm814-timer", },
 173         { .compatible = "ti,dm816-timer", },
 174         { .compatible = "ti,am335x-timer", },
 175         { .compatible = "ti,am335x-timer-1ms", },
 176         { }
 177 };
 178
 179 static int omap_timer_add_disabled_property(struct device_node *np)
 180 {
 181         struct property *prop;
 182
 183         prop = kzalloc(sizeof(*prop), GFP_KERNEL);
 184         if (!prop)
 185                 return -ENOMEM;
 186
 187         prop->name = "status";
 188         prop->value = "disabled";
 189         prop->length = strlen(prop->value);
 190
 191         return of_add_property(np, prop);
 192 }
 193
 194 static int omap_timer_update_dt(struct device_node *np)
 195 {
 196         int error = 0;
 197
 198         if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
 199                 error = omap_timer_add_disabled_property(np);
 200                 if (error)
 201                         return error;
 202         }
 203
 204         /* No parent interconnect target module configured? */
 205         if (of_get_property(np, "ti,hwmods", NULL))
 206                 return error;
 207
 208         /* Tag parent interconnect target module disabled */
 209         error = omap_timer_add_disabled_property(np->parent);
 210         if (error)
 211                 return error;
 212
 213         return 0;
 214 }
 215
 216 /**
 217  * omap_get_timer_dt - get a timer using device-tree
 218  * @match       - device-tree match structure for matching a device type
 219  * @property    - optional timer property to match
 220  *
 221  * Helper function to get a timer during early boot using device-tree for use
 222  * as kernel system timer. Optionally, the property argument can be used to
 223  * select a timer with a specific property. Once a timer is found then mark
 224  * the timer node in device-tree as disabled, to prevent the kernel from
 225  * registering this timer as a platform device and so no one else can use it.
 226  */
 227 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
 228                                                      const char *property)
 229 {
 230         struct device_node *np;
 231         int error;
 232
 233         for_each_matching_node(np, match) {
 234                 if (!of_device_is_available(np))
 235                         continue;
 236
 237                 if (property && !of_get_property(np, property, NULL))
 238                         continue;
 239
 240                 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
 241                                   of_get_property(np, "ti,timer-dsp", NULL) ||
 242                                   of_get_property(np, "ti,timer-pwm", NULL) ||
 243                                   of_get_property(np, "ti,timer-secure", NULL)))
 244                         continue;
 245
 246                 error = omap_timer_update_dt(np);
 247                 WARN(error, "%s: Could not update dt: %i\n", __func__, error);
 248
 249                 return np;
 250         }
 251
 252         return NULL;
 253 }
 254
 255 /**
 256  * omap_dmtimer_init - initialisation function when device tree is used
 257  *
 258  * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
 259  * cannot be used by the kernel as they are reserved. Therefore, to prevent the
 260  * kernel registering these devices remove them dynamically from the device
 261  * tree on boot.
 262  */
 263 static void __init omap_dmtimer_init(void)
 264 {
 265         struct device_node *np;
 266
 267         if (!cpu_is_omap34xx() && !soc_is_dra7xx())
 268                 return;
 269
 270         /* If we are a secure device, remove any secure timer nodes */
 271         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
 272                 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
 273                 of_node_put(np);
 274         }
 275 }
 276
 277 /**
 278  * omap_dm_timer_get_errata - get errata flags for a timer
 279  *
 280  * Get the timer errata flags that are specific to the OMAP device being used.
 281  */
 282 static u32 __init omap_dm_timer_get_errata(void)
 283 {
 284         if (cpu_is_omap24xx())
 285                 return 0;
 286
 287         return OMAP_TIMER_ERRATA_I103_I767;
 288 }
 289
 290 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 291                                          const char *fck_source,
 292                                          const char *property,
 293                                          const char **timer_name,
 294                                          int posted)
 295 {
 296         const char *oh_name = NULL;
 297         struct device_node *np;
 298         struct omap_hwmod *oh;
 299         struct clk *src;
 300         int r = 0;
 301
 302         np = omap_get_timer_dt(omap_timer_match, property);
 303         if (!np)
 304                 return -ENODEV;
 305
 306         of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 307         if (!oh_name) {
 308                 of_property_read_string_index(np->parent, "ti,hwmods", 0,
 309                                               &oh_name);
 310                 if (!oh_name)
 311                         return -ENODEV;
 312         }
 313
 314         timer->irq = irq_of_parse_and_map(np, 0);
 315         if (!timer->irq)
 316                 return -ENXIO;
 317
 318         timer->io_base = of_iomap(np, 0);
 319
 320         timer->fclk = of_clk_get_by_name(np, "fck");
 321
 322         of_node_put(np);
 323
 324         oh = omap_hwmod_lookup(oh_name);
 325         if (!oh)
 326                 return -ENODEV;
 327
 328         *timer_name = oh->name;
 329
 330         if (!timer->io_base)
 331                 return -ENXIO;
 332
 333         omap_hwmod_setup_one(oh_name);
 334
 335         /* After the dmtimer is using hwmod these clocks won't be needed */
 336         if (IS_ERR_OR_NULL(timer->fclk))
 337                 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
 338         if (IS_ERR(timer->fclk))
 339                 return PTR_ERR(timer->fclk);
 340
 341         src = clk_get(NULL, fck_source);
 342         if (IS_ERR(src))
 343                 return PTR_ERR(src);
 344
 345         WARN(clk_set_parent(timer->fclk, src) < 0,
 346              "Cannot set timer parent clock, no PLL clock driver?");
 347
 348         clk_put(src);
 349
 350         omap_hwmod_enable(oh);
 351         __omap_dm_timer_init_regs(timer);
 352
 353         if (posted)
 354                 __omap_dm_timer_enable_posted(timer);
 355
 356         /* Check that the intended posted configuration matches the actual */
 357         if (posted != timer->posted)
 358                 return -EINVAL;
 359
 360         timer->rate = clk_get_rate(timer->fclk);
 361         timer->reserved = 1;
 362
 363         return r;
 364 }
 365
 366 #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
 367 void tick_broadcast(const struct cpumask *mask)
 368 {
 369 }
 370 #endif
 371
 372 static void __init dmtimer_clkevt_init_common(struct dmtimer_clockevent *clkevt,
 373                                               int gptimer_id,
 374                                               const char *fck_source,
 375                                               unsigned int features,
 376                                               const struct cpumask *cpumask,
 377                                               const char *property,
 378                                               int rating, const char *name)
 379 {
 380         struct omap_dm_timer *timer = &clkevt->timer;
 381         int res;
 382
 383         timer->id = gptimer_id;
 384         timer->errata = omap_dm_timer_get_errata();
 385         clkevt->dev.features = features;
 386         clkevt->dev.rating = rating;
 387         clkevt->dev.set_next_event = omap2_gp_timer_set_next_event;
 388         clkevt->dev.set_state_shutdown = omap2_gp_timer_shutdown;
 389         clkevt->dev.set_state_periodic = omap2_gp_timer_set_periodic;
 390         clkevt->dev.set_state_oneshot = omap2_gp_timer_shutdown;
 391         clkevt->dev.tick_resume = omap2_gp_timer_shutdown;
 392
 393         /*
 394          * For clock-event timers we never read the timer counter and
 395          * so we are not impacted by errata i103 and i767. Therefore,
 396          * we can safely ignore this errata for clock-event timers.
 397          */
 398         __omap_dm_timer_override_errata(timer, OMAP_TIMER_ERRATA_I103_I767);
 399
 400         res = omap_dm_timer_init_one(timer, fck_source, property,
 401                                      &clkevt->dev.name, OMAP_TIMER_POSTED);
 402         BUG_ON(res);
 403
 404         clkevt->dev.cpumask = cpumask;
 405         clkevt->dev.irq = omap_dm_timer_get_irq(timer);
 406
 407         if (request_irq(clkevt->dev.irq, omap2_gp_timer_interrupt,
 408                         IRQF_TIMER | IRQF_IRQPOLL, name, clkevt))
 409                 pr_err("Failed to request irq %d (gp_timer)\n", clkevt->dev.irq);
 410
 411         __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW);
 412
 413         if (soc_is_am33xx() || soc_is_am43xx()) {
 414                 clkevt->dev.suspend = omap_clkevt_idle;
 415                 clkevt->dev.resume = omap_clkevt_unidle;
 416
 417                 clockevent_gpt_hwmod =
 418                         omap_hwmod_lookup(clkevt->dev.name);
 419         }
 420
 421         pr_info("OMAP clockevent source: %s at %lu Hz\n", clkevt->dev.name,
 422                 timer->rate);
 423 }
 424
 425 static DEFINE_PER_CPU(struct dmtimer_clockevent, dmtimer_percpu_timer);
 426
 427 static int omap_gptimer_starting_cpu(unsigned int cpu)
 428 {
 429         struct dmtimer_clockevent *clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
 430         struct clock_event_device *dev = &clkevt->dev;
 431         struct omap_dm_timer *timer = &clkevt->timer;
 432
 433         clockevents_config_and_register(dev, timer->rate, 3, ULONG_MAX);
 434         irq_force_affinity(dev->irq, cpumask_of(cpu));
 435
 436         return 0;
 437 }
 438
 439 static int __init dmtimer_percpu_quirk_init(void)
 440 {
 441         struct dmtimer_clockevent *clkevt;
 442         struct clock_event_device *dev;
 443         struct device_node *arm_timer;
 444         struct omap_dm_timer *timer;
 445         int cpu = 0;
 446
 447         arm_timer = of_find_compatible_node(NULL, NULL, "arm,armv7-timer");
 448         if (of_device_is_available(arm_timer)) {
 449                 pr_warn_once("ARM architected timer wrap issue i940 detected\n");
 450                 return 0;
 451         }
 452
 453         for_each_possible_cpu(cpu) {
 454                 clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
 455                 dev = &clkevt->dev;
 456                 timer = &clkevt->timer;
 457
 458                 dmtimer_clkevt_init_common(clkevt, 0, "timer_sys_ck",
 459                                            CLOCK_EVT_FEAT_ONESHOT,
 460                                            cpumask_of(cpu),
 461                                            "assigned-clock-parents",
 462                                            500, "percpu timer");
 463         }
 464
 465         cpuhp_setup_state(CPUHP_AP_OMAP_DM_TIMER_STARTING,
 466                           "clockevents/omap/gptimer:starting",
 467                           omap_gptimer_starting_cpu, NULL);
 468
 469         return 0;
 470 }
 471
 472 /* Clocksource code */
 473 static struct omap_dm_timer clksrc;
 474 static bool use_gptimer_clksrc __initdata;
 475
 476 /*
 477  * clocksource
 478  */
 479 static u64 clocksource_read_cycles(struct clocksource *cs)
 480 {
 481         return (u64)__omap_dm_timer_read_counter(&clksrc,
 482                                                      OMAP_TIMER_NONPOSTED);
 483 }
 484
 485 static struct clocksource clocksource_gpt = {
 486         .rating         = 300,
 487         .read           = clocksource_read_cycles,
 488         .mask           = CLOCKSOURCE_MASK(32),
 489         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 490 };
 491
 492 static u64 notrace dmtimer_read_sched_clock(void)
 493 {
 494         if (clksrc.reserved)
 495                 return __omap_dm_timer_read_counter(&clksrc,
 496                                                     OMAP_TIMER_NONPOSTED);
 497
 498         return 0;
 499 }
 500
 501 static const struct of_device_id omap_counter_match[] __initconst = {
 502         { .compatible = "ti,omap-counter32k", },
 503         { }
 504 };
 505
 506 /* Setup free-running counter for clocksource */
 507 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
 508 {
 509         int ret;
 510         struct device_node *np = NULL;
 511         struct omap_hwmod *oh;
 512         const char *oh_name = "counter_32k";
 513
 514         /*
 515          * See if the 32kHz counter is supported.
 516          */
 517         np = omap_get_timer_dt(omap_counter_match, NULL);
 518         if (!np)
 519                 return -ENODEV;
 520
 521         of_property_read_string_index(np->parent, "ti,hwmods", 0, &oh_name);
 522         if (!oh_name) {
 523                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 524                 if (!oh_name)
 525                         return -ENODEV;
 526         }
 527
 528         /*
 529          * First check hwmod data is available for sync32k counter
 530          */
 531         oh = omap_hwmod_lookup(oh_name);
 532         if (!oh || oh->slaves_cnt == 0)
 533                 return -ENODEV;
 534
 535         omap_hwmod_setup_one(oh_name);
 536
 537         ret = omap_hwmod_enable(oh);
 538         if (ret) {
 539                 pr_warn("%s: failed to enable counter_32k module (%d)\n",
 540                                                         __func__, ret);
 541                 return ret;
 542         }
 543
 544         return ret;
 545 }
 546
 547 static unsigned int omap2_gptimer_clksrc_load;
 548
 549 static void omap2_gptimer_clksrc_suspend(struct clocksource *unused)
 550 {
 551         omap2_gptimer_clksrc_load =
 552                 __omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED);
 553
 554         omap_hwmod_idle(clocksource_gpt_hwmod);
 555 }
 556
 557 static void omap2_gptimer_clksrc_resume(struct clocksource *unused)
 558 {
 559         omap_hwmod_enable(clocksource_gpt_hwmod);
 560
 561         __omap_dm_timer_load_start(&clksrc,
 562                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
 563                                    omap2_gptimer_clksrc_load,
 564                                    OMAP_TIMER_NONPOSTED);
 565 }
 566
 567 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 568                                                   const char *fck_source,
 569                                                   const char *property)
 570 {
 571         int res;
 572
 573         clksrc.id = gptimer_id;
 574         clksrc.errata = omap_dm_timer_get_errata();
 575
 576         res = omap_dm_timer_init_one(&clksrc, fck_source, property,
 577                                      &clocksource_gpt.name,
 578                                      OMAP_TIMER_NONPOSTED);
 579
 580         if (soc_is_am43xx()) {
 581                 clocksource_gpt.suspend = omap2_gptimer_clksrc_suspend;
 582                 clocksource_gpt.resume = omap2_gptimer_clksrc_resume;
 583
 584                 clocksource_gpt_hwmod =
 585                         omap_hwmod_lookup(clocksource_gpt.name);
 586         }
 587
 588         BUG_ON(res);
 589
 590         __omap_dm_timer_load_start(&clksrc,
 591                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
 592                                    OMAP_TIMER_NONPOSTED);
 593         sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
 594
 595         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 596                 pr_err("Could not register clocksource %s\n",
 597                         clocksource_gpt.name);
 598         else
 599                 pr_info("OMAP clocksource: %s at %lu Hz\n",
 600                         clocksource_gpt.name, clksrc.rate);
 601 }
 602
 603 static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
 604                 const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
 605                 const char *clksrc_prop, bool gptimer)
 606 {
 607         omap_clk_init();
 608         omap_dmtimer_init();
 609         dmtimer_clkevt_init_common(&clockevent, clkev_nr, clkev_src,
 610                                    CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 611                                    cpu_possible_mask, clkev_prop, 300, "clockevent");
 612         clockevents_config_and_register(&clockevent.dev, clockevent.timer.rate,
 613                                         3, /* Timer internal resynch latency */
 614                                         0xffffffff);
 615
 616         if (soc_is_dra7xx())
 617                 dmtimer_percpu_quirk_init();
 618
 619         /* Enable the use of clocksource="gp_timer" kernel parameter */
 620         if (use_gptimer_clksrc || gptimer)
 621                 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
 622                                                 clksrc_prop);
 623         else
 624                 omap2_sync32k_clocksource_init();
 625 }
 626
 627 void __init omap_init_time(void)
 628 {
 629         __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
 630                         2, "timer_sys_ck", NULL, false);
 631
 632         timer_probe();
 633 }
 634
 635 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
 636 void __init omap3_secure_sync32k_timer_init(void)
 637 {
 638         __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
 639                         2, "timer_sys_ck", NULL, false);
 640
 641         timer_probe();
 642 }
 643 #endif /* CONFIG_ARCH_OMAP3 */
 644
 645 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
 646         defined(CONFIG_SOC_AM43XX) || defined(CONFIG_SOC_DRA7XX)
 647 void __init omap3_gptimer_timer_init(void)
 648 {
 649         __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
 650                         1, "timer_sys_ck", "ti,timer-alwon", true);
 651         if (of_have_populated_dt())
 652                 timer_probe();
 653 }
 654 #endif
 655
 656 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) ||          \
 657         defined(CONFIG_SOC_DRA7XX)
 658 static void __init omap4_sync32k_timer_init(void)
 659 {
 660         __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
 661                         2, "sys_clkin_ck", NULL, false);
 662 }
 663
 664 void __init omap4_local_timer_init(void)
 665 {
 666         omap4_sync32k_timer_init();
 667         timer_probe();
 668 }
 669 #endif
 670
 671 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
 672
 673 /*
 674  * The realtime counter also called master counter, is a free-running
 675  * counter, which is related to real time. It produces the count used
 676  * by the CPU local timer peripherals in the MPU cluster. The timer counts
 677  * at a rate of 6.144 MHz. Because the device operates on different clocks
 678  * in different power modes, the master counter shifts operation between
 679  * clocks, adjusting the increment per clock in hardware accordingly to
 680  * maintain a constant count rate.
 681  */
 682 static void __init realtime_counter_init(void)
 683 {
 684 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 685         void __iomem *base;
 686         static struct clk *sys_clk;
 687         unsigned long rate;
 688         unsigned int reg;
 689         unsigned long long num, den;
 690
 691         base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
 692         if (!base) {
 693                 pr_err("%s: ioremap failed\n", __func__);
 694                 return;
 695         }
 696         sys_clk = clk_get(NULL, "sys_clkin");
 697         if (IS_ERR(sys_clk)) {
 698                 pr_err("%s: failed to get system clock handle\n", __func__);
 699                 iounmap(base);
 700                 return;
 701         }
 702
 703         rate = clk_get_rate(sys_clk);
 704
 705         if (soc_is_dra7xx()) {
 706                 /*
 707                  * Errata i856 says the 32.768KHz crystal does not start at
 708                  * power on, so the CPU falls back to an emulated 32KHz clock
 709                  * based on sysclk / 610 instead. This causes the master counter
 710                  * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
 711                  * (OR sysclk * 75 / 244)
 712                  *
 713                  * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
 714                  * Of course any board built without a populated 32.768KHz
 715                  * crystal would also need this fix even if the CPU is fixed
 716                  * later.
 717                  *
 718                  * Either case can be detected by using the two speedselect bits
 719                  * If they are not 0, then the 32.768KHz clock driving the
 720                  * coarse counter that corrects the fine counter every time it
 721                  * ticks is actually rate/610 rather than 32.768KHz and we
 722                  * should compensate to avoid the 570ppm (at 20MHz, much worse
 723                  * at other rates) too fast system time.
 724                  */
 725                 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
 726                 if (reg & DRA7_SPEEDSELECT_MASK) {
 727                         num = 75;
 728                         den = 244;
 729                         goto sysclk1_based;
 730                 }
 731         }
 732
 733         /* Numerator/denumerator values refer TRM Realtime Counter section */
 734         switch (rate) {
 735         case 12000000:
 736                 num = 64;
 737                 den = 125;
 738                 break;
 739         case 13000000:
 740                 num = 768;
 741                 den = 1625;
 742                 break;
 743         case 19200000:
 744                 num = 8;
 745                 den = 25;
 746                 break;
 747         case 20000000:
 748                 num = 192;
 749                 den = 625;
 750                 break;
 751         case 26000000:
 752                 num = 384;
 753                 den = 1625;
 754                 break;
 755         case 27000000:
 756                 num = 256;
 757                 den = 1125;
 758                 break;
 759         case 38400000:
 760         default:
 761                 /* Program it for 38.4 MHz */
 762                 num = 4;
 763                 den = 25;
 764                 break;
 765         }
 766
 767 sysclk1_based:
 768         /* Program numerator and denumerator registers */
 769         reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
 770                         NUMERATOR_DENUMERATOR_MASK;
 771         reg |= num;
 772         writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
 773
 774         reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
 775                         NUMERATOR_DENUMERATOR_MASK;
 776         reg |= den;
 777         writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 778
 779         arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
 780         set_cntfreq();
 781
 782         iounmap(base);
 783 #endif
 784 }
 785
 786 void __init omap5_realtime_timer_init(void)
 787 {
 788         omap4_sync32k_timer_init();
 789         realtime_counter_init();
 790
 791         timer_probe();
 792 }
 793 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
 794
 795 /**
 796  * omap2_override_clocksource - clocksource override with user configuration
 797  *
 798  * Allows user to override default clocksource, using kernel parameter
 799  *   clocksource="gp_timer"     (For all OMAP2PLUS architectures)
 800  *
 801  * Note that, here we are using same standard kernel parameter "clocksource=",
 802  * and not introducing any OMAP specific interface.
 803  */
 804 static int __init omap2_override_clocksource(char *str)
 805 {
 806         if (!str)
 807                 return 0;
 808         /*
 809          * For OMAP architecture, we only have two options
 810          *    - sync_32k (default)
 811          *    - gp_timer (sys_clk based)
 812          */
 813         if (!strcmp(str, "gp_timer"))
 814                 use_gptimer_clksrc = true;
 815
 816         return 0;
 817 }
 818 early_param("clocksource", omap2_override_clocksource);