arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39 #include <linux/of.h>
  40 #include <linux/of_address.h>
  41 #include <linux/of_irq.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/platform_data/dmtimer-omap.h>
  44 #include <linux/sched_clock.h>
  45 #include <linux/cpu.h>
  46
  47 #include <asm/mach/time.h>
  48
  49 #include "omap_hwmod.h"
  50 #include "omap_device.h"
  51 #include <plat/counter-32k.h>
  52 #include <clocksource/timer-ti-dm.h>
  53
  54 #include "soc.h"
  55 #include "common.h"
  56 #include "control.h"
  57 #include "powerdomain.h"
  58 #include "omap-secure.h"
  59
  60 #define REALTIME_COUNTER_BASE                           0x48243200
  61 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
  62 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
  63 #define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
  64
  65 /* Clockevent code */
  66
  67 /* Clockevent hwmod for am335x and am437x suspend */
  68 static struct omap_hwmod *clockevent_gpt_hwmod;
  69
  70 /* Clockesource hwmod for am437x suspend */
  71 static struct omap_hwmod *clocksource_gpt_hwmod;
  72
  73 struct dmtimer_clockevent {
  74         struct clock_event_device dev;
  75         struct omap_dm_timer timer;
  76 };
  77
  78 static struct dmtimer_clockevent clockevent;
  79
  80 static struct omap_dm_timer *to_dmtimer(struct clock_event_device *clockevent)
  81 {
  82         struct dmtimer_clockevent *clkevt =
  83                 container_of(clockevent, struct dmtimer_clockevent, dev);
  84         struct omap_dm_timer *timer = &clkevt->timer;
  85
  86         return timer;
  87 }
  88
  89 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
  90 static unsigned long arch_timer_freq;
  91
  92 void set_cntfreq(void)
  93 {
  94         omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
  95 }
  96 #endif
  97
  98 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  99 {
 100         struct dmtimer_clockevent *clkevt = dev_id;
 101         struct clock_event_device *evt = &clkevt->dev;
 102         struct omap_dm_timer *timer = &clkevt->timer;
 103
 104         __omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW);
 105         evt->event_handler(evt);
 106         return IRQ_HANDLED;
 107 }
 108
 109 static int omap2_gp_timer_set_next_event(unsigned long cycles,
 110                                          struct clock_event_device *evt)
 111 {
 112         struct omap_dm_timer *timer = to_dmtimer(evt);
 113
 114         __omap_dm_timer_load_start(timer, OMAP_TIMER_CTRL_ST,
 115                                    0xffffffff - cycles, OMAP_TIMER_POSTED);
 116
 117         return 0;
 118 }
 119
 120 static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
 121 {
 122         struct omap_dm_timer *timer = to_dmtimer(evt);
 123
 124         __omap_dm_timer_stop(timer, OMAP_TIMER_POSTED, timer->rate);
 125
 126         return 0;
 127 }
 128
 129 static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
 130 {
 131         struct omap_dm_timer *timer = to_dmtimer(evt);
 132         u32 period;
 133
 134         __omap_dm_timer_stop(timer, OMAP_TIMER_POSTED, timer->rate);
 135
 136         period = timer->rate / HZ;
 137         period -= 1;
 138         /* Looks like we need to first set the load value separately */
 139         __omap_dm_timer_write(timer, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
 140                               OMAP_TIMER_POSTED);
 141         __omap_dm_timer_load_start(timer,
 142                                    OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 143                                    0xffffffff - period, OMAP_TIMER_POSTED);
 144         return 0;
 145 }
 146
 147 static void omap_clkevt_idle(struct clock_event_device *unused)
 148 {
 149         if (!clockevent_gpt_hwmod)
 150                 return;
 151
 152         omap_hwmod_idle(clockevent_gpt_hwmod);
 153 }
 154
 155 static void omap_clkevt_unidle(struct clock_event_device *evt)
 156 {
 157         struct omap_dm_timer *timer = to_dmtimer(evt);
 158
 159         if (!clockevent_gpt_hwmod)
 160                 return;
 161
 162         omap_hwmod_enable(clockevent_gpt_hwmod);
 163         __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW);
 164 }
 165
 166 static const struct of_device_id omap_timer_match[] __initconst = {
 167         { .compatible = "ti,omap2420-timer", },
 168         { .compatible = "ti,omap3430-timer", },
 169         { .compatible = "ti,omap4430-timer", },
 170         { .compatible = "ti,omap5430-timer", },
 171         { .compatible = "ti,dm814-timer", },
 172         { .compatible = "ti,dm816-timer", },
 173         { .compatible = "ti,am335x-timer", },
 174         { .compatible = "ti,am335x-timer-1ms", },
 175         { }
 176 };
 177
 178 static int omap_timer_add_disabled_property(struct device_node *np)
 179 {
 180         struct property *prop;
 181
 182         prop = kzalloc(sizeof(*prop), GFP_KERNEL);
 183         if (!prop)
 184                 return -ENOMEM;
 185
 186         prop->name = "status";
 187         prop->value = "disabled";
 188         prop->length = strlen(prop->value);
 189
 190         return of_add_property(np, prop);
 191 }
 192
 193 static int omap_timer_update_dt(struct device_node *np)
 194 {
 195         int error = 0;
 196
 197         if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
 198                 error = omap_timer_add_disabled_property(np);
 199                 if (error)
 200                         return error;
 201         }
 202
 203         /* No parent interconnect target module configured? */
 204         if (of_get_property(np, "ti,hwmods", NULL))
 205                 return error;
 206
 207         /* Tag parent interconnect target module disabled */
 208         error = omap_timer_add_disabled_property(np->parent);
 209         if (error)
 210                 return error;
 211
 212         return 0;
 213 }
 214
 215 /**
 216  * omap_get_timer_dt - get a timer using device-tree
 217  * @match       - device-tree match structure for matching a device type
 218  * @property    - optional timer property to match
 219  *
 220  * Helper function to get a timer during early boot using device-tree for use
 221  * as kernel system timer. Optionally, the property argument can be used to
 222  * select a timer with a specific property. Once a timer is found then mark
 223  * the timer node in device-tree as disabled, to prevent the kernel from
 224  * registering this timer as a platform device and so no one else can use it.
 225  */
 226 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
 227                                                      const char *property)
 228 {
 229         struct device_node *np;
 230         int error;
 231
 232         for_each_matching_node(np, match) {
 233                 if (!of_device_is_available(np))
 234                         continue;
 235
 236                 if (property && !of_get_property(np, property, NULL))
 237                         continue;
 238
 239                 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
 240                                   of_get_property(np, "ti,timer-dsp", NULL) ||
 241                                   of_get_property(np, "ti,timer-pwm", NULL) ||
 242                                   of_get_property(np, "ti,timer-secure", NULL)))
 243                         continue;
 244
 245                 error = omap_timer_update_dt(np);
 246                 WARN(error, "%s: Could not update dt: %i\n", __func__, error);
 247
 248                 return np;
 249         }
 250
 251         return NULL;
 252 }
 253
 254 /**
 255  * omap_dmtimer_init - initialisation function when device tree is used
 256  *
 257  * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
 258  * cannot be used by the kernel as they are reserved. Therefore, to prevent the
 259  * kernel registering these devices remove them dynamically from the device
 260  * tree on boot.
 261  */
 262 static void __init omap_dmtimer_init(void)
 263 {
 264         struct device_node *np;
 265
 266         if (!cpu_is_omap34xx() && !soc_is_dra7xx())
 267                 return;
 268
 269         /* If we are a secure device, remove any secure timer nodes */
 270         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
 271                 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
 272                 of_node_put(np);
 273         }
 274 }
 275
 276 /**
 277  * omap_dm_timer_get_errata - get errata flags for a timer
 278  *
 279  * Get the timer errata flags that are specific to the OMAP device being used.
 280  */
 281 static u32 __init omap_dm_timer_get_errata(void)
 282 {
 283         if (cpu_is_omap24xx())
 284                 return 0;
 285
 286         return OMAP_TIMER_ERRATA_I103_I767;
 287 }
 288
 289 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 290                                          const char *fck_source,
 291                                          const char *property,
 292                                          const char **timer_name,
 293                                          int posted)
 294 {
 295         const char *oh_name = NULL;
 296         struct device_node *np;
 297         struct omap_hwmod *oh;
 298         struct clk *src;
 299         int r = 0;
 300
 301         np = omap_get_timer_dt(omap_timer_match, property);
 302         if (!np)
 303                 return -ENODEV;
 304
 305         of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 306         if (!oh_name) {
 307                 of_property_read_string_index(np->parent, "ti,hwmods", 0,
 308                                               &oh_name);
 309                 if (!oh_name)
 310                         return -ENODEV;
 311         }
 312
 313         timer->irq = irq_of_parse_and_map(np, 0);
 314         if (!timer->irq)
 315                 return -ENXIO;
 316
 317         timer->io_base = of_iomap(np, 0);
 318
 319         timer->fclk = of_clk_get_by_name(np, "fck");
 320
 321         of_node_put(np);
 322
 323         oh = omap_hwmod_lookup(oh_name);
 324         if (!oh)
 325                 return -ENODEV;
 326
 327         *timer_name = oh->name;
 328
 329         if (!timer->io_base)
 330                 return -ENXIO;
 331
 332         omap_hwmod_setup_one(oh_name);
 333
 334         /* After the dmtimer is using hwmod these clocks won't be needed */
 335         if (IS_ERR_OR_NULL(timer->fclk))
 336                 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
 337         if (IS_ERR(timer->fclk))
 338                 return PTR_ERR(timer->fclk);
 339
 340         src = clk_get(NULL, fck_source);
 341         if (IS_ERR(src))
 342                 return PTR_ERR(src);
 343
 344         WARN(clk_set_parent(timer->fclk, src) < 0,
 345              "Cannot set timer parent clock, no PLL clock driver?");
 346
 347         clk_put(src);
 348
 349         omap_hwmod_enable(oh);
 350         __omap_dm_timer_init_regs(timer);
 351
 352         if (posted)
 353                 __omap_dm_timer_enable_posted(timer);
 354
 355         /* Check that the intended posted configuration matches the actual */
 356         if (posted != timer->posted)
 357                 return -EINVAL;
 358
 359         timer->rate = clk_get_rate(timer->fclk);
 360         timer->reserved = 1;
 361
 362         return r;
 363 }
 364
 365 #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
 366 void tick_broadcast(const struct cpumask *mask)
 367 {
 368 }
 369 #endif
 370
 371 static void __init dmtimer_clkevt_init_common(struct dmtimer_clockevent *clkevt,
 372                                               int gptimer_id,
 373                                               const char *fck_source,
 374                                               unsigned int features,
 375                                               const struct cpumask *cpumask,
 376                                               const char *property,
 377                                               int rating, const char *name)
 378 {
 379         struct omap_dm_timer *timer = &clkevt->timer;
 380         int res;
 381
 382         timer->id = gptimer_id;
 383         timer->errata = omap_dm_timer_get_errata();
 384         clkevt->dev.features = features;
 385         clkevt->dev.rating = rating;
 386         clkevt->dev.set_next_event = omap2_gp_timer_set_next_event;
 387         clkevt->dev.set_state_shutdown = omap2_gp_timer_shutdown;
 388         clkevt->dev.set_state_periodic = omap2_gp_timer_set_periodic;
 389         clkevt->dev.set_state_oneshot = omap2_gp_timer_shutdown;
 390         clkevt->dev.tick_resume = omap2_gp_timer_shutdown;
 391
 392         /*
 393          * For clock-event timers we never read the timer counter and
 394          * so we are not impacted by errata i103 and i767. Therefore,
 395          * we can safely ignore this errata for clock-event timers.
 396          */
 397         __omap_dm_timer_override_errata(timer, OMAP_TIMER_ERRATA_I103_I767);
 398
 399         res = omap_dm_timer_init_one(timer, fck_source, property,
 400                                      &clkevt->dev.name, OMAP_TIMER_POSTED);
 401         BUG_ON(res);
 402
 403         clkevt->dev.cpumask = cpumask;
 404         clkevt->dev.irq = omap_dm_timer_get_irq(timer);
 405
 406         if (request_irq(clkevt->dev.irq, omap2_gp_timer_interrupt,
 407                         IRQF_TIMER | IRQF_IRQPOLL, name, clkevt))
 408                 pr_err("Failed to request irq %d (gp_timer)\n", clkevt->dev.irq);
 409
 410         __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW);
 411
 412         if (soc_is_am33xx() || soc_is_am43xx()) {
 413                 clkevt->dev.suspend = omap_clkevt_idle;
 414                 clkevt->dev.resume = omap_clkevt_unidle;
 415
 416                 clockevent_gpt_hwmod =
 417                         omap_hwmod_lookup(clkevt->dev.name);
 418         }
 419
 420         pr_info("OMAP clockevent source: %s at %lu Hz\n", clkevt->dev.name,
 421                 timer->rate);
 422 }
 423
 424 static DEFINE_PER_CPU(struct dmtimer_clockevent, dmtimer_percpu_timer);
 425
 426 static int omap_gptimer_starting_cpu(unsigned int cpu)
 427 {
 428         struct dmtimer_clockevent *clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
 429         struct clock_event_device *dev = &clkevt->dev;
 430         struct omap_dm_timer *timer = &clkevt->timer;
 431
 432         clockevents_config_and_register(dev, timer->rate, 3, ULONG_MAX);
 433         irq_force_affinity(dev->irq, cpumask_of(cpu));
 434
 435         return 0;
 436 }
 437
 438 static int __init dmtimer_percpu_quirk_init(void)
 439 {
 440         struct dmtimer_clockevent *clkevt;
 441         struct clock_event_device *dev;
 442         struct device_node *arm_timer;
 443         struct omap_dm_timer *timer;
 444         int cpu = 0;
 445
 446         arm_timer = of_find_compatible_node(NULL, NULL, "arm,armv7-timer");
 447         if (of_device_is_available(arm_timer)) {
 448                 pr_warn_once("ARM architected timer wrap issue i940 detected\n");
 449                 return 0;
 450         }
 451
 452         for_each_possible_cpu(cpu) {
 453                 clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
 454                 dev = &clkevt->dev;
 455                 timer = &clkevt->timer;
 456
 457                 dmtimer_clkevt_init_common(clkevt, 0, "timer_sys_ck",
 458                                            CLOCK_EVT_FEAT_ONESHOT,
 459                                            cpumask_of(cpu),
 460                                            "assigned-clock-parents",
 461                                            500, "percpu timer");
 462         }
 463
 464         cpuhp_setup_state(CPUHP_AP_OMAP_DM_TIMER_STARTING,
 465                           "clockevents/omap/gptimer:starting",
 466                           omap_gptimer_starting_cpu, NULL);
 467
 468         return 0;
 469 }
 470
 471 /* Clocksource code */
 472 static struct omap_dm_timer clksrc;
 473 static bool use_gptimer_clksrc __initdata;
 474
 475 /*
 476  * clocksource
 477  */
 478 static u64 clocksource_read_cycles(struct clocksource *cs)
 479 {
 480         return (u64)__omap_dm_timer_read_counter(&clksrc,
 481                                                      OMAP_TIMER_NONPOSTED);
 482 }
 483
 484 static struct clocksource clocksource_gpt = {
 485         .rating         = 300,
 486         .read           = clocksource_read_cycles,
 487         .mask           = CLOCKSOURCE_MASK(32),
 488         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 489 };
 490
 491 static u64 notrace dmtimer_read_sched_clock(void)
 492 {
 493         if (clksrc.reserved)
 494                 return __omap_dm_timer_read_counter(&clksrc,
 495                                                     OMAP_TIMER_NONPOSTED);
 496
 497         return 0;
 498 }
 499
 500 static const struct of_device_id omap_counter_match[] __initconst = {
 501         { .compatible = "ti,omap-counter32k", },
 502         { }
 503 };
 504
 505 /* Setup free-running counter for clocksource */
 506 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
 507 {
 508         int ret;
 509         struct device_node *np = NULL;
 510         struct omap_hwmod *oh;
 511         const char *oh_name = "counter_32k";
 512
 513         /*
 514          * See if the 32kHz counter is supported.
 515          */
 516         np = omap_get_timer_dt(omap_counter_match, NULL);
 517         if (!np)
 518                 return -ENODEV;
 519
 520         of_property_read_string_index(np->parent, "ti,hwmods", 0, &oh_name);
 521         if (!oh_name) {
 522                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 523                 if (!oh_name)
 524                         return -ENODEV;
 525         }
 526
 527         /*
 528          * First check hwmod data is available for sync32k counter
 529          */
 530         oh = omap_hwmod_lookup(oh_name);
 531         if (!oh || oh->slaves_cnt == 0)
 532                 return -ENODEV;
 533
 534         omap_hwmod_setup_one(oh_name);
 535
 536         ret = omap_hwmod_enable(oh);
 537         if (ret) {
 538                 pr_warn("%s: failed to enable counter_32k module (%d)\n",
 539                                                         __func__, ret);
 540                 return ret;
 541         }
 542
 543         return ret;
 544 }
 545
 546 static unsigned int omap2_gptimer_clksrc_load;
 547
 548 static void omap2_gptimer_clksrc_suspend(struct clocksource *unused)
 549 {
 550         omap2_gptimer_clksrc_load =
 551                 __omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED);
 552
 553         omap_hwmod_idle(clocksource_gpt_hwmod);
 554 }
 555
 556 static void omap2_gptimer_clksrc_resume(struct clocksource *unused)
 557 {
 558         omap_hwmod_enable(clocksource_gpt_hwmod);
 559
 560         __omap_dm_timer_load_start(&clksrc,
 561                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
 562                                    omap2_gptimer_clksrc_load,
 563                                    OMAP_TIMER_NONPOSTED);
 564 }
 565
 566 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 567                                                   const char *fck_source,
 568                                                   const char *property)
 569 {
 570         int res;
 571
 572         clksrc.id = gptimer_id;
 573         clksrc.errata = omap_dm_timer_get_errata();
 574
 575         res = omap_dm_timer_init_one(&clksrc, fck_source, property,
 576                                      &clocksource_gpt.name,
 577                                      OMAP_TIMER_NONPOSTED);
 578
 579         if (soc_is_am43xx()) {
 580                 clocksource_gpt.suspend = omap2_gptimer_clksrc_suspend;
 581                 clocksource_gpt.resume = omap2_gptimer_clksrc_resume;
 582
 583                 clocksource_gpt_hwmod =
 584                         omap_hwmod_lookup(clocksource_gpt.name);
 585         }
 586
 587         BUG_ON(res);
 588
 589         __omap_dm_timer_load_start(&clksrc,
 590                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
 591                                    OMAP_TIMER_NONPOSTED);
 592         sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
 593
 594         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 595                 pr_err("Could not register clocksource %s\n",
 596                         clocksource_gpt.name);
 597         else
 598                 pr_info("OMAP clocksource: %s at %lu Hz\n",
 599                         clocksource_gpt.name, clksrc.rate);
 600 }
 601
 602 static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
 603                 const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
 604                 const char *clksrc_prop, bool gptimer)
 605 {
 606         omap_clk_init();
 607         omap_dmtimer_init();
 608         dmtimer_clkevt_init_common(&clockevent, clkev_nr, clkev_src,
 609                                    CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 610                                    cpu_possible_mask, clkev_prop, 300, "clockevent");
 611         clockevents_config_and_register(&clockevent.dev, clockevent.timer.rate,
 612                                         3, /* Timer internal resynch latency */
 613                                         0xffffffff);
 614
 615         if (soc_is_dra7xx())
 616                 dmtimer_percpu_quirk_init();
 617
 618         /* Enable the use of clocksource="gp_timer" kernel parameter */
 619         if (use_gptimer_clksrc || gptimer)
 620                 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
 621                                                 clksrc_prop);
 622         else
 623                 omap2_sync32k_clocksource_init();
 624 }
 625
 626 void __init omap_init_time(void)
 627 {
 628         __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
 629                         2, "timer_sys_ck", NULL, false);
 630
 631         timer_probe();
 632 }
 633
 634 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
 635 void __init omap3_secure_sync32k_timer_init(void)
 636 {
 637         __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
 638                         2, "timer_sys_ck", NULL, false);
 639
 640         timer_probe();
 641 }
 642 #endif /* CONFIG_ARCH_OMAP3 */
 643
 644 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
 645         defined(CONFIG_SOC_AM43XX) || defined(CONFIG_SOC_DRA7XX)
 646 void __init omap3_gptimer_timer_init(void)
 647 {
 648         __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
 649                         1, "timer_sys_ck", "ti,timer-alwon", true);
 650         if (of_have_populated_dt())
 651                 timer_probe();
 652 }
 653 #endif
 654
 655 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) ||          \
 656         defined(CONFIG_SOC_DRA7XX)
 657 static void __init omap4_sync32k_timer_init(void)
 658 {
 659         __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
 660                         2, "sys_clkin_ck", NULL, false);
 661 }
 662
 663 void __init omap4_local_timer_init(void)
 664 {
 665         omap4_sync32k_timer_init();
 666         timer_probe();
 667 }
 668 #endif
 669
 670 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
 671
 672 /*
 673  * The realtime counter also called master counter, is a free-running
 674  * counter, which is related to real time. It produces the count used
 675  * by the CPU local timer peripherals in the MPU cluster. The timer counts
 676  * at a rate of 6.144 MHz. Because the device operates on different clocks
 677  * in different power modes, the master counter shifts operation between
 678  * clocks, adjusting the increment per clock in hardware accordingly to
 679  * maintain a constant count rate.
 680  */
 681 static void __init realtime_counter_init(void)
 682 {
 683 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 684         void __iomem *base;
 685         static struct clk *sys_clk;
 686         unsigned long rate;
 687         unsigned int reg;
 688         unsigned long long num, den;
 689
 690         base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
 691         if (!base) {
 692                 pr_err("%s: ioremap failed\n", __func__);
 693                 return;
 694         }
 695         sys_clk = clk_get(NULL, "sys_clkin");
 696         if (IS_ERR(sys_clk)) {
 697                 pr_err("%s: failed to get system clock handle\n", __func__);
 698                 iounmap(base);
 699                 return;
 700         }
 701
 702         rate = clk_get_rate(sys_clk);
 703         clk_put(sys_clk);
 704
 705         if (soc_is_dra7xx()) {
 706                 /*
 707                  * Errata i856 says the 32.768KHz crystal does not start at
 708                  * power on, so the CPU falls back to an emulated 32KHz clock
 709                  * based on sysclk / 610 instead. This causes the master counter
 710                  * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
 711                  * (OR sysclk * 75 / 244)
 712                  *
 713                  * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
 714                  * Of course any board built without a populated 32.768KHz
 715                  * crystal would also need this fix even if the CPU is fixed
 716                  * later.
 717                  *
 718                  * Either case can be detected by using the two speedselect bits
 719                  * If they are not 0, then the 32.768KHz clock driving the
 720                  * coarse counter that corrects the fine counter every time it
 721                  * ticks is actually rate/610 rather than 32.768KHz and we
 722                  * should compensate to avoid the 570ppm (at 20MHz, much worse
 723                  * at other rates) too fast system time.
 724                  */
 725                 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
 726                 if (reg & DRA7_SPEEDSELECT_MASK) {
 727                         num = 75;
 728                         den = 244;
 729                         goto sysclk1_based;
 730                 }
 731         }
 732
 733         /* Numerator/denumerator values refer TRM Realtime Counter section */
 734         switch (rate) {
 735         case 12000000:
 736                 num = 64;
 737                 den = 125;
 738                 break;
 739         case 13000000:
 740                 num = 768;
 741                 den = 1625;
 742                 break;
 743         case 19200000:
 744                 num = 8;
 745                 den = 25;
 746                 break;
 747         case 20000000:
 748                 num = 192;
 749                 den = 625;
 750                 break;
 751         case 26000000:
 752                 num = 384;
 753                 den = 1625;
 754                 break;
 755         case 27000000:
 756                 num = 256;
 757                 den = 1125;
 758                 break;
 759         case 38400000:
 760         default:
 761                 /* Program it for 38.4 MHz */
 762                 num = 4;
 763                 den = 25;
 764                 break;
 765         }
 766
 767 sysclk1_based:
 768         /* Program numerator and denumerator registers */
 769         reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
 770                         NUMERATOR_DENUMERATOR_MASK;
 771         reg |= num;
 772         writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
 773
 774         reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
 775                         NUMERATOR_DENUMERATOR_MASK;
 776         reg |= den;
 777         writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 778
 779         arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
 780         set_cntfreq();
 781
 782         iounmap(base);
 783 #endif
 784 }
 785
 786 void __init omap5_realtime_timer_init(void)
 787 {
 788         omap4_sync32k_timer_init();
 789         realtime_counter_init();
 790
 791         timer_probe();
 792 }
 793 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
 794
 795 /**
 796  * omap2_override_clocksource - clocksource override with user configuration
 797  *
 798  * Allows user to override default clocksource, using kernel parameter
 799  *   clocksource="gp_timer"     (For all OMAP2PLUS architectures)
 800  *
 801  * Note that, here we are using same standard kernel parameter "clocksource=",
 802  * and not introducing any OMAP specific interface.
 803  */
 804 static int __init omap2_override_clocksource(char *str)
 805 {
 806         if (!str)
 807                 return 0;
 808         /*
 809          * For OMAP architecture, we only have two options
 810          *    - sync_32k (default)
 811          *    - gp_timer (sys_clk based)
 812          */
 813         if (!strcmp(str, "gp_timer"))
 814                 use_gptimer_clksrc = true;
 815
 816         return 0;
 817 }
 818 early_param("clocksource", omap2_override_clocksource);