arch/arm/mach-omap2/prm44xx.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * OMAP44xx PRM instance offset macros
   4  *
   5  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  *
   8  * Paul Walmsley (paul@pwsan.com)
   9  * Rajendra Nayak (rnayak@ti.com)
  10  * Benoit Cousson (b-cousson@ti.com)
  11  *
  12  * This file is automatically generated from the OMAP hardware databases.
  13  * We respectfully ask that any modifications to this file be coordinated
  14  * with the public linux-omap@vger.kernel.org mailing list and the
  15  * authors above to ensure that the autogeneration scripts are kept
  16  * up-to-date with the file contents.
  17  *
  18  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
  19  *     or "OMAP4430".
  20  */
  21
  22 #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
  23 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
  24
  25 #include "prm44xx_54xx.h"
  26 #include "prm.h"
  27
  28 #define OMAP4430_PRM_BASE               0x4a306000
  29
  30 #define OMAP44XX_PRM_REGADDR(inst, reg)                         \
  31         OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
  32
  33
  34 /* PRM instances */
  35 #define OMAP4430_PRM_OCP_SOCKET_INST    0x0000
  36 #define OMAP4430_PRM_CKGEN_INST         0x0100
  37 #define OMAP4430_PRM_MPU_INST           0x0300
  38 #define OMAP4430_PRM_TESLA_INST         0x0400
  39 #define OMAP4430_PRM_ABE_INST           0x0500
  40 #define OMAP4430_PRM_ALWAYS_ON_INST     0x0600
  41 #define OMAP4430_PRM_CORE_INST          0x0700
  42 #define OMAP4430_PRM_IVAHD_INST         0x0f00
  43 #define OMAP4430_PRM_CAM_INST           0x1000
  44 #define OMAP4430_PRM_DSS_INST           0x1100
  45 #define OMAP4430_PRM_GFX_INST           0x1200
  46 #define OMAP4430_PRM_L3INIT_INST        0x1300
  47 #define OMAP4430_PRM_L4PER_INST         0x1400
  48 #define OMAP4430_PRM_CEFUSE_INST        0x1600
  49 #define OMAP4430_PRM_WKUP_INST          0x1700
  50 #define OMAP4430_PRM_WKUP_CM_INST       0x1800
  51 #define OMAP4430_PRM_EMU_INST           0x1900
  52 #define OMAP4430_PRM_EMU_CM_INST        0x1a00
  53 #define OMAP4430_PRM_DEVICE_INST        0x1b00
  54
  55 /* PRM clockdomain register offsets (from instance start) */
  56 #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS        0x0000
  57 #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS          0x0000
  58
  59 /* OMAP4 specific register offsets */
  60 #define OMAP4_RM_RSTST                                  0x0004
  61 #define OMAP4_PM_PWSTCTRL                               0x0000
  62 #define OMAP4_PM_PWSTST                                 0x0004
  63
  64 /* PRM.OCP_SOCKET_PRM register offsets */
  65 #define OMAP4_REVISION_PRM_OFFSET                       0x0000
  66 #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET                  0x0010
  67 #define OMAP4430_PRM_IRQSTATUS_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010)
  68 #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET                0x0014
  69 #define OMAP4_PRM_IRQENABLE_MPU_OFFSET                  0x0018
  70 #define OMAP4430_PRM_IRQENABLE_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018)
  71
  72 /* PRM.MPU_PRM register offsets */
  73 #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET                 0x0024
  74
  75 /* PRM.DEVICE_PRM register offsets */
  76 #define OMAP4_PRM_RSTCTRL_OFFSET                        0x0000
  77 #define OMAP4_PRM_VOLTCTRL_OFFSET                       0x0010
  78 #define OMAP4_PRM_IO_PMCTRL_OFFSET                      0x0020
  79 #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET             0x0028
  80 #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET              0x002c
  81 #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET              0x0030
  82 #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET       0x0034
  83 #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET        0x0038
  84 #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET        0x003c
  85 #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET                 0x0040
  86 #define OMAP4_PRM_VP_CORE_STATUS_OFFSET                 0x0044
  87 #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET               0x0048
  88 #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET                0x004c
  89 #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET               0x0050
  90 #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET               0x0054
  91 #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET                  0x0058
  92 #define OMAP4_PRM_VP_MPU_STATUS_OFFSET                  0x005c
  93 #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET                0x0060
  94 #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET                 0x0064
  95 #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET                0x0068
  96 #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET                0x006c
  97 #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET                  0x0070
  98 #define OMAP4_PRM_VP_IVA_STATUS_OFFSET                  0x0074
  99 #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET                0x0078
 100 #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET                 0x007c
 101 #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET                0x0080
 102 #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET                0x0084
 103 #define OMAP4_PRM_VC_SMPS_SA_OFFSET                     0x0088
 104 #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET             0x008c
 105 #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET             0x0090
 106 #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET          0x0094
 107 #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET           0x0098
 108 #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET           0x009c
 109 #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET                  0x00a0
 110 #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET                 0x00a4
 111 #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET                0x00a8
 112 #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET                 0x00ac
 113
 114 #endif