arch/arm/mach-omap2/prcm_mpu44xx.h

   1 /*
   2  * OMAP44xx PRCM MPU instance offset macros
   3  *
   4  * Copyright (C) 2010, 2012 Texas Instruments, Inc.
   5  * Copyright (C) 2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  *
  21  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
  22  *     or "OMAP4430".
  23  */
  24
  25 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
  26 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
  27
  28 #include "prcm_mpu_44xx_54xx.h"
  29
  30 #define OMAP4430_PRCM_MPU_BASE                  0x48243000
  31
  32 #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg)                            \
  33         OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
  34
  35 /* PRCM_MPU instances */
  36 #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST  0x0000
  37 #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST       0x0200
  38 #define OMAP4430_PRCM_MPU_CPU0_INST             0x0400
  39 #define OMAP4430_PRCM_MPU_CPU1_INST             0x0800
  40
  41 /* PRCM_MPU clockdomain register offsets (from instance start) */
  42 #define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS      0x0018
  43 #define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS      0x0018
  44
  45
  46 /*
  47  * PRCM_MPU
  48  *
  49  * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
  50  * point of view the PRCM_MPU is a single entity. It shares the same
  51  * programming model as the global PRCM and thus can be assimilate as two new
  52  * MOD inside the PRCM
  53  */
  54
  55 /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
  56 #define OMAP4_REVISION_PRCM_OFFSET              0x0000
  57 #define OMAP4430_REVISION_PRCM                  OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
  58
  59 /* PRCM_MPU.DEVICE_PRM register offsets */
  60 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET         0x0000
  61 #define OMAP4430_PRCM_MPU_PRM_RSTST             OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
  62 #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET   0x0004
  63 #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT       OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
  64
  65 /* PRCM_MPU.CPU0 register offsets */
  66 #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET          0x0000
  67 #define OMAP4430_PM_CPU0_PWRSTCTRL              OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
  68 #define OMAP4_PM_CPU0_PWRSTST_OFFSET            0x0004
  69 #define OMAP4430_PM_CPU0_PWRSTST                OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
  70 #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET       0x0008
  71 #define OMAP4430_RM_CPU0_CPU0_CONTEXT           OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
  72 #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET       0x000c
  73 #define OMAP4430_RM_CPU0_CPU0_RSTCTRL           OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
  74 #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET         0x0010
  75 #define OMAP4430_RM_CPU0_CPU0_RSTST             OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
  76 #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET       0x0014
  77 #define OMAP4430_CM_CPU0_CPU0_CLKCTRL           OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
  78 #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET          0x0018
  79 #define OMAP4430_CM_CPU0_CLKSTCTRL              OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
  80
  81 /* PRCM_MPU.CPU1 register offsets */
  82 #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET          0x0000
  83 #define OMAP4430_PM_CPU1_PWRSTCTRL              OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
  84 #define OMAP4_PM_CPU1_PWRSTST_OFFSET            0x0004
  85 #define OMAP4430_PM_CPU1_PWRSTST                OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
  86 #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET       0x0008
  87 #define OMAP4430_RM_CPU1_CPU1_CONTEXT           OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
  88 #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET       0x000c
  89 #define OMAP4430_RM_CPU1_CPU1_RSTCTRL           OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
  90 #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET         0x0010
  91 #define OMAP4430_RM_CPU1_CPU1_RSTST             OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
  92 #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET       0x0014
  93 #define OMAP4430_CM_CPU1_CPU1_CLKCTRL           OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
  94 #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET          0x0018
  95 #define OMAP4430_CM_CPU1_CLKSTCTRL              OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
  96
  97 #endif