arch/arm/mach-omap2/prcm43xx.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * AM43x PRCM defines
   4  *
   5  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
   9 #define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
  10
  11 #define AM43XX_PRM_PARTITION                            1
  12 #define AM43XX_CM_PARTITION                             1
  13
  14 /* PRM instances */
  15 #define AM43XX_PRM_OCP_SOCKET_INST                      0x0000
  16 #define AM43XX_PRM_MPU_INST                             0x0300
  17 #define AM43XX_PRM_GFX_INST                             0x0400
  18 #define AM43XX_PRM_RTC_INST                             0x0500
  19 #define AM43XX_PRM_TAMPER_INST                          0x0600
  20 #define AM43XX_PRM_CEFUSE_INST                          0x0700
  21 #define AM43XX_PRM_PER_INST                             0x0800
  22 #define AM43XX_PRM_WKUP_INST                            0x2000
  23 #define AM43XX_PRM_DEVICE_INST                          0x4000
  24
  25 /* PRM_IRQ offsets */
  26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET                 0x0004
  27 #define AM43XX_PRM_IRQENABLE_MPU_OFFSET                 0x0008
  28
  29 /* Other PRM offsets */
  30 #define AM43XX_PRM_IO_PMCTRL_OFFSET                     0x0024
  31
  32 /* CM instances */
  33 #define AM43XX_CM_WKUP_INST                             0x2800
  34 #define AM43XX_CM_MPU_INST                              0x8300
  35 #define AM43XX_CM_GFX_INST                              0x8400
  36 #define AM43XX_CM_RTC_INST                              0x8500
  37 #define AM43XX_CM_TAMPER_INST                           0x8600
  38 #define AM43XX_CM_CEFUSE_INST                           0x8700
  39 #define AM43XX_CM_PER_INST                              0x8800
  40
  41 /* CD offsets */
  42 #define AM43XX_CM_WKUP_L3_AON_CDOFFS                    0x0000
  43 #define AM43XX_CM_WKUP_L3S_TSC_CDOFFS                   0x0100
  44 #define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS               0x0200
  45 #define AM43XX_CM_WKUP_WKUP_CDOFFS                      0x0300
  46 #define AM43XX_CM_MPU_MPU_CDOFFS                        0x0000
  47 #define AM43XX_CM_GFX_GFX_L3_CDOFFS                     0x0000
  48 #define AM43XX_CM_RTC_RTC_CDOFFS                        0x0000
  49 #define AM43XX_CM_TAMPER_TAMPER_CDOFFS                  0x0000
  50 #define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS                  0x0000
  51 #define AM43XX_CM_PER_L3_CDOFFS                         0x0000
  52 #define AM43XX_CM_PER_L3S_CDOFFS                        0x0200
  53 #define AM43XX_CM_PER_ICSS_CDOFFS                       0x0300
  54 #define AM43XX_CM_PER_L4LS_CDOFFS                       0x0400
  55 #define AM43XX_CM_PER_EMIF_CDOFFS                       0x0700
  56 #define AM43XX_CM_PER_LCDC_CDOFFS                       0x0800
  57 #define AM43XX_CM_PER_DSS_CDOFFS                        0x0a00
  58 #define AM43XX_CM_PER_CPSW_CDOFFS                       0x0b00
  59 #define AM43XX_CM_PER_OCPWP_L3_CDOFFS                   0x0c00
  60
  61 /* CLK CTRL offsets */
  62 #define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET                0x0020
  63 #define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET               0x0720
  64
  65 #endif