2 * DRA7xx Power domains framework
4 * Copyright (C) 2009-2013 Texas Instruments, Inc.
5 * Copyright (C) 2009-2011 Nokia Corporation
7 * Generated by code originally written by:
8 * Abhijit Pagare (abhijitpagare@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 * Paul Walmsley (paul@pwsan.com)
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
23 #include <linux/kernel.h>
24 #include <linux/init.h>
26 #include "powerdomain.h"
28 #include "prcm-common.h"
31 #include "prcm_mpu7xx.h"
34 /* iva_7xx_pwrdm: IVA-HD power domain */
35 static struct powerdomain iva_7xx_pwrdm = {
37 .prcm_offs = DRA7XX_PRM_IVA_INST,
38 .prcm_partition = DRA7XX_PRM_PARTITION,
39 .pwrsts = PWRSTS_OFF_ON,
42 [0] = PWRSTS_ON, /* hwa_mem */
43 [1] = PWRSTS_ON, /* sl2_mem */
44 [2] = PWRSTS_ON, /* tcm1_mem */
45 [3] = PWRSTS_ON, /* tcm2_mem */
47 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
51 static struct powerdomain rtc_7xx_pwrdm = {
53 .prcm_offs = DRA7XX_PRM_RTC_INST,
54 .prcm_partition = DRA7XX_PRM_PARTITION,
58 /* custefuse_7xx_pwrdm: Customer efuse controller power domain */
59 static struct powerdomain custefuse_7xx_pwrdm = {
60 .name = "custefuse_pwrdm",
61 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
62 .prcm_partition = DRA7XX_PRM_PARTITION,
63 .pwrsts = PWRSTS_OFF_ON,
64 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
67 /* custefuse_aon_7xx_pwrdm: Customer efuse controller power domain */
68 static struct powerdomain custefuse_aon_7xx_pwrdm = {
69 .name = "custefuse_pwrdm",
70 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
71 .prcm_partition = DRA7XX_PRM_PARTITION,
75 /* ipu_7xx_pwrdm: Audio back end power domain */
76 static struct powerdomain ipu_7xx_pwrdm = {
78 .prcm_offs = DRA7XX_PRM_IPU_INST,
79 .prcm_partition = DRA7XX_PRM_PARTITION,
80 .pwrsts = PWRSTS_OFF_ON,
83 [0] = PWRSTS_ON, /* aessmem */
84 [1] = PWRSTS_ON, /* periphmem */
86 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
89 /* dss_7xx_pwrdm: Display subsystem power domain */
90 static struct powerdomain dss_7xx_pwrdm = {
92 .prcm_offs = DRA7XX_PRM_DSS_INST,
93 .prcm_partition = DRA7XX_PRM_PARTITION,
94 .pwrsts = PWRSTS_OFF_ON,
97 [0] = PWRSTS_ON, /* dss_mem */
99 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
102 /* l4per_7xx_pwrdm: Target peripherals power domain */
103 static struct powerdomain l4per_7xx_pwrdm = {
104 .name = "l4per_pwrdm",
105 .prcm_offs = DRA7XX_PRM_L4PER_INST,
106 .prcm_partition = DRA7XX_PRM_PARTITION,
110 [0] = PWRSTS_ON, /* nonretained_bank */
111 [1] = PWRSTS_ON, /* retained_bank */
113 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
116 /* gpu_7xx_pwrdm: 3D accelerator power domain */
117 static struct powerdomain gpu_7xx_pwrdm = {
119 .prcm_offs = DRA7XX_PRM_GPU_INST,
120 .prcm_partition = DRA7XX_PRM_PARTITION,
121 .pwrsts = PWRSTS_OFF_ON,
124 [0] = PWRSTS_ON, /* gpu_mem */
126 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
129 /* wkupaon_7xx_pwrdm: Wake-up power domain */
130 static struct powerdomain wkupaon_7xx_pwrdm = {
131 .name = "wkupaon_pwrdm",
132 .prcm_offs = DRA7XX_PRM_WKUPAON_INST,
133 .prcm_partition = DRA7XX_PRM_PARTITION,
137 [0] = PWRSTS_ON, /* wkup_bank */
141 /* core_7xx_pwrdm: CORE power domain */
142 static struct powerdomain core_7xx_pwrdm = {
143 .name = "core_pwrdm",
144 .prcm_offs = DRA7XX_PRM_CORE_INST,
145 .prcm_partition = DRA7XX_PRM_PARTITION,
149 [0] = PWRSTS_ON, /* core_nret_bank */
150 [1] = PWRSTS_ON, /* core_ocmram */
151 [2] = PWRSTS_ON, /* core_other_bank */
152 [3] = PWRSTS_ON, /* ipu_l2ram */
153 [4] = PWRSTS_ON, /* ipu_unicache */
155 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
158 /* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
159 static struct powerdomain coreaon_7xx_pwrdm = {
160 .name = "coreaon_pwrdm",
161 .prcm_offs = DRA7XX_PRM_COREAON_INST,
162 .prcm_partition = DRA7XX_PRM_PARTITION,
166 /* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
167 static struct powerdomain cpu0_7xx_pwrdm = {
168 .name = "cpu0_pwrdm",
169 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
170 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
171 .pwrsts = PWRSTS_RET_ON,
172 .pwrsts_logic_ret = PWRSTS_RET,
175 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
178 [0] = PWRSTS_ON, /* cpu0_l1 */
182 /* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
183 static struct powerdomain cpu1_7xx_pwrdm = {
184 .name = "cpu1_pwrdm",
185 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
186 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
187 .pwrsts = PWRSTS_RET_ON,
188 .pwrsts_logic_ret = PWRSTS_RET,
191 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
194 [0] = PWRSTS_ON, /* cpu1_l1 */
199 static struct powerdomain vpe_7xx_pwrdm = {
201 .prcm_offs = DRA7XX_PRM_VPE_INST,
202 .prcm_partition = DRA7XX_PRM_PARTITION,
203 .pwrsts = PWRSTS_OFF_ON,
206 [0] = PWRSTS_ON, /* vpe_bank */
208 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
211 /* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
212 static struct powerdomain mpu_7xx_pwrdm = {
214 .prcm_offs = DRA7XX_PRM_MPU_INST,
215 .prcm_partition = DRA7XX_PRM_PARTITION,
216 .pwrsts = PWRSTS_RET_ON,
217 .pwrsts_logic_ret = PWRSTS_RET,
220 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
221 [1] = PWRSTS_RET, /* mpu_ram */
224 [0] = PWRSTS_ON, /* mpu_l2 */
225 [1] = PWRSTS_ON, /* mpu_ram */
229 /* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
230 static struct powerdomain l3init_7xx_pwrdm = {
231 .name = "l3init_pwrdm",
232 .prcm_offs = DRA7XX_PRM_L3INIT_INST,
233 .prcm_partition = DRA7XX_PRM_PARTITION,
237 [0] = PWRSTS_ON, /* gmac_bank */
238 [1] = PWRSTS_ON, /* l3init_bank1 */
239 [2] = PWRSTS_ON, /* l3init_bank2 */
241 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
244 /* eve3_7xx_pwrdm: */
245 static struct powerdomain eve3_7xx_pwrdm = {
246 .name = "eve3_pwrdm",
247 .prcm_offs = DRA7XX_PRM_EVE3_INST,
248 .prcm_partition = DRA7XX_PRM_PARTITION,
249 .pwrsts = PWRSTS_OFF_ON,
252 [0] = PWRSTS_ON, /* eve3_bank */
254 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
257 /* emu_7xx_pwrdm: Emulation power domain */
258 static struct powerdomain emu_7xx_pwrdm = {
260 .prcm_offs = DRA7XX_PRM_EMU_INST,
261 .prcm_partition = DRA7XX_PRM_PARTITION,
262 .pwrsts = PWRSTS_OFF_ON,
265 [0] = PWRSTS_ON, /* emu_bank */
269 /* dsp2_7xx_pwrdm: */
270 static struct powerdomain dsp2_7xx_pwrdm = {
271 .name = "dsp2_pwrdm",
272 .prcm_offs = DRA7XX_PRM_DSP2_INST,
273 .prcm_partition = DRA7XX_PRM_PARTITION,
274 .pwrsts = PWRSTS_OFF_ON,
277 [0] = PWRSTS_ON, /* dsp2_edma */
278 [1] = PWRSTS_ON, /* dsp2_l1 */
279 [2] = PWRSTS_ON, /* dsp2_l2 */
281 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
284 /* dsp1_7xx_pwrdm: Tesla processor power domain */
285 static struct powerdomain dsp1_7xx_pwrdm = {
286 .name = "dsp1_pwrdm",
287 .prcm_offs = DRA7XX_PRM_DSP1_INST,
288 .prcm_partition = DRA7XX_PRM_PARTITION,
289 .pwrsts = PWRSTS_OFF_ON,
292 [0] = PWRSTS_ON, /* dsp1_edma */
293 [1] = PWRSTS_ON, /* dsp1_l1 */
294 [2] = PWRSTS_ON, /* dsp1_l2 */
296 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
299 /* cam_7xx_pwrdm: Camera subsystem power domain */
300 static struct powerdomain cam_7xx_pwrdm = {
302 .prcm_offs = DRA7XX_PRM_CAM_INST,
303 .prcm_partition = DRA7XX_PRM_PARTITION,
304 .pwrsts = PWRSTS_OFF_ON,
307 [0] = PWRSTS_ON, /* vip_bank */
309 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
312 /* eve4_7xx_pwrdm: */
313 static struct powerdomain eve4_7xx_pwrdm = {
314 .name = "eve4_pwrdm",
315 .prcm_offs = DRA7XX_PRM_EVE4_INST,
316 .prcm_partition = DRA7XX_PRM_PARTITION,
317 .pwrsts = PWRSTS_OFF_ON,
320 [0] = PWRSTS_ON, /* eve4_bank */
322 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
325 /* eve2_7xx_pwrdm: */
326 static struct powerdomain eve2_7xx_pwrdm = {
327 .name = "eve2_pwrdm",
328 .prcm_offs = DRA7XX_PRM_EVE2_INST,
329 .prcm_partition = DRA7XX_PRM_PARTITION,
330 .pwrsts = PWRSTS_OFF_ON,
333 [0] = PWRSTS_ON, /* eve2_bank */
335 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
338 /* eve1_7xx_pwrdm: */
339 static struct powerdomain eve1_7xx_pwrdm = {
340 .name = "eve1_pwrdm",
341 .prcm_offs = DRA7XX_PRM_EVE1_INST,
342 .prcm_partition = DRA7XX_PRM_PARTITION,
343 .pwrsts = PWRSTS_OFF_ON,
346 [0] = PWRSTS_ON, /* eve1_bank */
348 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
352 * The following power domains are not under SW control
358 /* As powerdomains are added or removed above, this list must also be changed */
359 static struct powerdomain *powerdomains_dra7xx[] __initdata = {
385 static struct powerdomain *powerdomains_dra76x[] __initdata = {
386 &custefuse_aon_7xx_pwrdm,
390 static struct powerdomain *powerdomains_dra74x[] __initdata = {
391 &custefuse_7xx_pwrdm,
395 static struct powerdomain *powerdomains_dra72x[] __initdata = {
396 &custefuse_aon_7xx_pwrdm,
400 void __init dra7xx_powerdomains_init(void)
402 pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
403 pwrdm_register_pwrdms(powerdomains_dra7xx);
406 pwrdm_register_pwrdms(powerdomains_dra76x);
407 else if (soc_is_dra74x())
408 pwrdm_register_pwrdms(powerdomains_dra74x);
409 else if (soc_is_dra72x())
410 pwrdm_register_pwrdms(powerdomains_dra72x);
412 pwrdm_complete_init();