arch/arm/mach-omap2/pm34xx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * OMAP3 Power Management Routines
   4  *
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  * Tony Lindgren <tony@atomide.com>
   7  * Jouni Hogander
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Rajendra Nayak <rnayak@ti.com>
  11  *
  12  * Copyright (C) 2005 Texas Instruments, Inc.
  13  * Richard Woodruff <r-woodruff2@ti.com>
  14  *
  15  * Based on pm.c for omap1
  16  */
  17
  18 #include <linux/cpu_pm.h>
  19 #include <linux/pm.h>
  20 #include <linux/suspend.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/list.h>
  24 #include <linux/err.h>
  25 #include <linux/clk.h>
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/omap-dma.h>
  29 #include <linux/omap-gpmc.h>
  30
  31 #include <trace/events/power.h>
  32
  33 #include <asm/fncpy.h>
  34 #include <asm/suspend.h>
  35 #include <asm/system_misc.h>
  36
  37 #include "clockdomain.h"
  38 #include "powerdomain.h"
  39 #include "soc.h"
  40 #include "common.h"
  41 #include "cm3xxx.h"
  42 #include "cm-regbits-34xx.h"
  43 #include "prm-regbits-34xx.h"
  44 #include "prm3xxx.h"
  45 #include "pm.h"
  46 #include "sdrc.h"
  47 #include "omap-secure.h"
  48 #include "sram.h"
  49 #include "control.h"
  50 #include "vc.h"
  51
  52 /* pm34xx errata defined in pm.h */
  53 u16 pm34xx_errata;
  54
  55 struct power_state {
  56         struct powerdomain *pwrdm;
  57         u32 next_state;
  58 #ifdef CONFIG_SUSPEND
  59         u32 saved_state;
  60 #endif
  61         struct list_head node;
  62 };
  63
  64 static LIST_HEAD(pwrst_list);
  65
  66 void (*omap3_do_wfi_sram)(void);
  67
  68 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  69 static struct powerdomain *core_pwrdm, *per_pwrdm;
  70
  71 static void omap3_core_save_context(void)
  72 {
  73         omap3_ctrl_save_padconf();
  74
  75         /*
  76          * Force write last pad into memory, as this can fail in some
  77          * cases according to errata 1.157, 1.185
  78          */
  79         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
  80                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
  81
  82         /* Save the Interrupt controller context */
  83         omap_intc_save_context();
  84         /* Save the GPMC context */
  85         omap3_gpmc_save_context();
  86         /* Save the system control module context, padconf already save above*/
  87         omap3_control_save_context();
  88         omap_dma_global_context_save();
  89 }
  90
  91 static void omap3_core_restore_context(void)
  92 {
  93         /* Restore the control module context, padconf restored by h/w */
  94         omap3_control_restore_context();
  95         /* Restore the GPMC context */
  96         omap3_gpmc_restore_context();
  97         /* Restore the interrupt controller context */
  98         omap_intc_restore_context();
  99         omap_dma_global_context_restore();
 100 }
 101
 102 /*
 103  * FIXME: This function should be called before entering off-mode after
 104  * OMAP3 secure services have been accessed. Currently it is only called
 105  * once during boot sequence, but this works as we are not using secure
 106  * services.
 107  */
 108 static void omap3_save_secure_ram_context(void)
 109 {
 110         u32 ret;
 111         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 112
 113         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 114                 /*
 115                  * MPU next state must be set to POWER_ON temporarily,
 116                  * otherwise the WFI executed inside the ROM code
 117                  * will hang the system.
 118                  */
 119                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 120                 ret = omap3_save_secure_ram(omap3_secure_ram_storage,
 121                                             OMAP3_SAVE_SECURE_RAM_SZ);
 122                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 123                 /* Following is for error tracking, it should not happen */
 124                 if (ret) {
 125                         pr_err("save_secure_sram() returns %08x\n", ret);
 126                         while (1)
 127                                 ;
 128                 }
 129         }
 130 }
 131
 132 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 133 {
 134         int c;
 135
 136         c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
 137                                     OMAP3430_ST_IO_CHAIN_MASK);
 138
 139         return c ? IRQ_HANDLED : IRQ_NONE;
 140 }
 141
 142 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
 143 {
 144         int c;
 145
 146         /*
 147          * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
 148          * these are handled in a separate handler to avoid acking
 149          * IO events before parsing in mux code
 150          */
 151         c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
 152                                                    OMAP3430_ST_IO_CHAIN_MASK));
 153         c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
 154         c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
 155         if (omap_rev() > OMAP3430_REV_ES1_0) {
 156                 c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
 157                 c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
 158         }
 159
 160         return c ? IRQ_HANDLED : IRQ_NONE;
 161 }
 162
 163 static void omap34xx_save_context(u32 *save)
 164 {
 165         u32 val;
 166
 167         /* Read Auxiliary Control Register */
 168         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
 169         *save++ = 1;
 170         *save++ = val;
 171
 172         /* Read L2 AUX ctrl register */
 173         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
 174         *save++ = 1;
 175         *save++ = val;
 176 }
 177
 178 static int omap34xx_do_sram_idle(unsigned long save_state)
 179 {
 180         omap34xx_cpu_suspend(save_state);
 181         return 0;
 182 }
 183
 184 void omap_sram_idle(void)
 185 {
 186         /* Variable to tell what needs to be saved and restored
 187          * in omap_sram_idle*/
 188         /* save_state = 0 => Nothing to save and restored */
 189         /* save_state = 1 => Only L1 and logic lost */
 190         /* save_state = 2 => Only L2 lost */
 191         /* save_state = 3 => L1, L2 and logic lost */
 192         int save_state = 0;
 193         int mpu_next_state = PWRDM_POWER_ON;
 194         int per_next_state = PWRDM_POWER_ON;
 195         int core_next_state = PWRDM_POWER_ON;
 196         u32 sdrc_pwr = 0;
 197         int error;
 198
 199         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 200         switch (mpu_next_state) {
 201         case PWRDM_POWER_ON:
 202         case PWRDM_POWER_RET:
 203                 /* No need to save context */
 204                 save_state = 0;
 205                 break;
 206         case PWRDM_POWER_OFF:
 207                 save_state = 3;
 208                 break;
 209         default:
 210                 /* Invalid state */
 211                 pr_err("Invalid mpu state in sram_idle\n");
 212                 return;
 213         }
 214
 215         /* NEON control */
 216         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 217                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 218
 219         /* Enable IO-PAD and IO-CHAIN wakeups */
 220         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 221         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 222
 223         pwrdm_pre_transition(NULL);
 224
 225         /* PER */
 226         if (per_next_state == PWRDM_POWER_OFF) {
 227                 error = cpu_cluster_pm_enter();
 228                 if (error)
 229                         return;
 230         }
 231
 232         /* CORE */
 233         if (core_next_state < PWRDM_POWER_ON) {
 234                 if (core_next_state == PWRDM_POWER_OFF) {
 235                         omap3_core_save_context();
 236                         omap3_cm_save_context();
 237                 }
 238         }
 239
 240         /* Configure PMIC signaling for I2C4 or sys_off_mode */
 241         omap3_vc_set_pmic_signaling(core_next_state);
 242
 243         omap3_intc_prepare_idle();
 244
 245         /*
 246          * On EMU/HS devices ROM code restores a SRDC value
 247          * from scratchpad which has automatic self refresh on timeout
 248          * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 249          * Hence store/restore the SDRC_POWER register here.
 250          */
 251         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 252             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 253              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 254             core_next_state == PWRDM_POWER_OFF)
 255                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 256
 257         /*
 258          * omap3_arm_context is the location where some ARM context
 259          * get saved. The rest is placed on the stack, and restored
 260          * from there before resuming.
 261          */
 262         if (save_state)
 263                 omap34xx_save_context(omap3_arm_context);
 264         if (save_state == 1 || save_state == 3)
 265                 cpu_suspend(save_state, omap34xx_do_sram_idle);
 266         else
 267                 omap34xx_do_sram_idle(save_state);
 268
 269         /* Restore normal SDRC POWER settings */
 270         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 271             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 272              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 273             core_next_state == PWRDM_POWER_OFF)
 274                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 275
 276         /* CORE */
 277         if (core_next_state < PWRDM_POWER_ON &&
 278             pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
 279                 omap3_core_restore_context();
 280                 omap3_cm_restore_context();
 281                 omap3_sram_restore_context();
 282                 omap2_sms_restore_context();
 283         } else {
 284                 /*
 285                  * In off-mode resume path above, omap3_core_restore_context
 286                  * also handles the INTC autoidle restore done here so limit
 287                  * this to non-off mode resume paths so we don't do it twice.
 288                  */
 289                 omap3_intc_resume_idle();
 290         }
 291
 292         pwrdm_post_transition(NULL);
 293
 294         /* PER */
 295         if (per_next_state == PWRDM_POWER_OFF)
 296                 cpu_cluster_pm_exit();
 297 }
 298
 299 static void omap3_pm_idle(void)
 300 {
 301         if (omap_irq_pending())
 302                 return;
 303
 304         trace_cpu_idle_rcuidle(1, smp_processor_id());
 305
 306         omap_sram_idle();
 307
 308         trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 309 }
 310
 311 #ifdef CONFIG_SUSPEND
 312 static int omap3_pm_suspend(void)
 313 {
 314         struct power_state *pwrst;
 315         int state, ret = 0;
 316
 317         /* Read current next_pwrsts */
 318         list_for_each_entry(pwrst, &pwrst_list, node)
 319                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 320         /* Set ones wanted by suspend */
 321         list_for_each_entry(pwrst, &pwrst_list, node) {
 322                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 323                         goto restore;
 324                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 325                         goto restore;
 326         }
 327
 328         omap3_intc_suspend();
 329
 330         omap_sram_idle();
 331
 332 restore:
 333         /* Restore next_pwrsts */
 334         list_for_each_entry(pwrst, &pwrst_list, node) {
 335                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 336                 if (state > pwrst->next_state) {
 337                         pr_info("Powerdomain (%s) didn't enter target state %d\n",
 338                                 pwrst->pwrdm->name, pwrst->next_state);
 339                         ret = -1;
 340                 }
 341                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 342         }
 343         if (ret)
 344                 pr_err("Could not enter target state in pm_suspend\n");
 345         else
 346                 pr_info("Successfully put all powerdomains to target state\n");
 347
 348         return ret;
 349 }
 350 #else
 351 #define omap3_pm_suspend NULL
 352 #endif /* CONFIG_SUSPEND */
 353
 354 static void __init prcm_setup_regs(void)
 355 {
 356         omap3_ctrl_init();
 357
 358         omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
 359 }
 360
 361 void omap3_pm_off_mode_enable(int enable)
 362 {
 363         struct power_state *pwrst;
 364         u32 state;
 365
 366         if (enable)
 367                 state = PWRDM_POWER_OFF;
 368         else
 369                 state = PWRDM_POWER_RET;
 370
 371         list_for_each_entry(pwrst, &pwrst_list, node) {
 372                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 373                                 pwrst->pwrdm == core_pwrdm &&
 374                                 state == PWRDM_POWER_OFF) {
 375                         pwrst->next_state = PWRDM_POWER_RET;
 376                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 377                                 __func__);
 378                 } else {
 379                         pwrst->next_state = state;
 380                 }
 381                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 382         }
 383 }
 384
 385 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 386 {
 387         struct power_state *pwrst;
 388
 389         list_for_each_entry(pwrst, &pwrst_list, node) {
 390                 if (pwrst->pwrdm == pwrdm)
 391                         return pwrst->next_state;
 392         }
 393         return -EINVAL;
 394 }
 395
 396 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 397 {
 398         struct power_state *pwrst;
 399
 400         list_for_each_entry(pwrst, &pwrst_list, node) {
 401                 if (pwrst->pwrdm == pwrdm) {
 402                         pwrst->next_state = state;
 403                         return 0;
 404                 }
 405         }
 406         return -EINVAL;
 407 }
 408
 409 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 410 {
 411         struct power_state *pwrst;
 412
 413         if (!pwrdm->pwrsts)
 414                 return 0;
 415
 416         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 417         if (!pwrst)
 418                 return -ENOMEM;
 419         pwrst->pwrdm = pwrdm;
 420         pwrst->next_state = PWRDM_POWER_RET;
 421         list_add(&pwrst->node, &pwrst_list);
 422
 423         if (pwrdm_has_hdwr_sar(pwrdm))
 424                 pwrdm_enable_hdwr_sar(pwrdm);
 425
 426         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 427 }
 428
 429 /*
 430  * Push functions to SRAM
 431  *
 432  * The minimum set of functions is pushed to SRAM for execution:
 433  * - omap3_do_wfi for erratum i581 WA,
 434  */
 435 void omap_push_sram_idle(void)
 436 {
 437         omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
 438 }
 439
 440 static void __init pm_errata_configure(void)
 441 {
 442         if (cpu_is_omap3630()) {
 443                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 444                 /* Enable the l2 cache toggling in sleep logic */
 445                 enable_omap3630_toggle_l2_on_restore();
 446                 if (omap_rev() < OMAP3630_REV_ES1_2)
 447                         pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
 448                                           PM_PER_MEMORIES_ERRATUM_i582);
 449         } else if (cpu_is_omap34xx()) {
 450                 pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
 451         }
 452 }
 453
 454 int __init omap3_pm_init(void)
 455 {
 456         struct power_state *pwrst, *tmp;
 457         struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
 458         int ret;
 459
 460         if (!omap3_has_io_chain_ctrl())
 461                 pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
 462
 463         pm_errata_configure();
 464
 465         /* XXX prcm_setup_regs needs to be before enabling hw
 466          * supervised mode for powerdomains */
 467         prcm_setup_regs();
 468
 469         ret = request_irq(omap_prcm_event_to_irq("wkup"),
 470                 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
 471
 472         if (ret) {
 473                 pr_err("pm: Failed to request pm_wkup irq\n");
 474                 goto err1;
 475         }
 476
 477         /* IO interrupt is shared with mux code */
 478         ret = request_irq(omap_prcm_event_to_irq("io"),
 479                 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
 480                 omap3_pm_init);
 481
 482         if (ret) {
 483                 pr_err("pm: Failed to request pm_io irq\n");
 484                 goto err2;
 485         }
 486
 487         ret = pwrdm_for_each(pwrdms_setup, NULL);
 488         if (ret) {
 489                 pr_err("Failed to setup powerdomains\n");
 490                 goto err3;
 491         }
 492
 493         (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
 494
 495         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 496         if (mpu_pwrdm == NULL) {
 497                 pr_err("Failed to get mpu_pwrdm\n");
 498                 ret = -EINVAL;
 499                 goto err3;
 500         }
 501
 502         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 503         per_pwrdm = pwrdm_lookup("per_pwrdm");
 504         core_pwrdm = pwrdm_lookup("core_pwrdm");
 505
 506         neon_clkdm = clkdm_lookup("neon_clkdm");
 507         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 508         per_clkdm = clkdm_lookup("per_clkdm");
 509         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 510
 511         omap_common_suspend_init(omap3_pm_suspend);
 512
 513         arm_pm_idle = omap3_pm_idle;
 514         omap3_idle_init();
 515
 516         /*
 517          * RTA is disabled during initialization as per erratum i608
 518          * it is safer to disable RTA by the bootloader, but we would like
 519          * to be doubly sure here and prevent any mishaps.
 520          */
 521         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 522                 omap3630_ctrl_disable_rta();
 523
 524         /*
 525          * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
 526          * not correctly reset when the PER powerdomain comes back
 527          * from OFF or OSWR when the CORE powerdomain is kept active.
 528          * See OMAP36xx Erratum i582 "PER Domain reset issue after
 529          * Domain-OFF/OSWR Wakeup".  This wakeup dependency is not a
 530          * complete workaround.  The kernel must also prevent the PER
 531          * powerdomain from going to OSWR/OFF while the CORE
 532          * powerdomain is not going to OSWR/OFF.  And if PER last
 533          * power state was off while CORE last power state was ON, the
 534          * UART3/4 and McBSP2/3 SIDETONE devices need to run a
 535          * self-test using their loopback tests; if that fails, those
 536          * devices are unusable until the PER/CORE can complete a transition
 537          * from ON to OSWR/OFF and then back to ON.
 538          *
 539          * XXX Technically this workaround is only needed if off-mode
 540          * or OSWR is enabled.
 541          */
 542         if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
 543                 clkdm_add_wkdep(per_clkdm, wkup_clkdm);
 544
 545         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 546         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 547                 omap3_secure_ram_storage =
 548                         kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL);
 549                 if (!omap3_secure_ram_storage)
 550                         pr_err("Memory allocation failed when allocating for secure sram context\n");
 551
 552                 local_irq_disable();
 553
 554                 omap_dma_global_context_save();
 555                 omap3_save_secure_ram_context();
 556                 omap_dma_global_context_restore();
 557
 558                 local_irq_enable();
 559         }
 560
 561         omap3_save_scratchpad_contents();
 562         return ret;
 563
 564 err3:
 565         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 566                 list_del(&pwrst->node);
 567                 kfree(pwrst);
 568         }
 569         free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
 570 err2:
 571         free_irq(omap_prcm_event_to_irq("wkup"), NULL);
 572 err1:
 573         return ret;
 574 }