2 * Hardware modules present on the DRA7xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/platform_data/hsmmc-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/i2c-omap.h>
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
40 /* Base offset for all DRA7XX interrupts external to MPUSS */
41 #define DRA7XX_IRQ_GIC_START 32
43 /* Base offset for all DRA7XX dma requests */
44 #define DRA7XX_DMA_REQ_START 1
55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
60 static struct omap_hwmod dra7xx_dmm_hwmod = {
62 .class = &dra7xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
66 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
74 * instance(s): l3_instr, l3_main_1, l3_main_2
76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
81 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
83 .class = &dra7xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
87 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
97 .class = &dra7xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
101 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
110 .class = &dra7xx_l3_hwmod_class,
111 .clkdm_name = "l3instr_clkdm",
114 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
116 .modulemode = MODULEMODE_HWCTRL,
123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
132 .class = &dra7xx_l4_hwmod_class,
133 .clkdm_name = "l4cfg_clkdm",
136 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
143 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
145 .class = &dra7xx_l4_hwmod_class,
146 .clkdm_name = "l4per_clkdm",
149 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
156 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
158 .class = &dra7xx_l4_hwmod_class,
159 .clkdm_name = "l4per2_clkdm",
162 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
163 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
169 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
171 .class = &dra7xx_l4_hwmod_class,
172 .clkdm_name = "l4per3_clkdm",
175 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
176 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
184 .class = &dra7xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
188 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
204 static struct omap_hwmod dra7xx_atl_hwmod = {
206 .class = &dra7xx_atl_hwmod_class,
207 .clkdm_name = "atl_clkdm",
208 .main_clk = "atl_gfclk_mux",
211 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL,
223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
228 static struct omap_hwmod dra7xx_bb2d_hwmod = {
230 .class = &dra7xx_bb2d_hwmod_class,
231 .clkdm_name = "dss_clkdm",
232 .main_clk = "dpll_core_h24x2_ck",
235 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_SWCTRL,
247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
250 .sysc_flags = SYSC_HAS_SIDLEMODE,
251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
253 .sysc_fields = &omap_hwmod_sysc_type1,
256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
258 .sysc = &dra7xx_counter_sysc,
262 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
263 .name = "counter_32k",
264 .class = &dra7xx_counter_hwmod_class,
265 .clkdm_name = "wkupaon_clkdm",
266 .flags = HWMOD_SWSUP_SIDLE,
267 .main_clk = "wkupaon_iclk_mux",
270 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
277 * 'ctrl_module' class
281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
282 .name = "ctrl_module",
285 /* ctrl_module_wkup */
286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
287 .name = "ctrl_module_wkup",
288 .class = &dra7xx_ctrl_module_hwmod_class,
289 .clkdm_name = "wkupaon_clkdm",
292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
299 * cpsw/gmac sub system
301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
306 SYSS_HAS_RESET_STATUS),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
309 .sysc_fields = &omap_hwmod_sysc_type3,
312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
314 .sysc = &dra7xx_gmac_sysc,
317 static struct omap_hwmod dra7xx_gmac_hwmod = {
319 .class = &dra7xx_gmac_hwmod_class,
320 .clkdm_name = "gmac_clkdm",
321 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
322 .main_clk = "dpll_gmac_ck",
326 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
328 .modulemode = MODULEMODE_SWCTRL,
336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
337 .name = "davinci_mdio",
340 static struct omap_hwmod dra7xx_mdio_hwmod = {
341 .name = "davinci_mdio",
342 .class = &dra7xx_mdio_hwmod_class,
343 .clkdm_name = "gmac_clkdm",
344 .main_clk = "dpll_gmac_ck",
352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
357 static struct omap_hwmod dra7xx_dcan1_hwmod = {
359 .class = &dra7xx_dcan_hwmod_class,
360 .clkdm_name = "wkupaon_clkdm",
361 .main_clk = "dcan1_sys_clk_mux",
364 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
365 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
366 .modulemode = MODULEMODE_SWCTRL,
372 static struct omap_hwmod dra7xx_dcan2_hwmod = {
374 .class = &dra7xx_dcan_hwmod_class,
375 .clkdm_name = "l4per2_clkdm",
376 .main_clk = "sys_clkin1",
379 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
380 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
381 .modulemode = MODULEMODE_SWCTRL,
387 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
390 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
391 SYSC_HAS_RESET_STATUS,
392 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
393 .sysc_fields = &omap_hwmod_sysc_type2,
399 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
401 .sysc = &dra7xx_epwmss_sysc,
405 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
407 .class = &dra7xx_epwmss_hwmod_class,
408 .clkdm_name = "l4per2_clkdm",
409 .main_clk = "l4_root_clk_div",
412 .modulemode = MODULEMODE_SWCTRL,
413 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
414 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
420 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
422 .class = &dra7xx_epwmss_hwmod_class,
423 .clkdm_name = "l4per2_clkdm",
424 .main_clk = "l4_root_clk_div",
427 .modulemode = MODULEMODE_SWCTRL,
428 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
429 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
435 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
437 .class = &dra7xx_epwmss_hwmod_class,
438 .clkdm_name = "l4per2_clkdm",
439 .main_clk = "l4_root_clk_div",
442 .modulemode = MODULEMODE_SWCTRL,
443 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
444 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
454 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
458 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
459 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
460 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
461 SYSS_HAS_RESET_STATUS),
462 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
463 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
464 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
465 .sysc_fields = &omap_hwmod_sysc_type1,
468 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
470 .sysc = &dra7xx_dma_sysc,
474 static struct omap_dma_dev_attr dma_dev_attr = {
475 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
476 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
481 static struct omap_hwmod dra7xx_dma_system_hwmod = {
482 .name = "dma_system",
483 .class = &dra7xx_dma_hwmod_class,
484 .clkdm_name = "dma_clkdm",
485 .main_clk = "l3_iclk_div",
488 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
489 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
492 .dev_attr = &dma_dev_attr,
499 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
503 static struct omap_hwmod dra7xx_tpcc_hwmod = {
505 .class = &dra7xx_tpcc_hwmod_class,
506 .clkdm_name = "l3main1_clkdm",
507 .main_clk = "l3_iclk_div",
510 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
511 .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
520 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
525 static struct omap_hwmod dra7xx_tptc0_hwmod = {
527 .class = &dra7xx_tptc_hwmod_class,
528 .clkdm_name = "l3main1_clkdm",
529 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
530 .main_clk = "l3_iclk_div",
533 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
534 .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
535 .modulemode = MODULEMODE_HWCTRL,
541 static struct omap_hwmod dra7xx_tptc1_hwmod = {
543 .class = &dra7xx_tptc_hwmod_class,
544 .clkdm_name = "l3main1_clkdm",
545 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
546 .main_clk = "l3_iclk_div",
549 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
550 .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
551 .modulemode = MODULEMODE_HWCTRL,
561 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
564 .sysc_flags = SYSS_HAS_RESET_STATUS,
567 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
569 .sysc = &dra7xx_dss_sysc,
570 .reset = omap_dss_reset,
574 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
575 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
579 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
580 { .role = "dss_clk", .clk = "dss_dss_clk" },
581 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
582 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
583 { .role = "video2_clk", .clk = "dss_video2_clk" },
584 { .role = "video1_clk", .clk = "dss_video1_clk" },
585 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
586 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
589 static struct omap_hwmod dra7xx_dss_hwmod = {
591 .class = &dra7xx_dss_hwmod_class,
592 .clkdm_name = "dss_clkdm",
593 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
594 .sdma_reqs = dra7xx_dss_sdma_reqs,
595 .main_clk = "dss_dss_clk",
598 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
599 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
600 .modulemode = MODULEMODE_SWCTRL,
603 .opt_clks = dss_opt_clks,
604 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
612 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
616 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
617 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
618 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
619 SYSS_HAS_RESET_STATUS),
620 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
621 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
622 .sysc_fields = &omap_hwmod_sysc_type1,
625 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
627 .sysc = &dra7xx_dispc_sysc,
631 /* dss_dispc dev_attr */
632 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
633 .has_framedonetv_irq = 1,
637 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
639 .class = &dra7xx_dispc_hwmod_class,
640 .clkdm_name = "dss_clkdm",
641 .main_clk = "dss_dss_clk",
644 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
645 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
648 .dev_attr = &dss_dispc_dev_attr,
649 .parent_hwmod = &dra7xx_dss_hwmod,
657 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
660 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
662 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
664 .sysc_fields = &omap_hwmod_sysc_type2,
667 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
669 .sysc = &dra7xx_hdmi_sysc,
674 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
675 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
678 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
680 .class = &dra7xx_hdmi_hwmod_class,
681 .clkdm_name = "dss_clkdm",
682 .main_clk = "dss_48mhz_clk",
685 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
686 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
689 .opt_clks = dss_hdmi_opt_clks,
690 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
691 .parent_hwmod = &dra7xx_dss_hwmod,
699 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
703 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
704 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
705 SYSS_HAS_RESET_STATUS),
706 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
708 .sysc_fields = &omap_hwmod_sysc_type1,
711 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
713 .sysc = &dra7xx_elm_sysc,
718 static struct omap_hwmod dra7xx_elm_hwmod = {
720 .class = &dra7xx_elm_hwmod_class,
721 .clkdm_name = "l4per_clkdm",
722 .main_clk = "l3_iclk_div",
725 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
726 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
736 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
740 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
741 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
742 SYSS_HAS_RESET_STATUS),
743 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
745 .sysc_fields = &omap_hwmod_sysc_type1,
748 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
750 .sysc = &dra7xx_gpio_sysc,
755 static struct omap_gpio_dev_attr gpio_dev_attr = {
761 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
762 { .role = "dbclk", .clk = "gpio1_dbclk" },
765 static struct omap_hwmod dra7xx_gpio1_hwmod = {
767 .class = &dra7xx_gpio_hwmod_class,
768 .clkdm_name = "wkupaon_clkdm",
769 .main_clk = "wkupaon_iclk_mux",
772 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
773 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
774 .modulemode = MODULEMODE_HWCTRL,
777 .opt_clks = gpio1_opt_clks,
778 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
779 .dev_attr = &gpio_dev_attr,
783 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
784 { .role = "dbclk", .clk = "gpio2_dbclk" },
787 static struct omap_hwmod dra7xx_gpio2_hwmod = {
789 .class = &dra7xx_gpio_hwmod_class,
790 .clkdm_name = "l4per_clkdm",
791 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
792 .main_clk = "l3_iclk_div",
795 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
796 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
797 .modulemode = MODULEMODE_HWCTRL,
800 .opt_clks = gpio2_opt_clks,
801 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
802 .dev_attr = &gpio_dev_attr,
806 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
807 { .role = "dbclk", .clk = "gpio3_dbclk" },
810 static struct omap_hwmod dra7xx_gpio3_hwmod = {
812 .class = &dra7xx_gpio_hwmod_class,
813 .clkdm_name = "l4per_clkdm",
814 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
815 .main_clk = "l3_iclk_div",
818 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
819 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
820 .modulemode = MODULEMODE_HWCTRL,
823 .opt_clks = gpio3_opt_clks,
824 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
825 .dev_attr = &gpio_dev_attr,
829 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
830 { .role = "dbclk", .clk = "gpio4_dbclk" },
833 static struct omap_hwmod dra7xx_gpio4_hwmod = {
835 .class = &dra7xx_gpio_hwmod_class,
836 .clkdm_name = "l4per_clkdm",
837 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
838 .main_clk = "l3_iclk_div",
841 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
842 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
843 .modulemode = MODULEMODE_HWCTRL,
846 .opt_clks = gpio4_opt_clks,
847 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
848 .dev_attr = &gpio_dev_attr,
852 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
853 { .role = "dbclk", .clk = "gpio5_dbclk" },
856 static struct omap_hwmod dra7xx_gpio5_hwmod = {
858 .class = &dra7xx_gpio_hwmod_class,
859 .clkdm_name = "l4per_clkdm",
860 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
861 .main_clk = "l3_iclk_div",
864 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
865 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
866 .modulemode = MODULEMODE_HWCTRL,
869 .opt_clks = gpio5_opt_clks,
870 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
871 .dev_attr = &gpio_dev_attr,
875 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
876 { .role = "dbclk", .clk = "gpio6_dbclk" },
879 static struct omap_hwmod dra7xx_gpio6_hwmod = {
881 .class = &dra7xx_gpio_hwmod_class,
882 .clkdm_name = "l4per_clkdm",
883 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
884 .main_clk = "l3_iclk_div",
887 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
888 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
889 .modulemode = MODULEMODE_HWCTRL,
892 .opt_clks = gpio6_opt_clks,
893 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
894 .dev_attr = &gpio_dev_attr,
898 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
899 { .role = "dbclk", .clk = "gpio7_dbclk" },
902 static struct omap_hwmod dra7xx_gpio7_hwmod = {
904 .class = &dra7xx_gpio_hwmod_class,
905 .clkdm_name = "l4per_clkdm",
906 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
907 .main_clk = "l3_iclk_div",
910 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
911 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
912 .modulemode = MODULEMODE_HWCTRL,
915 .opt_clks = gpio7_opt_clks,
916 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
917 .dev_attr = &gpio_dev_attr,
921 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
922 { .role = "dbclk", .clk = "gpio8_dbclk" },
925 static struct omap_hwmod dra7xx_gpio8_hwmod = {
927 .class = &dra7xx_gpio_hwmod_class,
928 .clkdm_name = "l4per_clkdm",
929 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
930 .main_clk = "l3_iclk_div",
933 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
934 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
935 .modulemode = MODULEMODE_HWCTRL,
938 .opt_clks = gpio8_opt_clks,
939 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
940 .dev_attr = &gpio_dev_attr,
948 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
952 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
953 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
954 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
955 .sysc_fields = &omap_hwmod_sysc_type1,
958 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
960 .sysc = &dra7xx_gpmc_sysc,
965 static struct omap_hwmod dra7xx_gpmc_hwmod = {
967 .class = &dra7xx_gpmc_hwmod_class,
968 .clkdm_name = "l3main1_clkdm",
969 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
970 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
971 .main_clk = "l3_iclk_div",
974 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
975 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
976 .modulemode = MODULEMODE_HWCTRL,
986 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
990 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
991 SYSS_HAS_RESET_STATUS),
992 .sysc_fields = &omap_hwmod_sysc_type1,
995 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
997 .sysc = &dra7xx_hdq1w_sysc,
1002 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1004 .class = &dra7xx_hdq1w_hwmod_class,
1005 .clkdm_name = "l4per_clkdm",
1006 .flags = HWMOD_INIT_NO_RESET,
1007 .main_clk = "func_12m_fclk",
1010 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1011 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1012 .modulemode = MODULEMODE_SWCTRL,
1022 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1023 .sysc_offs = 0x0010,
1024 .syss_offs = 0x0090,
1025 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1026 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1027 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1028 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1030 .clockact = CLOCKACT_TEST_ICLK,
1031 .sysc_fields = &omap_hwmod_sysc_type1,
1034 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1036 .sysc = &dra7xx_i2c_sysc,
1037 .reset = &omap_i2c_reset,
1038 .rev = OMAP_I2C_IP_VERSION_2,
1042 static struct omap_i2c_dev_attr i2c_dev_attr = {
1043 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1047 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1049 .class = &dra7xx_i2c_hwmod_class,
1050 .clkdm_name = "l4per_clkdm",
1051 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1052 .main_clk = "func_96m_fclk",
1055 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1056 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1057 .modulemode = MODULEMODE_SWCTRL,
1060 .dev_attr = &i2c_dev_attr,
1064 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1066 .class = &dra7xx_i2c_hwmod_class,
1067 .clkdm_name = "l4per_clkdm",
1068 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1069 .main_clk = "func_96m_fclk",
1072 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1073 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1074 .modulemode = MODULEMODE_SWCTRL,
1077 .dev_attr = &i2c_dev_attr,
1081 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1083 .class = &dra7xx_i2c_hwmod_class,
1084 .clkdm_name = "l4per_clkdm",
1085 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1086 .main_clk = "func_96m_fclk",
1089 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1090 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1091 .modulemode = MODULEMODE_SWCTRL,
1094 .dev_attr = &i2c_dev_attr,
1098 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1100 .class = &dra7xx_i2c_hwmod_class,
1101 .clkdm_name = "l4per_clkdm",
1102 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1103 .main_clk = "func_96m_fclk",
1106 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1107 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1108 .modulemode = MODULEMODE_SWCTRL,
1111 .dev_attr = &i2c_dev_attr,
1115 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1117 .class = &dra7xx_i2c_hwmod_class,
1118 .clkdm_name = "ipu_clkdm",
1119 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1120 .main_clk = "func_96m_fclk",
1123 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1124 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1125 .modulemode = MODULEMODE_SWCTRL,
1128 .dev_attr = &i2c_dev_attr,
1136 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1138 .sysc_offs = 0x0010,
1139 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1140 SYSC_HAS_SOFTRESET),
1141 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1142 .sysc_fields = &omap_hwmod_sysc_type2,
1145 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1147 .sysc = &dra7xx_mailbox_sysc,
1151 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1153 .class = &dra7xx_mailbox_hwmod_class,
1154 .clkdm_name = "l4cfg_clkdm",
1157 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1158 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1164 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1166 .class = &dra7xx_mailbox_hwmod_class,
1167 .clkdm_name = "l4cfg_clkdm",
1170 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1171 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1177 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1179 .class = &dra7xx_mailbox_hwmod_class,
1180 .clkdm_name = "l4cfg_clkdm",
1183 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1184 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1190 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1192 .class = &dra7xx_mailbox_hwmod_class,
1193 .clkdm_name = "l4cfg_clkdm",
1196 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1197 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1203 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1205 .class = &dra7xx_mailbox_hwmod_class,
1206 .clkdm_name = "l4cfg_clkdm",
1209 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1210 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1216 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1218 .class = &dra7xx_mailbox_hwmod_class,
1219 .clkdm_name = "l4cfg_clkdm",
1222 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1223 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1229 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1231 .class = &dra7xx_mailbox_hwmod_class,
1232 .clkdm_name = "l4cfg_clkdm",
1235 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1236 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1242 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1244 .class = &dra7xx_mailbox_hwmod_class,
1245 .clkdm_name = "l4cfg_clkdm",
1248 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1249 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1255 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1257 .class = &dra7xx_mailbox_hwmod_class,
1258 .clkdm_name = "l4cfg_clkdm",
1261 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1262 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1268 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1269 .name = "mailbox10",
1270 .class = &dra7xx_mailbox_hwmod_class,
1271 .clkdm_name = "l4cfg_clkdm",
1274 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1275 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1281 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1282 .name = "mailbox11",
1283 .class = &dra7xx_mailbox_hwmod_class,
1284 .clkdm_name = "l4cfg_clkdm",
1287 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1288 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1294 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1295 .name = "mailbox12",
1296 .class = &dra7xx_mailbox_hwmod_class,
1297 .clkdm_name = "l4cfg_clkdm",
1300 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1301 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1307 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1308 .name = "mailbox13",
1309 .class = &dra7xx_mailbox_hwmod_class,
1310 .clkdm_name = "l4cfg_clkdm",
1313 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1314 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1324 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1326 .sysc_offs = 0x0010,
1327 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1328 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1329 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1331 .sysc_fields = &omap_hwmod_sysc_type2,
1334 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1336 .sysc = &dra7xx_mcspi_sysc,
1337 .rev = OMAP4_MCSPI_REV,
1341 /* mcspi1 dev_attr */
1342 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1343 .num_chipselect = 4,
1346 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1348 .class = &dra7xx_mcspi_hwmod_class,
1349 .clkdm_name = "l4per_clkdm",
1350 .main_clk = "func_48m_fclk",
1353 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1354 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1355 .modulemode = MODULEMODE_SWCTRL,
1358 .dev_attr = &mcspi1_dev_attr,
1362 /* mcspi2 dev_attr */
1363 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1364 .num_chipselect = 2,
1367 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1369 .class = &dra7xx_mcspi_hwmod_class,
1370 .clkdm_name = "l4per_clkdm",
1371 .main_clk = "func_48m_fclk",
1374 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1375 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1376 .modulemode = MODULEMODE_SWCTRL,
1379 .dev_attr = &mcspi2_dev_attr,
1383 /* mcspi3 dev_attr */
1384 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1385 .num_chipselect = 2,
1388 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1390 .class = &dra7xx_mcspi_hwmod_class,
1391 .clkdm_name = "l4per_clkdm",
1392 .main_clk = "func_48m_fclk",
1395 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1396 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1397 .modulemode = MODULEMODE_SWCTRL,
1400 .dev_attr = &mcspi3_dev_attr,
1404 /* mcspi4 dev_attr */
1405 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1406 .num_chipselect = 1,
1409 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1411 .class = &dra7xx_mcspi_hwmod_class,
1412 .clkdm_name = "l4per_clkdm",
1413 .main_clk = "func_48m_fclk",
1416 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1417 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1418 .modulemode = MODULEMODE_SWCTRL,
1421 .dev_attr = &mcspi4_dev_attr,
1428 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1429 .sysc_offs = 0x0004,
1430 .sysc_flags = SYSC_HAS_SIDLEMODE,
1431 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1432 .sysc_fields = &omap_hwmod_sysc_type3,
1435 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1437 .sysc = &dra7xx_mcasp_sysc,
1441 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1442 { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1443 { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1446 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1448 .class = &dra7xx_mcasp_hwmod_class,
1449 .clkdm_name = "ipu_clkdm",
1450 .main_clk = "mcasp1_aux_gfclk_mux",
1451 .flags = HWMOD_OPT_CLKS_NEEDED,
1454 .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1455 .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1456 .modulemode = MODULEMODE_SWCTRL,
1459 .opt_clks = mcasp1_opt_clks,
1460 .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks),
1464 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1465 { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1466 { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1469 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1471 .class = &dra7xx_mcasp_hwmod_class,
1472 .clkdm_name = "l4per2_clkdm",
1473 .main_clk = "mcasp2_aux_gfclk_mux",
1474 .flags = HWMOD_OPT_CLKS_NEEDED,
1477 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1478 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1479 .modulemode = MODULEMODE_SWCTRL,
1482 .opt_clks = mcasp2_opt_clks,
1483 .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks),
1487 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1488 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1491 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1493 .class = &dra7xx_mcasp_hwmod_class,
1494 .clkdm_name = "l4per2_clkdm",
1495 .main_clk = "mcasp3_aux_gfclk_mux",
1496 .flags = HWMOD_OPT_CLKS_NEEDED,
1499 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1500 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1501 .modulemode = MODULEMODE_SWCTRL,
1504 .opt_clks = mcasp3_opt_clks,
1505 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
1509 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1510 { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1513 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1515 .class = &dra7xx_mcasp_hwmod_class,
1516 .clkdm_name = "l4per2_clkdm",
1517 .main_clk = "mcasp4_aux_gfclk_mux",
1518 .flags = HWMOD_OPT_CLKS_NEEDED,
1521 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1522 .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1523 .modulemode = MODULEMODE_SWCTRL,
1526 .opt_clks = mcasp4_opt_clks,
1527 .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks),
1531 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1532 { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1535 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1537 .class = &dra7xx_mcasp_hwmod_class,
1538 .clkdm_name = "l4per2_clkdm",
1539 .main_clk = "mcasp5_aux_gfclk_mux",
1540 .flags = HWMOD_OPT_CLKS_NEEDED,
1543 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1544 .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1545 .modulemode = MODULEMODE_SWCTRL,
1548 .opt_clks = mcasp5_opt_clks,
1549 .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks),
1553 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1554 { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1557 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1559 .class = &dra7xx_mcasp_hwmod_class,
1560 .clkdm_name = "l4per2_clkdm",
1561 .main_clk = "mcasp6_aux_gfclk_mux",
1562 .flags = HWMOD_OPT_CLKS_NEEDED,
1565 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1566 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1567 .modulemode = MODULEMODE_SWCTRL,
1570 .opt_clks = mcasp6_opt_clks,
1571 .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks),
1575 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1576 { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1579 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1581 .class = &dra7xx_mcasp_hwmod_class,
1582 .clkdm_name = "l4per2_clkdm",
1583 .main_clk = "mcasp7_aux_gfclk_mux",
1584 .flags = HWMOD_OPT_CLKS_NEEDED,
1587 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1588 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1589 .modulemode = MODULEMODE_SWCTRL,
1592 .opt_clks = mcasp7_opt_clks,
1593 .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks),
1597 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1598 { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1601 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1603 .class = &dra7xx_mcasp_hwmod_class,
1604 .clkdm_name = "l4per2_clkdm",
1605 .main_clk = "mcasp8_aux_gfclk_mux",
1606 .flags = HWMOD_OPT_CLKS_NEEDED,
1609 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1610 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1611 .modulemode = MODULEMODE_SWCTRL,
1614 .opt_clks = mcasp8_opt_clks,
1615 .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks),
1623 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1625 .sysc_offs = 0x0010,
1626 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1627 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1628 SYSC_HAS_SOFTRESET),
1629 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1630 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1631 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1632 .sysc_fields = &omap_hwmod_sysc_type2,
1635 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1637 .sysc = &dra7xx_mmc_sysc,
1641 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1642 { .role = "clk32k", .clk = "mmc1_clk32k" },
1646 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1647 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1650 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1652 .class = &dra7xx_mmc_hwmod_class,
1653 .clkdm_name = "l3init_clkdm",
1654 .main_clk = "mmc1_fclk_div",
1657 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1658 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1659 .modulemode = MODULEMODE_SWCTRL,
1662 .opt_clks = mmc1_opt_clks,
1663 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1664 .dev_attr = &mmc1_dev_attr,
1668 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1669 { .role = "clk32k", .clk = "mmc2_clk32k" },
1672 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1674 .class = &dra7xx_mmc_hwmod_class,
1675 .clkdm_name = "l3init_clkdm",
1676 .main_clk = "mmc2_fclk_div",
1679 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1680 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1681 .modulemode = MODULEMODE_SWCTRL,
1684 .opt_clks = mmc2_opt_clks,
1685 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1689 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1690 { .role = "clk32k", .clk = "mmc3_clk32k" },
1693 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1695 .class = &dra7xx_mmc_hwmod_class,
1696 .clkdm_name = "l4per_clkdm",
1697 .main_clk = "mmc3_gfclk_div",
1700 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1701 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1702 .modulemode = MODULEMODE_SWCTRL,
1705 .opt_clks = mmc3_opt_clks,
1706 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1710 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1711 { .role = "clk32k", .clk = "mmc4_clk32k" },
1714 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1716 .class = &dra7xx_mmc_hwmod_class,
1717 .clkdm_name = "l4per_clkdm",
1718 .main_clk = "mmc4_gfclk_div",
1721 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1722 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1723 .modulemode = MODULEMODE_SWCTRL,
1726 .opt_clks = mmc4_opt_clks,
1727 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1735 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1740 static struct omap_hwmod dra7xx_mpu_hwmod = {
1742 .class = &dra7xx_mpu_hwmod_class,
1743 .clkdm_name = "mpu_clkdm",
1744 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1745 .main_clk = "dpll_mpu_m2_ck",
1748 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1749 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1759 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1761 .sysc_offs = 0x0010,
1762 .syss_offs = 0x0014,
1763 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1764 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1765 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1766 .sysc_fields = &omap_hwmod_sysc_type1,
1769 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1771 .sysc = &dra7xx_ocp2scp_sysc,
1775 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1777 .class = &dra7xx_ocp2scp_hwmod_class,
1778 .clkdm_name = "l3init_clkdm",
1779 .main_clk = "l4_root_clk_div",
1782 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1783 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1784 .modulemode = MODULEMODE_HWCTRL,
1790 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1792 .class = &dra7xx_ocp2scp_hwmod_class,
1793 .clkdm_name = "l3init_clkdm",
1794 .main_clk = "l4_root_clk_div",
1797 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1798 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1799 .modulemode = MODULEMODE_HWCTRL,
1810 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1811 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1812 * associated with an IP automatically leaving the driver to handle that
1813 * by itself. This does not work for PCIeSS which needs the reset lines
1814 * deasserted for the driver to start accessing registers.
1816 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1817 * lines after asserting them.
1819 static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1823 for (i = 0; i < oh->rst_lines_cnt; i++) {
1824 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1825 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1831 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1833 .reset = dra7xx_pciess_reset,
1837 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1838 { .name = "pcie", .rst_shift = 0 },
1841 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1843 .class = &dra7xx_pciess_hwmod_class,
1844 .clkdm_name = "pcie_clkdm",
1845 .rst_lines = dra7xx_pciess1_resets,
1846 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
1847 .main_clk = "l4_root_clk_div",
1850 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1851 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1852 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1853 .modulemode = MODULEMODE_SWCTRL,
1859 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1860 { .name = "pcie", .rst_shift = 1 },
1864 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1866 .class = &dra7xx_pciess_hwmod_class,
1867 .clkdm_name = "pcie_clkdm",
1868 .rst_lines = dra7xx_pciess2_resets,
1869 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
1870 .main_clk = "l4_root_clk_div",
1873 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1874 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1875 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1876 .modulemode = MODULEMODE_SWCTRL,
1886 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1887 .sysc_offs = 0x0010,
1888 .sysc_flags = SYSC_HAS_SIDLEMODE,
1889 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1891 .sysc_fields = &omap_hwmod_sysc_type2,
1894 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1896 .sysc = &dra7xx_qspi_sysc,
1900 static struct omap_hwmod dra7xx_qspi_hwmod = {
1902 .class = &dra7xx_qspi_hwmod_class,
1903 .clkdm_name = "l4per2_clkdm",
1904 .main_clk = "qspi_gfclk_div",
1907 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1908 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1909 .modulemode = MODULEMODE_SWCTRL,
1918 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1919 .sysc_offs = 0x0078,
1920 .sysc_flags = SYSC_HAS_SIDLEMODE,
1921 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1923 .sysc_fields = &omap_hwmod_sysc_type3,
1926 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1928 .sysc = &dra7xx_rtcss_sysc,
1929 .unlock = &omap_hwmod_rtc_unlock,
1930 .lock = &omap_hwmod_rtc_lock,
1934 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1936 .class = &dra7xx_rtcss_hwmod_class,
1937 .clkdm_name = "rtc_clkdm",
1938 .main_clk = "sys_32k_ck",
1941 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1942 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1943 .modulemode = MODULEMODE_SWCTRL,
1953 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1954 .sysc_offs = 0x0000,
1955 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1956 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1957 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1958 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1959 .sysc_fields = &omap_hwmod_sysc_type2,
1962 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1964 .sysc = &dra7xx_sata_sysc,
1969 static struct omap_hwmod dra7xx_sata_hwmod = {
1971 .class = &dra7xx_sata_hwmod_class,
1972 .clkdm_name = "l3init_clkdm",
1973 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1974 .main_clk = "func_48m_fclk",
1978 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1979 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1980 .modulemode = MODULEMODE_SWCTRL,
1986 * 'smartreflex' class
1990 /* The IP is not compliant to type1 / type2 scheme */
1991 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1996 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1997 .sysc_offs = 0x0038,
1998 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1999 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2001 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2004 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2005 .name = "smartreflex",
2006 .sysc = &dra7xx_smartreflex_sysc,
2010 /* smartreflex_core */
2011 /* smartreflex_core dev_attr */
2012 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2013 .sensor_voltdm_name = "core",
2016 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2017 .name = "smartreflex_core",
2018 .class = &dra7xx_smartreflex_hwmod_class,
2019 .clkdm_name = "coreaon_clkdm",
2020 .main_clk = "wkupaon_iclk_mux",
2023 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2024 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2025 .modulemode = MODULEMODE_SWCTRL,
2028 .dev_attr = &smartreflex_core_dev_attr,
2031 /* smartreflex_mpu */
2032 /* smartreflex_mpu dev_attr */
2033 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2034 .sensor_voltdm_name = "mpu",
2037 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2038 .name = "smartreflex_mpu",
2039 .class = &dra7xx_smartreflex_hwmod_class,
2040 .clkdm_name = "coreaon_clkdm",
2041 .main_clk = "wkupaon_iclk_mux",
2044 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2045 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2046 .modulemode = MODULEMODE_SWCTRL,
2049 .dev_attr = &smartreflex_mpu_dev_attr,
2057 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2059 .sysc_offs = 0x0010,
2060 .syss_offs = 0x0014,
2061 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2062 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2063 SYSS_HAS_RESET_STATUS),
2064 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2065 .sysc_fields = &omap_hwmod_sysc_type1,
2068 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2070 .sysc = &dra7xx_spinlock_sysc,
2074 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2076 .class = &dra7xx_spinlock_hwmod_class,
2077 .clkdm_name = "l4cfg_clkdm",
2078 .main_clk = "l3_iclk_div",
2081 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2082 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2090 * This class contains several variants: ['timer_1ms', 'timer_secure',
2094 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2096 .sysc_offs = 0x0010,
2097 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2098 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2099 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2101 .sysc_fields = &omap_hwmod_sysc_type2,
2104 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2106 .sysc = &dra7xx_timer_1ms_sysc,
2109 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2111 .sysc_offs = 0x0010,
2112 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2113 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2114 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2116 .sysc_fields = &omap_hwmod_sysc_type2,
2119 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2121 .sysc = &dra7xx_timer_sysc,
2125 static struct omap_hwmod dra7xx_timer1_hwmod = {
2127 .class = &dra7xx_timer_1ms_hwmod_class,
2128 .clkdm_name = "wkupaon_clkdm",
2129 .main_clk = "timer1_gfclk_mux",
2132 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2133 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2134 .modulemode = MODULEMODE_SWCTRL,
2140 static struct omap_hwmod dra7xx_timer2_hwmod = {
2142 .class = &dra7xx_timer_1ms_hwmod_class,
2143 .clkdm_name = "l4per_clkdm",
2144 .main_clk = "timer2_gfclk_mux",
2147 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2148 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2149 .modulemode = MODULEMODE_SWCTRL,
2155 static struct omap_hwmod dra7xx_timer3_hwmod = {
2157 .class = &dra7xx_timer_hwmod_class,
2158 .clkdm_name = "l4per_clkdm",
2159 .main_clk = "timer3_gfclk_mux",
2162 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2163 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2164 .modulemode = MODULEMODE_SWCTRL,
2170 static struct omap_hwmod dra7xx_timer4_hwmod = {
2172 .class = &dra7xx_timer_hwmod_class,
2173 .clkdm_name = "l4per_clkdm",
2174 .main_clk = "timer4_gfclk_mux",
2177 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2178 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2179 .modulemode = MODULEMODE_SWCTRL,
2185 static struct omap_hwmod dra7xx_timer5_hwmod = {
2187 .class = &dra7xx_timer_hwmod_class,
2188 .clkdm_name = "ipu_clkdm",
2189 .main_clk = "timer5_gfclk_mux",
2192 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2193 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2194 .modulemode = MODULEMODE_SWCTRL,
2200 static struct omap_hwmod dra7xx_timer6_hwmod = {
2202 .class = &dra7xx_timer_hwmod_class,
2203 .clkdm_name = "ipu_clkdm",
2204 .main_clk = "timer6_gfclk_mux",
2207 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2208 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2209 .modulemode = MODULEMODE_SWCTRL,
2215 static struct omap_hwmod dra7xx_timer7_hwmod = {
2217 .class = &dra7xx_timer_hwmod_class,
2218 .clkdm_name = "ipu_clkdm",
2219 .main_clk = "timer7_gfclk_mux",
2222 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2223 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2224 .modulemode = MODULEMODE_SWCTRL,
2230 static struct omap_hwmod dra7xx_timer8_hwmod = {
2232 .class = &dra7xx_timer_hwmod_class,
2233 .clkdm_name = "ipu_clkdm",
2234 .main_clk = "timer8_gfclk_mux",
2237 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2238 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2239 .modulemode = MODULEMODE_SWCTRL,
2245 static struct omap_hwmod dra7xx_timer9_hwmod = {
2247 .class = &dra7xx_timer_hwmod_class,
2248 .clkdm_name = "l4per_clkdm",
2249 .main_clk = "timer9_gfclk_mux",
2252 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2253 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2254 .modulemode = MODULEMODE_SWCTRL,
2260 static struct omap_hwmod dra7xx_timer10_hwmod = {
2262 .class = &dra7xx_timer_1ms_hwmod_class,
2263 .clkdm_name = "l4per_clkdm",
2264 .main_clk = "timer10_gfclk_mux",
2267 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2268 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2269 .modulemode = MODULEMODE_SWCTRL,
2275 static struct omap_hwmod dra7xx_timer11_hwmod = {
2277 .class = &dra7xx_timer_hwmod_class,
2278 .clkdm_name = "l4per_clkdm",
2279 .main_clk = "timer11_gfclk_mux",
2282 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2283 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2284 .modulemode = MODULEMODE_SWCTRL,
2290 static struct omap_hwmod dra7xx_timer12_hwmod = {
2292 .class = &dra7xx_timer_hwmod_class,
2293 .clkdm_name = "wkupaon_clkdm",
2294 .main_clk = "secure_32k_clk_src_ck",
2297 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2298 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2304 static struct omap_hwmod dra7xx_timer13_hwmod = {
2306 .class = &dra7xx_timer_hwmod_class,
2307 .clkdm_name = "l4per3_clkdm",
2308 .main_clk = "timer13_gfclk_mux",
2311 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2312 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2313 .modulemode = MODULEMODE_SWCTRL,
2319 static struct omap_hwmod dra7xx_timer14_hwmod = {
2321 .class = &dra7xx_timer_hwmod_class,
2322 .clkdm_name = "l4per3_clkdm",
2323 .main_clk = "timer14_gfclk_mux",
2326 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2327 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2328 .modulemode = MODULEMODE_SWCTRL,
2334 static struct omap_hwmod dra7xx_timer15_hwmod = {
2336 .class = &dra7xx_timer_hwmod_class,
2337 .clkdm_name = "l4per3_clkdm",
2338 .main_clk = "timer15_gfclk_mux",
2341 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2342 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2343 .modulemode = MODULEMODE_SWCTRL,
2349 static struct omap_hwmod dra7xx_timer16_hwmod = {
2351 .class = &dra7xx_timer_hwmod_class,
2352 .clkdm_name = "l4per3_clkdm",
2353 .main_clk = "timer16_gfclk_mux",
2356 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2357 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2358 .modulemode = MODULEMODE_SWCTRL,
2368 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2370 .sysc_offs = 0x0054,
2371 .syss_offs = 0x0058,
2372 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2373 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2374 SYSS_HAS_RESET_STATUS),
2375 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2377 .sysc_fields = &omap_hwmod_sysc_type1,
2380 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2382 .sysc = &dra7xx_uart_sysc,
2386 static struct omap_hwmod dra7xx_uart1_hwmod = {
2388 .class = &dra7xx_uart_hwmod_class,
2389 .clkdm_name = "l4per_clkdm",
2390 .main_clk = "uart1_gfclk_mux",
2391 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2394 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2395 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2396 .modulemode = MODULEMODE_SWCTRL,
2402 static struct omap_hwmod dra7xx_uart2_hwmod = {
2404 .class = &dra7xx_uart_hwmod_class,
2405 .clkdm_name = "l4per_clkdm",
2406 .main_clk = "uart2_gfclk_mux",
2407 .flags = HWMOD_SWSUP_SIDLE_ACT,
2410 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2411 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2412 .modulemode = MODULEMODE_SWCTRL,
2418 static struct omap_hwmod dra7xx_uart3_hwmod = {
2420 .class = &dra7xx_uart_hwmod_class,
2421 .clkdm_name = "l4per_clkdm",
2422 .main_clk = "uart3_gfclk_mux",
2423 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2426 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2427 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2428 .modulemode = MODULEMODE_SWCTRL,
2434 static struct omap_hwmod dra7xx_uart4_hwmod = {
2436 .class = &dra7xx_uart_hwmod_class,
2437 .clkdm_name = "l4per_clkdm",
2438 .main_clk = "uart4_gfclk_mux",
2439 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2442 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2443 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2444 .modulemode = MODULEMODE_SWCTRL,
2450 static struct omap_hwmod dra7xx_uart5_hwmod = {
2452 .class = &dra7xx_uart_hwmod_class,
2453 .clkdm_name = "l4per_clkdm",
2454 .main_clk = "uart5_gfclk_mux",
2455 .flags = HWMOD_SWSUP_SIDLE_ACT,
2458 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2459 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2460 .modulemode = MODULEMODE_SWCTRL,
2466 static struct omap_hwmod dra7xx_uart6_hwmod = {
2468 .class = &dra7xx_uart_hwmod_class,
2469 .clkdm_name = "ipu_clkdm",
2470 .main_clk = "uart6_gfclk_mux",
2471 .flags = HWMOD_SWSUP_SIDLE_ACT,
2474 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2475 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2476 .modulemode = MODULEMODE_SWCTRL,
2482 static struct omap_hwmod dra7xx_uart7_hwmod = {
2484 .class = &dra7xx_uart_hwmod_class,
2485 .clkdm_name = "l4per2_clkdm",
2486 .main_clk = "uart7_gfclk_mux",
2487 .flags = HWMOD_SWSUP_SIDLE_ACT,
2490 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2491 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2492 .modulemode = MODULEMODE_SWCTRL,
2498 static struct omap_hwmod dra7xx_uart8_hwmod = {
2500 .class = &dra7xx_uart_hwmod_class,
2501 .clkdm_name = "l4per2_clkdm",
2502 .main_clk = "uart8_gfclk_mux",
2503 .flags = HWMOD_SWSUP_SIDLE_ACT,
2506 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2507 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2508 .modulemode = MODULEMODE_SWCTRL,
2514 static struct omap_hwmod dra7xx_uart9_hwmod = {
2516 .class = &dra7xx_uart_hwmod_class,
2517 .clkdm_name = "l4per2_clkdm",
2518 .main_clk = "uart9_gfclk_mux",
2519 .flags = HWMOD_SWSUP_SIDLE_ACT,
2522 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2523 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2524 .modulemode = MODULEMODE_SWCTRL,
2530 static struct omap_hwmod dra7xx_uart10_hwmod = {
2532 .class = &dra7xx_uart_hwmod_class,
2533 .clkdm_name = "wkupaon_clkdm",
2534 .main_clk = "uart10_gfclk_mux",
2535 .flags = HWMOD_SWSUP_SIDLE_ACT,
2538 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2539 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2540 .modulemode = MODULEMODE_SWCTRL,
2546 * 'usb_otg_ss' class
2550 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2552 .sysc_offs = 0x0010,
2553 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2554 SYSC_HAS_SIDLEMODE),
2555 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2556 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2557 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2558 .sysc_fields = &omap_hwmod_sysc_type2,
2561 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2562 .name = "usb_otg_ss",
2563 .sysc = &dra7xx_usb_otg_ss_sysc,
2567 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2568 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2571 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2572 .name = "usb_otg_ss1",
2573 .class = &dra7xx_usb_otg_ss_hwmod_class,
2574 .clkdm_name = "l3init_clkdm",
2575 .main_clk = "dpll_core_h13x2_ck",
2578 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2579 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2580 .modulemode = MODULEMODE_HWCTRL,
2583 .opt_clks = usb_otg_ss1_opt_clks,
2584 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2588 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2589 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2592 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2593 .name = "usb_otg_ss2",
2594 .class = &dra7xx_usb_otg_ss_hwmod_class,
2595 .clkdm_name = "l3init_clkdm",
2596 .main_clk = "dpll_core_h13x2_ck",
2599 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2600 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2601 .modulemode = MODULEMODE_HWCTRL,
2604 .opt_clks = usb_otg_ss2_opt_clks,
2605 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2609 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2610 .name = "usb_otg_ss3",
2611 .class = &dra7xx_usb_otg_ss_hwmod_class,
2612 .clkdm_name = "l3init_clkdm",
2613 .main_clk = "dpll_core_h13x2_ck",
2616 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2617 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2618 .modulemode = MODULEMODE_HWCTRL,
2624 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2625 .name = "usb_otg_ss4",
2626 .class = &dra7xx_usb_otg_ss_hwmod_class,
2627 .clkdm_name = "l3init_clkdm",
2628 .main_clk = "dpll_core_h13x2_ck",
2631 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2632 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2633 .modulemode = MODULEMODE_HWCTRL,
2643 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2648 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2650 .class = &dra7xx_vcp_hwmod_class,
2651 .clkdm_name = "l3main1_clkdm",
2652 .main_clk = "l3_iclk_div",
2655 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2656 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2662 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2664 .class = &dra7xx_vcp_hwmod_class,
2665 .clkdm_name = "l3main1_clkdm",
2666 .main_clk = "l3_iclk_div",
2669 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2670 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2680 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2682 .sysc_offs = 0x0010,
2683 .syss_offs = 0x0014,
2684 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2685 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2686 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2688 .sysc_fields = &omap_hwmod_sysc_type1,
2691 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2693 .sysc = &dra7xx_wd_timer_sysc,
2694 .pre_shutdown = &omap2_wd_timer_disable,
2695 .reset = &omap2_wd_timer_reset,
2699 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2700 .name = "wd_timer2",
2701 .class = &dra7xx_wd_timer_hwmod_class,
2702 .clkdm_name = "wkupaon_clkdm",
2703 .main_clk = "sys_32k_ck",
2706 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2707 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2708 .modulemode = MODULEMODE_SWCTRL,
2718 /* l3_main_1 -> dmm */
2719 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2720 .master = &dra7xx_l3_main_1_hwmod,
2721 .slave = &dra7xx_dmm_hwmod,
2722 .clk = "l3_iclk_div",
2723 .user = OCP_USER_SDMA,
2726 /* l3_main_2 -> l3_instr */
2727 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2728 .master = &dra7xx_l3_main_2_hwmod,
2729 .slave = &dra7xx_l3_instr_hwmod,
2730 .clk = "l3_iclk_div",
2731 .user = OCP_USER_MPU | OCP_USER_SDMA,
2734 /* l4_cfg -> l3_main_1 */
2735 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2736 .master = &dra7xx_l4_cfg_hwmod,
2737 .slave = &dra7xx_l3_main_1_hwmod,
2738 .clk = "l3_iclk_div",
2739 .user = OCP_USER_MPU | OCP_USER_SDMA,
2742 /* mpu -> l3_main_1 */
2743 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2744 .master = &dra7xx_mpu_hwmod,
2745 .slave = &dra7xx_l3_main_1_hwmod,
2746 .clk = "l3_iclk_div",
2747 .user = OCP_USER_MPU,
2750 /* l3_main_1 -> l3_main_2 */
2751 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2752 .master = &dra7xx_l3_main_1_hwmod,
2753 .slave = &dra7xx_l3_main_2_hwmod,
2754 .clk = "l3_iclk_div",
2755 .user = OCP_USER_MPU,
2758 /* l4_cfg -> l3_main_2 */
2759 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2760 .master = &dra7xx_l4_cfg_hwmod,
2761 .slave = &dra7xx_l3_main_2_hwmod,
2762 .clk = "l3_iclk_div",
2763 .user = OCP_USER_MPU | OCP_USER_SDMA,
2766 /* l3_main_1 -> l4_cfg */
2767 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2768 .master = &dra7xx_l3_main_1_hwmod,
2769 .slave = &dra7xx_l4_cfg_hwmod,
2770 .clk = "l3_iclk_div",
2771 .user = OCP_USER_MPU | OCP_USER_SDMA,
2774 /* l3_main_1 -> l4_per1 */
2775 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2776 .master = &dra7xx_l3_main_1_hwmod,
2777 .slave = &dra7xx_l4_per1_hwmod,
2778 .clk = "l3_iclk_div",
2779 .user = OCP_USER_MPU | OCP_USER_SDMA,
2782 /* l3_main_1 -> l4_per2 */
2783 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2784 .master = &dra7xx_l3_main_1_hwmod,
2785 .slave = &dra7xx_l4_per2_hwmod,
2786 .clk = "l3_iclk_div",
2787 .user = OCP_USER_MPU | OCP_USER_SDMA,
2790 /* l3_main_1 -> l4_per3 */
2791 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2792 .master = &dra7xx_l3_main_1_hwmod,
2793 .slave = &dra7xx_l4_per3_hwmod,
2794 .clk = "l3_iclk_div",
2795 .user = OCP_USER_MPU | OCP_USER_SDMA,
2798 /* l3_main_1 -> l4_wkup */
2799 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2800 .master = &dra7xx_l3_main_1_hwmod,
2801 .slave = &dra7xx_l4_wkup_hwmod,
2802 .clk = "wkupaon_iclk_mux",
2803 .user = OCP_USER_MPU | OCP_USER_SDMA,
2806 /* l4_per2 -> atl */
2807 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2808 .master = &dra7xx_l4_per2_hwmod,
2809 .slave = &dra7xx_atl_hwmod,
2810 .clk = "l3_iclk_div",
2811 .user = OCP_USER_MPU | OCP_USER_SDMA,
2814 /* l3_main_1 -> bb2d */
2815 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2816 .master = &dra7xx_l3_main_1_hwmod,
2817 .slave = &dra7xx_bb2d_hwmod,
2818 .clk = "l3_iclk_div",
2819 .user = OCP_USER_MPU | OCP_USER_SDMA,
2822 /* l4_wkup -> counter_32k */
2823 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2824 .master = &dra7xx_l4_wkup_hwmod,
2825 .slave = &dra7xx_counter_32k_hwmod,
2826 .clk = "wkupaon_iclk_mux",
2827 .user = OCP_USER_MPU | OCP_USER_SDMA,
2830 /* l4_wkup -> ctrl_module_wkup */
2831 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2832 .master = &dra7xx_l4_wkup_hwmod,
2833 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2834 .clk = "wkupaon_iclk_mux",
2835 .user = OCP_USER_MPU | OCP_USER_SDMA,
2838 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2839 .master = &dra7xx_l4_per2_hwmod,
2840 .slave = &dra7xx_gmac_hwmod,
2841 .clk = "dpll_gmac_ck",
2842 .user = OCP_USER_MPU,
2845 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2846 .master = &dra7xx_gmac_hwmod,
2847 .slave = &dra7xx_mdio_hwmod,
2848 .user = OCP_USER_MPU,
2851 /* l4_wkup -> dcan1 */
2852 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2853 .master = &dra7xx_l4_wkup_hwmod,
2854 .slave = &dra7xx_dcan1_hwmod,
2855 .clk = "wkupaon_iclk_mux",
2856 .user = OCP_USER_MPU | OCP_USER_SDMA,
2859 /* l4_per2 -> dcan2 */
2860 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2861 .master = &dra7xx_l4_per2_hwmod,
2862 .slave = &dra7xx_dcan2_hwmod,
2863 .clk = "l3_iclk_div",
2864 .user = OCP_USER_MPU | OCP_USER_SDMA,
2867 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2869 .pa_start = 0x4a056000,
2870 .pa_end = 0x4a056fff,
2871 .flags = ADDR_TYPE_RT
2876 /* l4_cfg -> dma_system */
2877 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2878 .master = &dra7xx_l4_cfg_hwmod,
2879 .slave = &dra7xx_dma_system_hwmod,
2880 .clk = "l3_iclk_div",
2881 .addr = dra7xx_dma_system_addrs,
2882 .user = OCP_USER_MPU | OCP_USER_SDMA,
2885 /* l3_main_1 -> tpcc */
2886 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
2887 .master = &dra7xx_l3_main_1_hwmod,
2888 .slave = &dra7xx_tpcc_hwmod,
2889 .clk = "l3_iclk_div",
2890 .user = OCP_USER_MPU,
2893 /* l3_main_1 -> tptc0 */
2894 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
2895 .master = &dra7xx_l3_main_1_hwmod,
2896 .slave = &dra7xx_tptc0_hwmod,
2897 .clk = "l3_iclk_div",
2898 .user = OCP_USER_MPU,
2901 /* l3_main_1 -> tptc1 */
2902 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
2903 .master = &dra7xx_l3_main_1_hwmod,
2904 .slave = &dra7xx_tptc1_hwmod,
2905 .clk = "l3_iclk_div",
2906 .user = OCP_USER_MPU,
2909 /* l3_main_1 -> dss */
2910 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2911 .master = &dra7xx_l3_main_1_hwmod,
2912 .slave = &dra7xx_dss_hwmod,
2913 .clk = "l3_iclk_div",
2914 .user = OCP_USER_MPU | OCP_USER_SDMA,
2917 /* l3_main_1 -> dispc */
2918 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2919 .master = &dra7xx_l3_main_1_hwmod,
2920 .slave = &dra7xx_dss_dispc_hwmod,
2921 .clk = "l3_iclk_div",
2922 .user = OCP_USER_MPU | OCP_USER_SDMA,
2925 /* l3_main_1 -> dispc */
2926 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2927 .master = &dra7xx_l3_main_1_hwmod,
2928 .slave = &dra7xx_dss_hdmi_hwmod,
2929 .clk = "l3_iclk_div",
2930 .user = OCP_USER_MPU | OCP_USER_SDMA,
2933 /* l4_per2 -> mcasp1 */
2934 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
2935 .master = &dra7xx_l4_per2_hwmod,
2936 .slave = &dra7xx_mcasp1_hwmod,
2937 .clk = "l4_root_clk_div",
2938 .user = OCP_USER_MPU | OCP_USER_SDMA,
2941 /* l3_main_1 -> mcasp1 */
2942 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
2943 .master = &dra7xx_l3_main_1_hwmod,
2944 .slave = &dra7xx_mcasp1_hwmod,
2945 .clk = "l3_iclk_div",
2946 .user = OCP_USER_MPU | OCP_USER_SDMA,
2949 /* l4_per2 -> mcasp2 */
2950 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
2951 .master = &dra7xx_l4_per2_hwmod,
2952 .slave = &dra7xx_mcasp2_hwmod,
2953 .clk = "l4_root_clk_div",
2954 .user = OCP_USER_MPU | OCP_USER_SDMA,
2957 /* l3_main_1 -> mcasp2 */
2958 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
2959 .master = &dra7xx_l3_main_1_hwmod,
2960 .slave = &dra7xx_mcasp2_hwmod,
2961 .clk = "l3_iclk_div",
2962 .user = OCP_USER_MPU | OCP_USER_SDMA,
2965 /* l4_per2 -> mcasp3 */
2966 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
2967 .master = &dra7xx_l4_per2_hwmod,
2968 .slave = &dra7xx_mcasp3_hwmod,
2969 .clk = "l4_root_clk_div",
2970 .user = OCP_USER_MPU | OCP_USER_SDMA,
2973 /* l3_main_1 -> mcasp3 */
2974 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
2975 .master = &dra7xx_l3_main_1_hwmod,
2976 .slave = &dra7xx_mcasp3_hwmod,
2977 .clk = "l3_iclk_div",
2978 .user = OCP_USER_MPU | OCP_USER_SDMA,
2981 /* l4_per2 -> mcasp4 */
2982 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
2983 .master = &dra7xx_l4_per2_hwmod,
2984 .slave = &dra7xx_mcasp4_hwmod,
2985 .clk = "l4_root_clk_div",
2986 .user = OCP_USER_MPU | OCP_USER_SDMA,
2989 /* l4_per2 -> mcasp5 */
2990 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
2991 .master = &dra7xx_l4_per2_hwmod,
2992 .slave = &dra7xx_mcasp5_hwmod,
2993 .clk = "l4_root_clk_div",
2994 .user = OCP_USER_MPU | OCP_USER_SDMA,
2997 /* l4_per2 -> mcasp6 */
2998 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
2999 .master = &dra7xx_l4_per2_hwmod,
3000 .slave = &dra7xx_mcasp6_hwmod,
3001 .clk = "l4_root_clk_div",
3002 .user = OCP_USER_MPU | OCP_USER_SDMA,
3005 /* l4_per2 -> mcasp7 */
3006 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3007 .master = &dra7xx_l4_per2_hwmod,
3008 .slave = &dra7xx_mcasp7_hwmod,
3009 .clk = "l4_root_clk_div",
3010 .user = OCP_USER_MPU | OCP_USER_SDMA,
3013 /* l4_per2 -> mcasp8 */
3014 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3015 .master = &dra7xx_l4_per2_hwmod,
3016 .slave = &dra7xx_mcasp8_hwmod,
3017 .clk = "l4_root_clk_div",
3018 .user = OCP_USER_MPU | OCP_USER_SDMA,
3021 /* l4_per1 -> elm */
3022 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3023 .master = &dra7xx_l4_per1_hwmod,
3024 .slave = &dra7xx_elm_hwmod,
3025 .clk = "l3_iclk_div",
3026 .user = OCP_USER_MPU | OCP_USER_SDMA,
3029 /* l4_wkup -> gpio1 */
3030 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3031 .master = &dra7xx_l4_wkup_hwmod,
3032 .slave = &dra7xx_gpio1_hwmod,
3033 .clk = "wkupaon_iclk_mux",
3034 .user = OCP_USER_MPU | OCP_USER_SDMA,
3037 /* l4_per1 -> gpio2 */
3038 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3039 .master = &dra7xx_l4_per1_hwmod,
3040 .slave = &dra7xx_gpio2_hwmod,
3041 .clk = "l3_iclk_div",
3042 .user = OCP_USER_MPU | OCP_USER_SDMA,
3045 /* l4_per1 -> gpio3 */
3046 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3047 .master = &dra7xx_l4_per1_hwmod,
3048 .slave = &dra7xx_gpio3_hwmod,
3049 .clk = "l3_iclk_div",
3050 .user = OCP_USER_MPU | OCP_USER_SDMA,
3053 /* l4_per1 -> gpio4 */
3054 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3055 .master = &dra7xx_l4_per1_hwmod,
3056 .slave = &dra7xx_gpio4_hwmod,
3057 .clk = "l3_iclk_div",
3058 .user = OCP_USER_MPU | OCP_USER_SDMA,
3061 /* l4_per1 -> gpio5 */
3062 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3063 .master = &dra7xx_l4_per1_hwmod,
3064 .slave = &dra7xx_gpio5_hwmod,
3065 .clk = "l3_iclk_div",
3066 .user = OCP_USER_MPU | OCP_USER_SDMA,
3069 /* l4_per1 -> gpio6 */
3070 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3071 .master = &dra7xx_l4_per1_hwmod,
3072 .slave = &dra7xx_gpio6_hwmod,
3073 .clk = "l3_iclk_div",
3074 .user = OCP_USER_MPU | OCP_USER_SDMA,
3077 /* l4_per1 -> gpio7 */
3078 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3079 .master = &dra7xx_l4_per1_hwmod,
3080 .slave = &dra7xx_gpio7_hwmod,
3081 .clk = "l3_iclk_div",
3082 .user = OCP_USER_MPU | OCP_USER_SDMA,
3085 /* l4_per1 -> gpio8 */
3086 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3087 .master = &dra7xx_l4_per1_hwmod,
3088 .slave = &dra7xx_gpio8_hwmod,
3089 .clk = "l3_iclk_div",
3090 .user = OCP_USER_MPU | OCP_USER_SDMA,
3093 /* l3_main_1 -> gpmc */
3094 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3095 .master = &dra7xx_l3_main_1_hwmod,
3096 .slave = &dra7xx_gpmc_hwmod,
3097 .clk = "l3_iclk_div",
3098 .user = OCP_USER_MPU | OCP_USER_SDMA,
3101 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3103 .pa_start = 0x480b2000,
3104 .pa_end = 0x480b201f,
3105 .flags = ADDR_TYPE_RT
3110 /* l4_per1 -> hdq1w */
3111 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3112 .master = &dra7xx_l4_per1_hwmod,
3113 .slave = &dra7xx_hdq1w_hwmod,
3114 .clk = "l3_iclk_div",
3115 .addr = dra7xx_hdq1w_addrs,
3116 .user = OCP_USER_MPU | OCP_USER_SDMA,
3119 /* l4_per1 -> i2c1 */
3120 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3121 .master = &dra7xx_l4_per1_hwmod,
3122 .slave = &dra7xx_i2c1_hwmod,
3123 .clk = "l3_iclk_div",
3124 .user = OCP_USER_MPU | OCP_USER_SDMA,
3127 /* l4_per1 -> i2c2 */
3128 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3129 .master = &dra7xx_l4_per1_hwmod,
3130 .slave = &dra7xx_i2c2_hwmod,
3131 .clk = "l3_iclk_div",
3132 .user = OCP_USER_MPU | OCP_USER_SDMA,
3135 /* l4_per1 -> i2c3 */
3136 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3137 .master = &dra7xx_l4_per1_hwmod,
3138 .slave = &dra7xx_i2c3_hwmod,
3139 .clk = "l3_iclk_div",
3140 .user = OCP_USER_MPU | OCP_USER_SDMA,
3143 /* l4_per1 -> i2c4 */
3144 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3145 .master = &dra7xx_l4_per1_hwmod,
3146 .slave = &dra7xx_i2c4_hwmod,
3147 .clk = "l3_iclk_div",
3148 .user = OCP_USER_MPU | OCP_USER_SDMA,
3151 /* l4_per1 -> i2c5 */
3152 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3153 .master = &dra7xx_l4_per1_hwmod,
3154 .slave = &dra7xx_i2c5_hwmod,
3155 .clk = "l3_iclk_div",
3156 .user = OCP_USER_MPU | OCP_USER_SDMA,
3159 /* l4_cfg -> mailbox1 */
3160 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3161 .master = &dra7xx_l4_cfg_hwmod,
3162 .slave = &dra7xx_mailbox1_hwmod,
3163 .clk = "l3_iclk_div",
3164 .user = OCP_USER_MPU | OCP_USER_SDMA,
3167 /* l4_per3 -> mailbox2 */
3168 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3169 .master = &dra7xx_l4_per3_hwmod,
3170 .slave = &dra7xx_mailbox2_hwmod,
3171 .clk = "l3_iclk_div",
3172 .user = OCP_USER_MPU | OCP_USER_SDMA,
3175 /* l4_per3 -> mailbox3 */
3176 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3177 .master = &dra7xx_l4_per3_hwmod,
3178 .slave = &dra7xx_mailbox3_hwmod,
3179 .clk = "l3_iclk_div",
3180 .user = OCP_USER_MPU | OCP_USER_SDMA,
3183 /* l4_per3 -> mailbox4 */
3184 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3185 .master = &dra7xx_l4_per3_hwmod,
3186 .slave = &dra7xx_mailbox4_hwmod,
3187 .clk = "l3_iclk_div",
3188 .user = OCP_USER_MPU | OCP_USER_SDMA,
3191 /* l4_per3 -> mailbox5 */
3192 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3193 .master = &dra7xx_l4_per3_hwmod,
3194 .slave = &dra7xx_mailbox5_hwmod,
3195 .clk = "l3_iclk_div",
3196 .user = OCP_USER_MPU | OCP_USER_SDMA,
3199 /* l4_per3 -> mailbox6 */
3200 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3201 .master = &dra7xx_l4_per3_hwmod,
3202 .slave = &dra7xx_mailbox6_hwmod,
3203 .clk = "l3_iclk_div",
3204 .user = OCP_USER_MPU | OCP_USER_SDMA,
3207 /* l4_per3 -> mailbox7 */
3208 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3209 .master = &dra7xx_l4_per3_hwmod,
3210 .slave = &dra7xx_mailbox7_hwmod,
3211 .clk = "l3_iclk_div",
3212 .user = OCP_USER_MPU | OCP_USER_SDMA,
3215 /* l4_per3 -> mailbox8 */
3216 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3217 .master = &dra7xx_l4_per3_hwmod,
3218 .slave = &dra7xx_mailbox8_hwmod,
3219 .clk = "l3_iclk_div",
3220 .user = OCP_USER_MPU | OCP_USER_SDMA,
3223 /* l4_per3 -> mailbox9 */
3224 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3225 .master = &dra7xx_l4_per3_hwmod,
3226 .slave = &dra7xx_mailbox9_hwmod,
3227 .clk = "l3_iclk_div",
3228 .user = OCP_USER_MPU | OCP_USER_SDMA,
3231 /* l4_per3 -> mailbox10 */
3232 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3233 .master = &dra7xx_l4_per3_hwmod,
3234 .slave = &dra7xx_mailbox10_hwmod,
3235 .clk = "l3_iclk_div",
3236 .user = OCP_USER_MPU | OCP_USER_SDMA,
3239 /* l4_per3 -> mailbox11 */
3240 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3241 .master = &dra7xx_l4_per3_hwmod,
3242 .slave = &dra7xx_mailbox11_hwmod,
3243 .clk = "l3_iclk_div",
3244 .user = OCP_USER_MPU | OCP_USER_SDMA,
3247 /* l4_per3 -> mailbox12 */
3248 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3249 .master = &dra7xx_l4_per3_hwmod,
3250 .slave = &dra7xx_mailbox12_hwmod,
3251 .clk = "l3_iclk_div",
3252 .user = OCP_USER_MPU | OCP_USER_SDMA,
3255 /* l4_per3 -> mailbox13 */
3256 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3257 .master = &dra7xx_l4_per3_hwmod,
3258 .slave = &dra7xx_mailbox13_hwmod,
3259 .clk = "l3_iclk_div",
3260 .user = OCP_USER_MPU | OCP_USER_SDMA,
3263 /* l4_per1 -> mcspi1 */
3264 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3265 .master = &dra7xx_l4_per1_hwmod,
3266 .slave = &dra7xx_mcspi1_hwmod,
3267 .clk = "l3_iclk_div",
3268 .user = OCP_USER_MPU | OCP_USER_SDMA,
3271 /* l4_per1 -> mcspi2 */
3272 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3273 .master = &dra7xx_l4_per1_hwmod,
3274 .slave = &dra7xx_mcspi2_hwmod,
3275 .clk = "l3_iclk_div",
3276 .user = OCP_USER_MPU | OCP_USER_SDMA,
3279 /* l4_per1 -> mcspi3 */
3280 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3281 .master = &dra7xx_l4_per1_hwmod,
3282 .slave = &dra7xx_mcspi3_hwmod,
3283 .clk = "l3_iclk_div",
3284 .user = OCP_USER_MPU | OCP_USER_SDMA,
3287 /* l4_per1 -> mcspi4 */
3288 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3289 .master = &dra7xx_l4_per1_hwmod,
3290 .slave = &dra7xx_mcspi4_hwmod,
3291 .clk = "l3_iclk_div",
3292 .user = OCP_USER_MPU | OCP_USER_SDMA,
3295 /* l4_per1 -> mmc1 */
3296 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3297 .master = &dra7xx_l4_per1_hwmod,
3298 .slave = &dra7xx_mmc1_hwmod,
3299 .clk = "l3_iclk_div",
3300 .user = OCP_USER_MPU | OCP_USER_SDMA,
3303 /* l4_per1 -> mmc2 */
3304 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3305 .master = &dra7xx_l4_per1_hwmod,
3306 .slave = &dra7xx_mmc2_hwmod,
3307 .clk = "l3_iclk_div",
3308 .user = OCP_USER_MPU | OCP_USER_SDMA,
3311 /* l4_per1 -> mmc3 */
3312 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3313 .master = &dra7xx_l4_per1_hwmod,
3314 .slave = &dra7xx_mmc3_hwmod,
3315 .clk = "l3_iclk_div",
3316 .user = OCP_USER_MPU | OCP_USER_SDMA,
3319 /* l4_per1 -> mmc4 */
3320 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3321 .master = &dra7xx_l4_per1_hwmod,
3322 .slave = &dra7xx_mmc4_hwmod,
3323 .clk = "l3_iclk_div",
3324 .user = OCP_USER_MPU | OCP_USER_SDMA,
3328 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3329 .master = &dra7xx_l4_cfg_hwmod,
3330 .slave = &dra7xx_mpu_hwmod,
3331 .clk = "l3_iclk_div",
3332 .user = OCP_USER_MPU | OCP_USER_SDMA,
3335 /* l4_cfg -> ocp2scp1 */
3336 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3337 .master = &dra7xx_l4_cfg_hwmod,
3338 .slave = &dra7xx_ocp2scp1_hwmod,
3339 .clk = "l4_root_clk_div",
3340 .user = OCP_USER_MPU | OCP_USER_SDMA,
3343 /* l4_cfg -> ocp2scp3 */
3344 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3345 .master = &dra7xx_l4_cfg_hwmod,
3346 .slave = &dra7xx_ocp2scp3_hwmod,
3347 .clk = "l4_root_clk_div",
3348 .user = OCP_USER_MPU | OCP_USER_SDMA,
3351 /* l3_main_1 -> pciess1 */
3352 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3353 .master = &dra7xx_l3_main_1_hwmod,
3354 .slave = &dra7xx_pciess1_hwmod,
3355 .clk = "l3_iclk_div",
3356 .user = OCP_USER_MPU | OCP_USER_SDMA,
3359 /* l4_cfg -> pciess1 */
3360 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3361 .master = &dra7xx_l4_cfg_hwmod,
3362 .slave = &dra7xx_pciess1_hwmod,
3363 .clk = "l4_root_clk_div",
3364 .user = OCP_USER_MPU | OCP_USER_SDMA,
3367 /* l3_main_1 -> pciess2 */
3368 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3369 .master = &dra7xx_l3_main_1_hwmod,
3370 .slave = &dra7xx_pciess2_hwmod,
3371 .clk = "l3_iclk_div",
3372 .user = OCP_USER_MPU | OCP_USER_SDMA,
3375 /* l4_cfg -> pciess2 */
3376 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3377 .master = &dra7xx_l4_cfg_hwmod,
3378 .slave = &dra7xx_pciess2_hwmod,
3379 .clk = "l4_root_clk_div",
3380 .user = OCP_USER_MPU | OCP_USER_SDMA,
3383 /* l3_main_1 -> qspi */
3384 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3385 .master = &dra7xx_l3_main_1_hwmod,
3386 .slave = &dra7xx_qspi_hwmod,
3387 .clk = "l3_iclk_div",
3388 .user = OCP_USER_MPU | OCP_USER_SDMA,
3391 /* l4_per3 -> rtcss */
3392 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3393 .master = &dra7xx_l4_per3_hwmod,
3394 .slave = &dra7xx_rtcss_hwmod,
3395 .clk = "l4_root_clk_div",
3396 .user = OCP_USER_MPU | OCP_USER_SDMA,
3399 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3402 .pa_start = 0x4a141100,
3403 .pa_end = 0x4a141107,
3404 .flags = ADDR_TYPE_RT
3409 /* l4_cfg -> sata */
3410 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3411 .master = &dra7xx_l4_cfg_hwmod,
3412 .slave = &dra7xx_sata_hwmod,
3413 .clk = "l3_iclk_div",
3414 .addr = dra7xx_sata_addrs,
3415 .user = OCP_USER_MPU | OCP_USER_SDMA,
3418 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3420 .pa_start = 0x4a0dd000,
3421 .pa_end = 0x4a0dd07f,
3422 .flags = ADDR_TYPE_RT
3427 /* l4_cfg -> smartreflex_core */
3428 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3429 .master = &dra7xx_l4_cfg_hwmod,
3430 .slave = &dra7xx_smartreflex_core_hwmod,
3431 .clk = "l4_root_clk_div",
3432 .addr = dra7xx_smartreflex_core_addrs,
3433 .user = OCP_USER_MPU | OCP_USER_SDMA,
3436 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3438 .pa_start = 0x4a0d9000,
3439 .pa_end = 0x4a0d907f,
3440 .flags = ADDR_TYPE_RT
3445 /* l4_cfg -> smartreflex_mpu */
3446 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3447 .master = &dra7xx_l4_cfg_hwmod,
3448 .slave = &dra7xx_smartreflex_mpu_hwmod,
3449 .clk = "l4_root_clk_div",
3450 .addr = dra7xx_smartreflex_mpu_addrs,
3451 .user = OCP_USER_MPU | OCP_USER_SDMA,
3454 /* l4_cfg -> spinlock */
3455 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3456 .master = &dra7xx_l4_cfg_hwmod,
3457 .slave = &dra7xx_spinlock_hwmod,
3458 .clk = "l3_iclk_div",
3459 .user = OCP_USER_MPU | OCP_USER_SDMA,
3462 /* l4_wkup -> timer1 */
3463 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3464 .master = &dra7xx_l4_wkup_hwmod,
3465 .slave = &dra7xx_timer1_hwmod,
3466 .clk = "wkupaon_iclk_mux",
3467 .user = OCP_USER_MPU | OCP_USER_SDMA,
3470 /* l4_per1 -> timer2 */
3471 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3472 .master = &dra7xx_l4_per1_hwmod,
3473 .slave = &dra7xx_timer2_hwmod,
3474 .clk = "l3_iclk_div",
3475 .user = OCP_USER_MPU | OCP_USER_SDMA,
3478 /* l4_per1 -> timer3 */
3479 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3480 .master = &dra7xx_l4_per1_hwmod,
3481 .slave = &dra7xx_timer3_hwmod,
3482 .clk = "l3_iclk_div",
3483 .user = OCP_USER_MPU | OCP_USER_SDMA,
3486 /* l4_per1 -> timer4 */
3487 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3488 .master = &dra7xx_l4_per1_hwmod,
3489 .slave = &dra7xx_timer4_hwmod,
3490 .clk = "l3_iclk_div",
3491 .user = OCP_USER_MPU | OCP_USER_SDMA,
3494 /* l4_per3 -> timer5 */
3495 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3496 .master = &dra7xx_l4_per3_hwmod,
3497 .slave = &dra7xx_timer5_hwmod,
3498 .clk = "l3_iclk_div",
3499 .user = OCP_USER_MPU | OCP_USER_SDMA,
3502 /* l4_per3 -> timer6 */
3503 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3504 .master = &dra7xx_l4_per3_hwmod,
3505 .slave = &dra7xx_timer6_hwmod,
3506 .clk = "l3_iclk_div",
3507 .user = OCP_USER_MPU | OCP_USER_SDMA,
3510 /* l4_per3 -> timer7 */
3511 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3512 .master = &dra7xx_l4_per3_hwmod,
3513 .slave = &dra7xx_timer7_hwmod,
3514 .clk = "l3_iclk_div",
3515 .user = OCP_USER_MPU | OCP_USER_SDMA,
3518 /* l4_per3 -> timer8 */
3519 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3520 .master = &dra7xx_l4_per3_hwmod,
3521 .slave = &dra7xx_timer8_hwmod,
3522 .clk = "l3_iclk_div",
3523 .user = OCP_USER_MPU | OCP_USER_SDMA,
3526 /* l4_per1 -> timer9 */
3527 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3528 .master = &dra7xx_l4_per1_hwmod,
3529 .slave = &dra7xx_timer9_hwmod,
3530 .clk = "l3_iclk_div",
3531 .user = OCP_USER_MPU | OCP_USER_SDMA,
3534 /* l4_per1 -> timer10 */
3535 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3536 .master = &dra7xx_l4_per1_hwmod,
3537 .slave = &dra7xx_timer10_hwmod,
3538 .clk = "l3_iclk_div",
3539 .user = OCP_USER_MPU | OCP_USER_SDMA,
3542 /* l4_per1 -> timer11 */
3543 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3544 .master = &dra7xx_l4_per1_hwmod,
3545 .slave = &dra7xx_timer11_hwmod,
3546 .clk = "l3_iclk_div",
3547 .user = OCP_USER_MPU | OCP_USER_SDMA,
3550 /* l4_wkup -> timer12 */
3551 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3552 .master = &dra7xx_l4_wkup_hwmod,
3553 .slave = &dra7xx_timer12_hwmod,
3554 .clk = "wkupaon_iclk_mux",
3555 .user = OCP_USER_MPU | OCP_USER_SDMA,
3558 /* l4_per3 -> timer13 */
3559 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3560 .master = &dra7xx_l4_per3_hwmod,
3561 .slave = &dra7xx_timer13_hwmod,
3562 .clk = "l3_iclk_div",
3563 .user = OCP_USER_MPU | OCP_USER_SDMA,
3566 /* l4_per3 -> timer14 */
3567 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3568 .master = &dra7xx_l4_per3_hwmod,
3569 .slave = &dra7xx_timer14_hwmod,
3570 .clk = "l3_iclk_div",
3571 .user = OCP_USER_MPU | OCP_USER_SDMA,
3574 /* l4_per3 -> timer15 */
3575 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3576 .master = &dra7xx_l4_per3_hwmod,
3577 .slave = &dra7xx_timer15_hwmod,
3578 .clk = "l3_iclk_div",
3579 .user = OCP_USER_MPU | OCP_USER_SDMA,
3582 /* l4_per3 -> timer16 */
3583 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3584 .master = &dra7xx_l4_per3_hwmod,
3585 .slave = &dra7xx_timer16_hwmod,
3586 .clk = "l3_iclk_div",
3587 .user = OCP_USER_MPU | OCP_USER_SDMA,
3590 /* l4_per1 -> uart1 */
3591 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3592 .master = &dra7xx_l4_per1_hwmod,
3593 .slave = &dra7xx_uart1_hwmod,
3594 .clk = "l3_iclk_div",
3595 .user = OCP_USER_MPU | OCP_USER_SDMA,
3598 /* l4_per1 -> uart2 */
3599 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3600 .master = &dra7xx_l4_per1_hwmod,
3601 .slave = &dra7xx_uart2_hwmod,
3602 .clk = "l3_iclk_div",
3603 .user = OCP_USER_MPU | OCP_USER_SDMA,
3606 /* l4_per1 -> uart3 */
3607 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3608 .master = &dra7xx_l4_per1_hwmod,
3609 .slave = &dra7xx_uart3_hwmod,
3610 .clk = "l3_iclk_div",
3611 .user = OCP_USER_MPU | OCP_USER_SDMA,
3614 /* l4_per1 -> uart4 */
3615 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3616 .master = &dra7xx_l4_per1_hwmod,
3617 .slave = &dra7xx_uart4_hwmod,
3618 .clk = "l3_iclk_div",
3619 .user = OCP_USER_MPU | OCP_USER_SDMA,
3622 /* l4_per1 -> uart5 */
3623 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3624 .master = &dra7xx_l4_per1_hwmod,
3625 .slave = &dra7xx_uart5_hwmod,
3626 .clk = "l3_iclk_div",
3627 .user = OCP_USER_MPU | OCP_USER_SDMA,
3630 /* l4_per1 -> uart6 */
3631 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3632 .master = &dra7xx_l4_per1_hwmod,
3633 .slave = &dra7xx_uart6_hwmod,
3634 .clk = "l3_iclk_div",
3635 .user = OCP_USER_MPU | OCP_USER_SDMA,
3638 /* l4_per2 -> uart7 */
3639 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3640 .master = &dra7xx_l4_per2_hwmod,
3641 .slave = &dra7xx_uart7_hwmod,
3642 .clk = "l3_iclk_div",
3643 .user = OCP_USER_MPU | OCP_USER_SDMA,
3646 /* l4_per2 -> uart8 */
3647 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3648 .master = &dra7xx_l4_per2_hwmod,
3649 .slave = &dra7xx_uart8_hwmod,
3650 .clk = "l3_iclk_div",
3651 .user = OCP_USER_MPU | OCP_USER_SDMA,
3654 /* l4_per2 -> uart9 */
3655 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3656 .master = &dra7xx_l4_per2_hwmod,
3657 .slave = &dra7xx_uart9_hwmod,
3658 .clk = "l3_iclk_div",
3659 .user = OCP_USER_MPU | OCP_USER_SDMA,
3662 /* l4_wkup -> uart10 */
3663 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3664 .master = &dra7xx_l4_wkup_hwmod,
3665 .slave = &dra7xx_uart10_hwmod,
3666 .clk = "wkupaon_iclk_mux",
3667 .user = OCP_USER_MPU | OCP_USER_SDMA,
3670 /* l4_per3 -> usb_otg_ss1 */
3671 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3672 .master = &dra7xx_l4_per3_hwmod,
3673 .slave = &dra7xx_usb_otg_ss1_hwmod,
3674 .clk = "dpll_core_h13x2_ck",
3675 .user = OCP_USER_MPU | OCP_USER_SDMA,
3678 /* l4_per3 -> usb_otg_ss2 */
3679 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3680 .master = &dra7xx_l4_per3_hwmod,
3681 .slave = &dra7xx_usb_otg_ss2_hwmod,
3682 .clk = "dpll_core_h13x2_ck",
3683 .user = OCP_USER_MPU | OCP_USER_SDMA,
3686 /* l4_per3 -> usb_otg_ss3 */
3687 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3688 .master = &dra7xx_l4_per3_hwmod,
3689 .slave = &dra7xx_usb_otg_ss3_hwmod,
3690 .clk = "dpll_core_h13x2_ck",
3691 .user = OCP_USER_MPU | OCP_USER_SDMA,
3694 /* l4_per3 -> usb_otg_ss4 */
3695 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3696 .master = &dra7xx_l4_per3_hwmod,
3697 .slave = &dra7xx_usb_otg_ss4_hwmod,
3698 .clk = "dpll_core_h13x2_ck",
3699 .user = OCP_USER_MPU | OCP_USER_SDMA,
3702 /* l3_main_1 -> vcp1 */
3703 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3704 .master = &dra7xx_l3_main_1_hwmod,
3705 .slave = &dra7xx_vcp1_hwmod,
3706 .clk = "l3_iclk_div",
3707 .user = OCP_USER_MPU | OCP_USER_SDMA,
3710 /* l4_per2 -> vcp1 */
3711 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3712 .master = &dra7xx_l4_per2_hwmod,
3713 .slave = &dra7xx_vcp1_hwmod,
3714 .clk = "l3_iclk_div",
3715 .user = OCP_USER_MPU | OCP_USER_SDMA,
3718 /* l3_main_1 -> vcp2 */
3719 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3720 .master = &dra7xx_l3_main_1_hwmod,
3721 .slave = &dra7xx_vcp2_hwmod,
3722 .clk = "l3_iclk_div",
3723 .user = OCP_USER_MPU | OCP_USER_SDMA,
3726 /* l4_per2 -> vcp2 */
3727 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3728 .master = &dra7xx_l4_per2_hwmod,
3729 .slave = &dra7xx_vcp2_hwmod,
3730 .clk = "l3_iclk_div",
3731 .user = OCP_USER_MPU | OCP_USER_SDMA,
3734 /* l4_wkup -> wd_timer2 */
3735 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3736 .master = &dra7xx_l4_wkup_hwmod,
3737 .slave = &dra7xx_wd_timer2_hwmod,
3738 .clk = "wkupaon_iclk_mux",
3739 .user = OCP_USER_MPU | OCP_USER_SDMA,
3742 /* l4_per2 -> epwmss0 */
3743 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3744 .master = &dra7xx_l4_per2_hwmod,
3745 .slave = &dra7xx_epwmss0_hwmod,
3746 .clk = "l4_root_clk_div",
3747 .user = OCP_USER_MPU,
3750 /* l4_per2 -> epwmss1 */
3751 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3752 .master = &dra7xx_l4_per2_hwmod,
3753 .slave = &dra7xx_epwmss1_hwmod,
3754 .clk = "l4_root_clk_div",
3755 .user = OCP_USER_MPU,
3758 /* l4_per2 -> epwmss2 */
3759 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3760 .master = &dra7xx_l4_per2_hwmod,
3761 .slave = &dra7xx_epwmss2_hwmod,
3762 .clk = "l4_root_clk_div",
3763 .user = OCP_USER_MPU,
3766 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3767 &dra7xx_l3_main_1__dmm,
3768 &dra7xx_l3_main_2__l3_instr,
3769 &dra7xx_l4_cfg__l3_main_1,
3770 &dra7xx_mpu__l3_main_1,
3771 &dra7xx_l3_main_1__l3_main_2,
3772 &dra7xx_l4_cfg__l3_main_2,
3773 &dra7xx_l3_main_1__l4_cfg,
3774 &dra7xx_l3_main_1__l4_per1,
3775 &dra7xx_l3_main_1__l4_per2,
3776 &dra7xx_l3_main_1__l4_per3,
3777 &dra7xx_l3_main_1__l4_wkup,
3778 &dra7xx_l4_per2__atl,
3779 &dra7xx_l3_main_1__bb2d,
3780 &dra7xx_l4_wkup__counter_32k,
3781 &dra7xx_l4_wkup__ctrl_module_wkup,
3782 &dra7xx_l4_wkup__dcan1,
3783 &dra7xx_l4_per2__dcan2,
3784 &dra7xx_l4_per2__cpgmac0,
3785 &dra7xx_l4_per2__mcasp1,
3786 &dra7xx_l3_main_1__mcasp1,
3787 &dra7xx_l4_per2__mcasp2,
3788 &dra7xx_l3_main_1__mcasp2,
3789 &dra7xx_l4_per2__mcasp3,
3790 &dra7xx_l3_main_1__mcasp3,
3791 &dra7xx_l4_per2__mcasp4,
3792 &dra7xx_l4_per2__mcasp5,
3793 &dra7xx_l4_per2__mcasp6,
3794 &dra7xx_l4_per2__mcasp7,
3795 &dra7xx_l4_per2__mcasp8,
3797 &dra7xx_l4_cfg__dma_system,
3798 &dra7xx_l3_main_1__tpcc,
3799 &dra7xx_l3_main_1__tptc0,
3800 &dra7xx_l3_main_1__tptc1,
3801 &dra7xx_l3_main_1__dss,
3802 &dra7xx_l3_main_1__dispc,
3803 &dra7xx_l3_main_1__hdmi,
3804 &dra7xx_l4_per1__elm,
3805 &dra7xx_l4_wkup__gpio1,
3806 &dra7xx_l4_per1__gpio2,
3807 &dra7xx_l4_per1__gpio3,
3808 &dra7xx_l4_per1__gpio4,
3809 &dra7xx_l4_per1__gpio5,
3810 &dra7xx_l4_per1__gpio6,
3811 &dra7xx_l4_per1__gpio7,
3812 &dra7xx_l4_per1__gpio8,
3813 &dra7xx_l3_main_1__gpmc,
3814 &dra7xx_l4_per1__hdq1w,
3815 &dra7xx_l4_per1__i2c1,
3816 &dra7xx_l4_per1__i2c2,
3817 &dra7xx_l4_per1__i2c3,
3818 &dra7xx_l4_per1__i2c4,
3819 &dra7xx_l4_per1__i2c5,
3820 &dra7xx_l4_cfg__mailbox1,
3821 &dra7xx_l4_per3__mailbox2,
3822 &dra7xx_l4_per3__mailbox3,
3823 &dra7xx_l4_per3__mailbox4,
3824 &dra7xx_l4_per3__mailbox5,
3825 &dra7xx_l4_per3__mailbox6,
3826 &dra7xx_l4_per3__mailbox7,
3827 &dra7xx_l4_per3__mailbox8,
3828 &dra7xx_l4_per3__mailbox9,
3829 &dra7xx_l4_per3__mailbox10,
3830 &dra7xx_l4_per3__mailbox11,
3831 &dra7xx_l4_per3__mailbox12,
3832 &dra7xx_l4_per3__mailbox13,
3833 &dra7xx_l4_per1__mcspi1,
3834 &dra7xx_l4_per1__mcspi2,
3835 &dra7xx_l4_per1__mcspi3,
3836 &dra7xx_l4_per1__mcspi4,
3837 &dra7xx_l4_per1__mmc1,
3838 &dra7xx_l4_per1__mmc2,
3839 &dra7xx_l4_per1__mmc3,
3840 &dra7xx_l4_per1__mmc4,
3841 &dra7xx_l4_cfg__mpu,
3842 &dra7xx_l4_cfg__ocp2scp1,
3843 &dra7xx_l4_cfg__ocp2scp3,
3844 &dra7xx_l3_main_1__pciess1,
3845 &dra7xx_l4_cfg__pciess1,
3846 &dra7xx_l3_main_1__pciess2,
3847 &dra7xx_l4_cfg__pciess2,
3848 &dra7xx_l3_main_1__qspi,
3849 &dra7xx_l4_per3__rtcss,
3850 &dra7xx_l4_cfg__sata,
3851 &dra7xx_l4_cfg__smartreflex_core,
3852 &dra7xx_l4_cfg__smartreflex_mpu,
3853 &dra7xx_l4_cfg__spinlock,
3854 &dra7xx_l4_wkup__timer1,
3855 &dra7xx_l4_per1__timer2,
3856 &dra7xx_l4_per1__timer3,
3857 &dra7xx_l4_per1__timer4,
3858 &dra7xx_l4_per3__timer5,
3859 &dra7xx_l4_per3__timer6,
3860 &dra7xx_l4_per3__timer7,
3861 &dra7xx_l4_per3__timer8,
3862 &dra7xx_l4_per1__timer9,
3863 &dra7xx_l4_per1__timer10,
3864 &dra7xx_l4_per1__timer11,
3865 &dra7xx_l4_per3__timer13,
3866 &dra7xx_l4_per3__timer14,
3867 &dra7xx_l4_per3__timer15,
3868 &dra7xx_l4_per3__timer16,
3869 &dra7xx_l4_per1__uart1,
3870 &dra7xx_l4_per1__uart2,
3871 &dra7xx_l4_per1__uart3,
3872 &dra7xx_l4_per1__uart4,
3873 &dra7xx_l4_per1__uart5,
3874 &dra7xx_l4_per1__uart6,
3875 &dra7xx_l4_per2__uart7,
3876 &dra7xx_l4_per2__uart8,
3877 &dra7xx_l4_per2__uart9,
3878 &dra7xx_l4_wkup__uart10,
3879 &dra7xx_l4_per3__usb_otg_ss1,
3880 &dra7xx_l4_per3__usb_otg_ss2,
3881 &dra7xx_l4_per3__usb_otg_ss3,
3882 &dra7xx_l3_main_1__vcp1,
3883 &dra7xx_l4_per2__vcp1,
3884 &dra7xx_l3_main_1__vcp2,
3885 &dra7xx_l4_per2__vcp2,
3886 &dra7xx_l4_wkup__wd_timer2,
3887 &dra7xx_l4_per2__epwmss0,
3888 &dra7xx_l4_per2__epwmss1,
3889 &dra7xx_l4_per2__epwmss2,
3893 /* GP-only hwmod links */
3894 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
3895 &dra7xx_l4_wkup__timer12,
3899 /* SoC variant specific hwmod links */
3900 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3901 &dra7xx_l4_per3__usb_otg_ss4,
3905 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3909 int __init dra7xx_hwmod_init(void)
3914 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3916 if (!ret && soc_is_dra74x())
3917 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3918 else if (!ret && soc_is_dra72x())
3919 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3921 if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
3922 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);