1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hardware modules present on the OMAP44xx chips
5 * Copyright (C) 2009-2012 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 * Note that this file is currently not in sync with autogeneration scripts.
17 * The above note to be removed, once it is synced up.
22 #include "omap_hwmod.h"
23 #include "omap_hwmod_common_data.h"
27 #include "prm-regbits-44xx.h"
29 /* Base offset for all OMAP4 interrupts external to MPUSS */
30 #define OMAP44XX_IRQ_GIC_START 32
40 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
45 static struct omap_hwmod omap44xx_dmm_hwmod = {
47 .class = &omap44xx_dmm_hwmod_class,
48 .clkdm_name = "l3_emif_clkdm",
51 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
52 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
59 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
61 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
66 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
68 .class = &omap44xx_l3_hwmod_class,
69 .clkdm_name = "l3_instr_clkdm",
72 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
73 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
74 .modulemode = MODULEMODE_HWCTRL,
80 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
82 .class = &omap44xx_l3_hwmod_class,
83 .clkdm_name = "l3_1_clkdm",
86 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
87 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
93 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
95 .class = &omap44xx_l3_hwmod_class,
96 .clkdm_name = "l3_2_clkdm",
99 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
100 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
106 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
108 .class = &omap44xx_l3_hwmod_class,
109 .clkdm_name = "l3_instr_clkdm",
112 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
113 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
114 .modulemode = MODULEMODE_HWCTRL,
121 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
123 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
128 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
130 .class = &omap44xx_l4_hwmod_class,
131 .clkdm_name = "l4_cfg_clkdm",
134 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
135 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
141 static struct omap_hwmod omap44xx_l4_per_hwmod = {
143 .class = &omap44xx_l4_hwmod_class,
144 .clkdm_name = "l4_per_clkdm",
147 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
148 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
154 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
156 .class = &omap44xx_l4_hwmod_class,
157 .clkdm_name = "l4_wkup_clkdm",
160 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
161 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
168 * instance(s): mpu_private
170 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
175 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
176 .name = "mpu_private",
177 .class = &omap44xx_mpu_bus_hwmod_class,
178 .clkdm_name = "mpuss_clkdm",
181 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
188 * instance(s): ocp_wp_noc
190 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
191 .name = "ocp_wp_noc",
195 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
196 .name = "ocp_wp_noc",
197 .class = &omap44xx_ocp_wp_noc_hwmod_class,
198 .clkdm_name = "l3_instr_clkdm",
201 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
202 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
203 .modulemode = MODULEMODE_HWCTRL,
209 * Modules omap_hwmod structures
211 * The following IPs are excluded for the moment because:
212 * - They do not need an explicit SW control using omap_hwmod API.
213 * - They still need to be validated with the driver
214 * properly adapted to omap_hwmod / omap_device
220 * 'ctrl_module' class
221 * attila core control module + core pad control module + wkup pad control
222 * module + attila wkup control module
225 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
228 .sysc_flags = SYSC_HAS_SIDLEMODE,
229 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
231 .sysc_fields = &omap_hwmod_sysc_type2,
234 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
235 .name = "ctrl_module",
236 .sysc = &omap44xx_ctrl_module_sysc,
239 /* ctrl_module_core */
240 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
241 .name = "ctrl_module_core",
242 .class = &omap44xx_ctrl_module_hwmod_class,
243 .clkdm_name = "l4_cfg_clkdm",
246 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
251 /* ctrl_module_pad_core */
252 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
253 .name = "ctrl_module_pad_core",
254 .class = &omap44xx_ctrl_module_hwmod_class,
255 .clkdm_name = "l4_cfg_clkdm",
258 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
263 /* ctrl_module_wkup */
264 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
265 .name = "ctrl_module_wkup",
266 .class = &omap44xx_ctrl_module_hwmod_class,
267 .clkdm_name = "l4_wkup_clkdm",
270 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
275 /* ctrl_module_pad_wkup */
276 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
277 .name = "ctrl_module_pad_wkup",
278 .class = &omap44xx_ctrl_module_hwmod_class,
279 .clkdm_name = "l4_wkup_clkdm",
282 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
289 * debug and emulation sub system
292 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
297 static struct omap_hwmod omap44xx_debugss_hwmod = {
299 .class = &omap44xx_debugss_hwmod_class,
300 .clkdm_name = "emu_sys_clkdm",
301 .main_clk = "trace_clk_div_ck",
304 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
305 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
312 * external memory interface no1
315 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
319 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
321 .sysc = &omap44xx_emif_sysc,
325 static struct omap_hwmod omap44xx_emif1_hwmod = {
327 .class = &omap44xx_emif_hwmod_class,
328 .clkdm_name = "l3_emif_clkdm",
329 .flags = HWMOD_INIT_NO_IDLE,
330 .main_clk = "ddrphy_ck",
333 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
334 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
335 .modulemode = MODULEMODE_HWCTRL,
341 static struct omap_hwmod omap44xx_emif2_hwmod = {
343 .class = &omap44xx_emif_hwmod_class,
344 .clkdm_name = "l3_emif_clkdm",
345 .flags = HWMOD_INIT_NO_IDLE,
346 .main_clk = "ddrphy_ck",
349 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
350 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
351 .modulemode = MODULEMODE_HWCTRL,
358 * general purpose memory controller
361 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
365 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
366 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
367 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
368 .sysc_fields = &omap_hwmod_sysc_type1,
371 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
373 .sysc = &omap44xx_gpmc_sysc,
377 static struct omap_hwmod omap44xx_gpmc_hwmod = {
379 .class = &omap44xx_gpmc_hwmod_class,
380 .clkdm_name = "l3_2_clkdm",
381 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
382 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
385 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
386 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
387 .modulemode = MODULEMODE_HWCTRL,
394 * external images sensor pixel data processor
397 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
401 * ISS needs 100 OCP clk cycles delay after a softreset before
402 * accessing sysconfig again.
403 * The lowest frequency at the moment for L3 bus is 100 MHz, so
404 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
406 * TODO: Indicate errata when available.
409 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
410 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
411 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
412 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
413 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
414 .sysc_fields = &omap_hwmod_sysc_type2,
417 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
419 .sysc = &omap44xx_iss_sysc,
423 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
424 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
427 static struct omap_hwmod omap44xx_iss_hwmod = {
429 .class = &omap44xx_iss_hwmod_class,
430 .clkdm_name = "iss_clkdm",
431 .main_clk = "ducati_clk_mux_ck",
434 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
435 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
436 .modulemode = MODULEMODE_SWCTRL,
439 .opt_clks = iss_opt_clks,
440 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
445 * multi-standard video encoder/decoder hardware accelerator
448 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
453 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
454 { .name = "seq0", .rst_shift = 0 },
455 { .name = "seq1", .rst_shift = 1 },
456 { .name = "logic", .rst_shift = 2 },
459 static struct omap_hwmod omap44xx_iva_hwmod = {
461 .class = &omap44xx_iva_hwmod_class,
462 .clkdm_name = "ivahd_clkdm",
463 .rst_lines = omap44xx_iva_resets,
464 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
465 .main_clk = "dpll_iva_m5x2_ck",
468 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
469 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
470 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
471 .modulemode = MODULEMODE_HWCTRL,
481 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
486 static struct omap_hwmod omap44xx_mpu_hwmod = {
488 .class = &omap44xx_mpu_hwmod_class,
489 .clkdm_name = "mpuss_clkdm",
490 .flags = HWMOD_INIT_NO_IDLE,
491 .main_clk = "dpll_mpu_m2_ck",
494 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
495 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
502 * top-level core on-chip ram
505 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
510 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
512 .class = &omap44xx_ocmc_ram_hwmod_class,
513 .clkdm_name = "l3_2_clkdm",
516 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
517 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
525 * power and reset manager (part of the prcm infrastructure) + clock manager 2
526 * + clock manager 1 (in always on power domain) + local prm in mpu
529 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
534 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
536 .class = &omap44xx_prcm_hwmod_class,
537 .clkdm_name = "l4_wkup_clkdm",
538 .flags = HWMOD_NO_IDLEST,
541 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
547 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
548 .name = "cm_core_aon",
549 .class = &omap44xx_prcm_hwmod_class,
550 .flags = HWMOD_NO_IDLEST,
553 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
559 static struct omap_hwmod omap44xx_cm_core_hwmod = {
561 .class = &omap44xx_prcm_hwmod_class,
562 .flags = HWMOD_NO_IDLEST,
565 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
571 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
572 { .name = "rst_global_warm_sw", .rst_shift = 0 },
573 { .name = "rst_global_cold_sw", .rst_shift = 1 },
576 static struct omap_hwmod omap44xx_prm_hwmod = {
578 .class = &omap44xx_prcm_hwmod_class,
579 .rst_lines = omap44xx_prm_resets,
580 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
585 * system clock and reset manager
588 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
593 static struct omap_hwmod omap44xx_scrm_hwmod = {
595 .class = &omap44xx_scrm_hwmod_class,
596 .clkdm_name = "l4_wkup_clkdm",
599 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
606 * shared level 2 memory interface
609 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
614 static struct omap_hwmod omap44xx_sl2if_hwmod = {
616 .class = &omap44xx_sl2if_hwmod_class,
617 .clkdm_name = "ivahd_clkdm",
620 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
621 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
622 .modulemode = MODULEMODE_HWCTRL,
631 /* l3_main_1 -> dmm */
632 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
633 .master = &omap44xx_l3_main_1_hwmod,
634 .slave = &omap44xx_dmm_hwmod,
636 .user = OCP_USER_SDMA,
640 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
641 .master = &omap44xx_mpu_hwmod,
642 .slave = &omap44xx_dmm_hwmod,
644 .user = OCP_USER_MPU,
647 /* iva -> l3_instr */
648 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
649 .master = &omap44xx_iva_hwmod,
650 .slave = &omap44xx_l3_instr_hwmod,
652 .user = OCP_USER_MPU | OCP_USER_SDMA,
655 /* l3_main_3 -> l3_instr */
656 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
657 .master = &omap44xx_l3_main_3_hwmod,
658 .slave = &omap44xx_l3_instr_hwmod,
660 .user = OCP_USER_MPU | OCP_USER_SDMA,
663 /* ocp_wp_noc -> l3_instr */
664 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
665 .master = &omap44xx_ocp_wp_noc_hwmod,
666 .slave = &omap44xx_l3_instr_hwmod,
668 .user = OCP_USER_MPU | OCP_USER_SDMA,
671 /* l3_main_2 -> l3_main_1 */
672 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
673 .master = &omap44xx_l3_main_2_hwmod,
674 .slave = &omap44xx_l3_main_1_hwmod,
676 .user = OCP_USER_MPU | OCP_USER_SDMA,
679 /* l4_cfg -> l3_main_1 */
680 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
681 .master = &omap44xx_l4_cfg_hwmod,
682 .slave = &omap44xx_l3_main_1_hwmod,
684 .user = OCP_USER_MPU | OCP_USER_SDMA,
687 /* mpu -> l3_main_1 */
688 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
689 .master = &omap44xx_mpu_hwmod,
690 .slave = &omap44xx_l3_main_1_hwmod,
692 .user = OCP_USER_MPU,
695 /* debugss -> l3_main_2 */
696 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
697 .master = &omap44xx_debugss_hwmod,
698 .slave = &omap44xx_l3_main_2_hwmod,
699 .clk = "dbgclk_mux_ck",
700 .user = OCP_USER_MPU | OCP_USER_SDMA,
703 /* iss -> l3_main_2 */
704 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
705 .master = &omap44xx_iss_hwmod,
706 .slave = &omap44xx_l3_main_2_hwmod,
708 .user = OCP_USER_MPU | OCP_USER_SDMA,
711 /* iva -> l3_main_2 */
712 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
713 .master = &omap44xx_iva_hwmod,
714 .slave = &omap44xx_l3_main_2_hwmod,
716 .user = OCP_USER_MPU | OCP_USER_SDMA,
719 /* l3_main_1 -> l3_main_2 */
720 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
721 .master = &omap44xx_l3_main_1_hwmod,
722 .slave = &omap44xx_l3_main_2_hwmod,
724 .user = OCP_USER_MPU,
727 /* l4_cfg -> l3_main_2 */
728 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
729 .master = &omap44xx_l4_cfg_hwmod,
730 .slave = &omap44xx_l3_main_2_hwmod,
732 .user = OCP_USER_MPU | OCP_USER_SDMA,
735 /* l3_main_1 -> l3_main_3 */
736 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
737 .master = &omap44xx_l3_main_1_hwmod,
738 .slave = &omap44xx_l3_main_3_hwmod,
740 .user = OCP_USER_MPU,
743 /* l3_main_2 -> l3_main_3 */
744 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
745 .master = &omap44xx_l3_main_2_hwmod,
746 .slave = &omap44xx_l3_main_3_hwmod,
748 .user = OCP_USER_MPU | OCP_USER_SDMA,
751 /* l4_cfg -> l3_main_3 */
752 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
753 .master = &omap44xx_l4_cfg_hwmod,
754 .slave = &omap44xx_l3_main_3_hwmod,
756 .user = OCP_USER_MPU | OCP_USER_SDMA,
759 /* l3_main_1 -> l4_cfg */
760 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
761 .master = &omap44xx_l3_main_1_hwmod,
762 .slave = &omap44xx_l4_cfg_hwmod,
764 .user = OCP_USER_MPU | OCP_USER_SDMA,
767 /* l3_main_2 -> l4_per */
768 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
769 .master = &omap44xx_l3_main_2_hwmod,
770 .slave = &omap44xx_l4_per_hwmod,
772 .user = OCP_USER_MPU | OCP_USER_SDMA,
775 /* l4_cfg -> l4_wkup */
776 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
777 .master = &omap44xx_l4_cfg_hwmod,
778 .slave = &omap44xx_l4_wkup_hwmod,
780 .user = OCP_USER_MPU | OCP_USER_SDMA,
783 /* mpu -> mpu_private */
784 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
785 .master = &omap44xx_mpu_hwmod,
786 .slave = &omap44xx_mpu_private_hwmod,
788 .user = OCP_USER_MPU | OCP_USER_SDMA,
791 /* l4_cfg -> ocp_wp_noc */
792 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
793 .master = &omap44xx_l4_cfg_hwmod,
794 .slave = &omap44xx_ocp_wp_noc_hwmod,
796 .user = OCP_USER_MPU | OCP_USER_SDMA,
799 /* l4_cfg -> ctrl_module_core */
800 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
801 .master = &omap44xx_l4_cfg_hwmod,
802 .slave = &omap44xx_ctrl_module_core_hwmod,
804 .user = OCP_USER_MPU | OCP_USER_SDMA,
807 /* l4_cfg -> ctrl_module_pad_core */
808 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
809 .master = &omap44xx_l4_cfg_hwmod,
810 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
812 .user = OCP_USER_MPU | OCP_USER_SDMA,
815 /* l4_wkup -> ctrl_module_wkup */
816 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
817 .master = &omap44xx_l4_wkup_hwmod,
818 .slave = &omap44xx_ctrl_module_wkup_hwmod,
819 .clk = "l4_wkup_clk_mux_ck",
820 .user = OCP_USER_MPU | OCP_USER_SDMA,
823 /* l4_wkup -> ctrl_module_pad_wkup */
824 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
825 .master = &omap44xx_l4_wkup_hwmod,
826 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
827 .clk = "l4_wkup_clk_mux_ck",
828 .user = OCP_USER_MPU | OCP_USER_SDMA,
831 /* l3_instr -> debugss */
832 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
833 .master = &omap44xx_l3_instr_hwmod,
834 .slave = &omap44xx_debugss_hwmod,
836 .user = OCP_USER_MPU | OCP_USER_SDMA,
839 /* l3_main_2 -> gpmc */
840 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
841 .master = &omap44xx_l3_main_2_hwmod,
842 .slave = &omap44xx_gpmc_hwmod,
844 .user = OCP_USER_MPU | OCP_USER_SDMA,
847 /* l3_main_2 -> iss */
848 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
849 .master = &omap44xx_l3_main_2_hwmod,
850 .slave = &omap44xx_iss_hwmod,
852 .user = OCP_USER_MPU | OCP_USER_SDMA,
856 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
857 .master = &omap44xx_iva_hwmod,
858 .slave = &omap44xx_sl2if_hwmod,
859 .clk = "dpll_iva_m5x2_ck",
860 .user = OCP_USER_IVA,
863 /* l3_main_2 -> iva */
864 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
865 .master = &omap44xx_l3_main_2_hwmod,
866 .slave = &omap44xx_iva_hwmod,
868 .user = OCP_USER_MPU,
871 /* l3_main_2 -> ocmc_ram */
872 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
873 .master = &omap44xx_l3_main_2_hwmod,
874 .slave = &omap44xx_ocmc_ram_hwmod,
876 .user = OCP_USER_MPU | OCP_USER_SDMA,
879 /* mpu_private -> prcm_mpu */
880 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
881 .master = &omap44xx_mpu_private_hwmod,
882 .slave = &omap44xx_prcm_mpu_hwmod,
884 .user = OCP_USER_MPU | OCP_USER_SDMA,
887 /* l4_wkup -> cm_core_aon */
888 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
889 .master = &omap44xx_l4_wkup_hwmod,
890 .slave = &omap44xx_cm_core_aon_hwmod,
891 .clk = "l4_wkup_clk_mux_ck",
892 .user = OCP_USER_MPU | OCP_USER_SDMA,
895 /* l4_cfg -> cm_core */
896 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
897 .master = &omap44xx_l4_cfg_hwmod,
898 .slave = &omap44xx_cm_core_hwmod,
900 .user = OCP_USER_MPU | OCP_USER_SDMA,
904 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
905 .master = &omap44xx_l4_wkup_hwmod,
906 .slave = &omap44xx_prm_hwmod,
907 .clk = "l4_wkup_clk_mux_ck",
908 .user = OCP_USER_MPU | OCP_USER_SDMA,
911 /* l4_wkup -> scrm */
912 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
913 .master = &omap44xx_l4_wkup_hwmod,
914 .slave = &omap44xx_scrm_hwmod,
915 .clk = "l4_wkup_clk_mux_ck",
916 .user = OCP_USER_MPU | OCP_USER_SDMA,
919 /* l3_main_2 -> sl2if */
920 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
921 .master = &omap44xx_l3_main_2_hwmod,
922 .slave = &omap44xx_sl2if_hwmod,
924 .user = OCP_USER_MPU | OCP_USER_SDMA,
928 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
929 .master = &omap44xx_mpu_hwmod,
930 .slave = &omap44xx_emif1_hwmod,
932 .user = OCP_USER_MPU | OCP_USER_SDMA,
936 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
937 .master = &omap44xx_mpu_hwmod,
938 .slave = &omap44xx_emif2_hwmod,
940 .user = OCP_USER_MPU | OCP_USER_SDMA,
943 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
944 &omap44xx_l3_main_1__dmm,
946 &omap44xx_iva__l3_instr,
947 &omap44xx_l3_main_3__l3_instr,
948 &omap44xx_ocp_wp_noc__l3_instr,
949 &omap44xx_l3_main_2__l3_main_1,
950 &omap44xx_l4_cfg__l3_main_1,
951 &omap44xx_mpu__l3_main_1,
952 &omap44xx_debugss__l3_main_2,
953 &omap44xx_iss__l3_main_2,
954 &omap44xx_iva__l3_main_2,
955 &omap44xx_l3_main_1__l3_main_2,
956 &omap44xx_l4_cfg__l3_main_2,
957 &omap44xx_l3_main_1__l3_main_3,
958 &omap44xx_l3_main_2__l3_main_3,
959 &omap44xx_l4_cfg__l3_main_3,
960 &omap44xx_l3_main_1__l4_cfg,
961 &omap44xx_l3_main_2__l4_per,
962 &omap44xx_l4_cfg__l4_wkup,
963 &omap44xx_mpu__mpu_private,
964 &omap44xx_l4_cfg__ocp_wp_noc,
965 &omap44xx_l4_cfg__ctrl_module_core,
966 &omap44xx_l4_cfg__ctrl_module_pad_core,
967 &omap44xx_l4_wkup__ctrl_module_wkup,
968 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
969 &omap44xx_l3_instr__debugss,
970 &omap44xx_l3_main_2__gpmc,
971 &omap44xx_l3_main_2__iss,
972 /* &omap44xx_iva__sl2if, */
973 &omap44xx_l3_main_2__iva,
974 &omap44xx_l3_main_2__ocmc_ram,
975 &omap44xx_mpu_private__prcm_mpu,
976 &omap44xx_l4_wkup__cm_core_aon,
977 &omap44xx_l4_cfg__cm_core,
978 &omap44xx_l4_wkup__prm,
979 &omap44xx_l4_wkup__scrm,
980 /* &omap44xx_l3_main_2__sl2if, */
981 &omap44xx_mpu__emif1,
982 &omap44xx_mpu__emif2,
986 int __init omap44xx_hwmod_init(void)
989 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);