3 * Copyright (C) 2013 Texas Instruments Incorporated
5 * Hwmod common for AM335x and AM43x
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/types.h>
19 #include "omap_hwmod.h"
23 #include "omap_hwmod_33xx_43xx_common_data.h"
27 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
28 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
29 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
30 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
34 * instance(s): l3_main, l3_s, l3_instr
36 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
40 struct omap_hwmod am33xx_l3_main_hwmod = {
42 .class = &am33xx_l3_hwmod_class,
43 .clkdm_name = "l3_clkdm",
44 .flags = HWMOD_INIT_NO_IDLE,
45 .main_clk = "l3_gclk",
48 .modulemode = MODULEMODE_SWCTRL,
54 struct omap_hwmod am33xx_l3_s_hwmod = {
56 .class = &am33xx_l3_hwmod_class,
57 .clkdm_name = "l3s_clkdm",
61 struct omap_hwmod am33xx_l3_instr_hwmod = {
63 .class = &am33xx_l3_hwmod_class,
64 .clkdm_name = "l3_clkdm",
65 .flags = HWMOD_INIT_NO_IDLE,
66 .main_clk = "l3_gclk",
69 .modulemode = MODULEMODE_SWCTRL,
76 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
78 struct omap_hwmod_class am33xx_l4_hwmod_class = {
83 struct omap_hwmod am33xx_l4_ls_hwmod = {
85 .class = &am33xx_l4_hwmod_class,
86 .clkdm_name = "l4ls_clkdm",
87 .flags = HWMOD_INIT_NO_IDLE,
88 .main_clk = "l4ls_gclk",
91 .modulemode = MODULEMODE_SWCTRL,
97 struct omap_hwmod am33xx_l4_wkup_hwmod = {
99 .class = &am33xx_l4_hwmod_class,
100 .clkdm_name = "l4_wkup_clkdm",
101 .flags = HWMOD_INIT_NO_IDLE,
104 .modulemode = MODULEMODE_SWCTRL,
112 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
116 struct omap_hwmod am33xx_mpu_hwmod = {
118 .class = &am33xx_mpu_hwmod_class,
119 .clkdm_name = "mpu_clkdm",
120 .flags = HWMOD_INIT_NO_IDLE,
121 .main_clk = "dpll_mpu_m2_ck",
124 .modulemode = MODULEMODE_SWCTRL,
131 * Wakeup controller sub-system under wakeup domain
133 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
139 * Programmable Real-Time Unit and Industrial Communication Subsystem
141 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
145 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
146 { .name = "pruss", .rst_shift = 1 },
150 /* Pseudo hwmod for reset control purpose only */
151 struct omap_hwmod am33xx_pruss_hwmod = {
153 .class = &am33xx_pruss_hwmod_class,
154 .clkdm_name = "pruss_ocp_clkdm",
155 .main_clk = "pruss_ocp_gclk",
158 .modulemode = MODULEMODE_SWCTRL,
161 .rst_lines = am33xx_pruss_resets,
162 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
166 /* Pseudo hwmod for reset control purpose only */
167 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
171 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
172 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
175 struct omap_hwmod am33xx_gfx_hwmod = {
177 .class = &am33xx_gfx_hwmod_class,
178 .clkdm_name = "gfx_l3_clkdm",
179 .main_clk = "gfx_fck_div_ck",
182 .modulemode = MODULEMODE_SWCTRL,
185 .rst_lines = am33xx_gfx_resets,
186 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
191 * power and reset manager (whole prcm infrastructure)
193 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
198 struct omap_hwmod am33xx_prcm_hwmod = {
200 .class = &am33xx_prcm_hwmod_class,
201 .clkdm_name = "l4_wkup_clkdm",
208 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
212 struct omap_hwmod_class am33xx_emif_hwmod_class = {
214 .sysc = &am33xx_emif_sysc,
220 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
224 .sysc_flags = SYSS_HAS_RESET_STATUS,
227 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
229 .sysc = &am33xx_aes0_sysc,
232 struct omap_hwmod am33xx_aes0_hwmod = {
234 .class = &am33xx_aes0_hwmod_class,
235 .clkdm_name = "l3_clkdm",
236 .main_clk = "aes0_fck",
239 .modulemode = MODULEMODE_SWCTRL,
244 /* sha0 HIB2 (the 'P' (public) device) */
245 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
249 .sysc_flags = SYSS_HAS_RESET_STATUS,
252 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
254 .sysc = &am33xx_sha0_sysc,
257 struct omap_hwmod am33xx_sha0_hwmod = {
259 .class = &am33xx_sha0_hwmod_class,
260 .clkdm_name = "l3_clkdm",
261 .main_clk = "l3_gclk",
264 .modulemode = MODULEMODE_SWCTRL,
270 static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
273 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
274 .idlemodes = SIDLE_FORCE | SIDLE_NO,
275 .sysc_fields = &omap_hwmod_sysc_type1,
278 static struct omap_hwmod_class am33xx_rng_hwmod_class = {
280 .sysc = &am33xx_rng_sysc,
283 struct omap_hwmod am33xx_rng_hwmod = {
285 .class = &am33xx_rng_hwmod_class,
286 .clkdm_name = "l4ls_clkdm",
287 .flags = HWMOD_SWSUP_SIDLE,
288 .main_clk = "rng_fck",
291 .modulemode = MODULEMODE_SWCTRL,
297 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
301 struct omap_hwmod am33xx_ocmcram_hwmod = {
303 .class = &am33xx_ocmcram_hwmod_class,
304 .clkdm_name = "l3_clkdm",
305 .flags = HWMOD_INIT_NO_IDLE,
306 .main_clk = "l3_gclk",
309 .modulemode = MODULEMODE_SWCTRL,
314 /* 'smartreflex' class */
315 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
316 .name = "smartreflex",
320 struct omap_hwmod am33xx_smartreflex0_hwmod = {
321 .name = "smartreflex0",
322 .class = &am33xx_smartreflex_hwmod_class,
323 .clkdm_name = "l4_wkup_clkdm",
324 .main_clk = "smartreflex0_fck",
327 .modulemode = MODULEMODE_SWCTRL,
333 struct omap_hwmod am33xx_smartreflex1_hwmod = {
334 .name = "smartreflex1",
335 .class = &am33xx_smartreflex_hwmod_class,
336 .clkdm_name = "l4_wkup_clkdm",
337 .main_clk = "smartreflex1_fck",
340 .modulemode = MODULEMODE_SWCTRL,
346 * 'control' module class
348 struct omap_hwmod_class am33xx_control_hwmod_class = {
355 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
360 struct omap_hwmod am33xx_dcan0_hwmod = {
362 .class = &am33xx_dcan_hwmod_class,
363 .clkdm_name = "l4ls_clkdm",
364 .main_clk = "dcan0_fck",
367 .modulemode = MODULEMODE_SWCTRL,
373 struct omap_hwmod am33xx_dcan1_hwmod = {
375 .class = &am33xx_dcan_hwmod_class,
376 .clkdm_name = "l4ls_clkdm",
377 .main_clk = "dcan1_fck",
380 .modulemode = MODULEMODE_SWCTRL,
386 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
390 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
391 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
392 SYSS_HAS_RESET_STATUS),
393 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
394 .sysc_fields = &omap_hwmod_sysc_type1,
397 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
399 .sysc = &am33xx_elm_sysc,
402 struct omap_hwmod am33xx_elm_hwmod = {
404 .class = &am33xx_elm_hwmod_class,
405 .clkdm_name = "l4ls_clkdm",
406 .main_clk = "l4ls_gclk",
409 .modulemode = MODULEMODE_SWCTRL,
415 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
418 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
419 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
420 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
421 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
422 .sysc_fields = &omap_hwmod_sysc_type2,
425 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
427 .sysc = &am33xx_epwmss_sysc,
431 struct omap_hwmod am33xx_epwmss0_hwmod = {
433 .class = &am33xx_epwmss_hwmod_class,
434 .clkdm_name = "l4ls_clkdm",
435 .main_clk = "l4ls_gclk",
438 .modulemode = MODULEMODE_SWCTRL,
444 struct omap_hwmod am33xx_epwmss1_hwmod = {
446 .class = &am33xx_epwmss_hwmod_class,
447 .clkdm_name = "l4ls_clkdm",
448 .main_clk = "l4ls_gclk",
451 .modulemode = MODULEMODE_SWCTRL,
457 struct omap_hwmod am33xx_epwmss2_hwmod = {
459 .class = &am33xx_epwmss_hwmod_class,
460 .clkdm_name = "l4ls_clkdm",
461 .main_clk = "l4ls_gclk",
464 .modulemode = MODULEMODE_SWCTRL,
470 * 'gpio' class: for gpio 0,1,2,3
472 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
476 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
477 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
478 SYSS_HAS_RESET_STATUS),
479 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
481 .sysc_fields = &omap_hwmod_sysc_type1,
484 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
486 .sysc = &am33xx_gpio_sysc,
490 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
491 { .role = "dbclk", .clk = "gpio1_dbclk" },
494 static struct omap_hwmod am33xx_gpio1_hwmod = {
496 .class = &am33xx_gpio_hwmod_class,
497 .clkdm_name = "l4ls_clkdm",
498 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
499 .main_clk = "l4ls_gclk",
502 .modulemode = MODULEMODE_SWCTRL,
505 .opt_clks = gpio1_opt_clks,
506 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
510 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
511 { .role = "dbclk", .clk = "gpio2_dbclk" },
514 static struct omap_hwmod am33xx_gpio2_hwmod = {
516 .class = &am33xx_gpio_hwmod_class,
517 .clkdm_name = "l4ls_clkdm",
518 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
519 .main_clk = "l4ls_gclk",
522 .modulemode = MODULEMODE_SWCTRL,
525 .opt_clks = gpio2_opt_clks,
526 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
530 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
531 { .role = "dbclk", .clk = "gpio3_dbclk" },
534 static struct omap_hwmod am33xx_gpio3_hwmod = {
536 .class = &am33xx_gpio_hwmod_class,
537 .clkdm_name = "l4ls_clkdm",
538 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
539 .main_clk = "l4ls_gclk",
542 .modulemode = MODULEMODE_SWCTRL,
545 .opt_clks = gpio3_opt_clks,
546 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
550 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
554 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
555 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
556 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
557 .sysc_fields = &omap_hwmod_sysc_type1,
560 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
565 struct omap_hwmod am33xx_gpmc_hwmod = {
567 .class = &am33xx_gpmc_hwmod_class,
568 .clkdm_name = "l3s_clkdm",
569 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
570 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
571 .main_clk = "l3s_gclk",
574 .modulemode = MODULEMODE_SWCTRL,
581 * mailbox module allowing communication between the on-chip processors using a
582 * queued mailbox-interrupt mechanism.
584 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
587 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
589 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
590 .sysc_fields = &omap_hwmod_sysc_type2,
593 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
595 .sysc = &am33xx_mailbox_sysc,
598 struct omap_hwmod am33xx_mailbox_hwmod = {
600 .class = &am33xx_mailbox_hwmod_class,
601 .clkdm_name = "l4ls_clkdm",
602 .main_clk = "l4ls_gclk",
605 .modulemode = MODULEMODE_SWCTRL,
613 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
616 .sysc_flags = SYSC_HAS_SIDLEMODE,
617 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
618 .sysc_fields = &omap_hwmod_sysc_type3,
621 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
623 .sysc = &am33xx_mcasp_sysc,
627 struct omap_hwmod am33xx_mcasp0_hwmod = {
629 .class = &am33xx_mcasp_hwmod_class,
630 .clkdm_name = "l3s_clkdm",
631 .main_clk = "mcasp0_fck",
634 .modulemode = MODULEMODE_SWCTRL,
640 struct omap_hwmod am33xx_mcasp1_hwmod = {
642 .class = &am33xx_mcasp_hwmod_class,
643 .clkdm_name = "l3s_clkdm",
644 .main_clk = "mcasp1_fck",
647 .modulemode = MODULEMODE_SWCTRL,
656 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
659 .sysc_flags = SYSC_HAS_SIDLEMODE,
660 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
661 SIDLE_SMART | SIDLE_SMART_WKUP),
662 .sysc_fields = &omap_hwmod_sysc_type3,
665 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
667 .sysc = &am33xx_rtc_sysc,
668 .unlock = &omap_hwmod_rtc_unlock,
669 .lock = &omap_hwmod_rtc_lock,
672 struct omap_hwmod am33xx_rtc_hwmod = {
674 .class = &am33xx_rtc_hwmod_class,
675 .clkdm_name = "l4_rtc_clkdm",
676 .main_clk = "clk_32768_ck",
679 .modulemode = MODULEMODE_SWCTRL,
685 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
689 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
690 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
691 SYSS_HAS_RESET_STATUS),
692 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
693 .sysc_fields = &omap_hwmod_sysc_type1,
696 struct omap_hwmod_class am33xx_spi_hwmod_class = {
698 .sysc = &am33xx_mcspi_sysc,
702 struct omap_hwmod am33xx_spi0_hwmod = {
704 .class = &am33xx_spi_hwmod_class,
705 .clkdm_name = "l4ls_clkdm",
706 .main_clk = "dpll_per_m2_div4_ck",
709 .modulemode = MODULEMODE_SWCTRL,
715 struct omap_hwmod am33xx_spi1_hwmod = {
717 .class = &am33xx_spi_hwmod_class,
718 .clkdm_name = "l4ls_clkdm",
719 .main_clk = "dpll_per_m2_div4_ck",
722 .modulemode = MODULEMODE_SWCTRL,
729 * spinlock provides hardware assistance for synchronizing the
730 * processes running on multiple processors
733 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
737 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
738 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
739 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
740 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
741 .sysc_fields = &omap_hwmod_sysc_type1,
744 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
746 .sysc = &am33xx_spinlock_sysc,
749 struct omap_hwmod am33xx_spinlock_hwmod = {
751 .class = &am33xx_spinlock_hwmod_class,
752 .clkdm_name = "l4ls_clkdm",
753 .main_clk = "l4ls_gclk",
756 .modulemode = MODULEMODE_SWCTRL,
761 /* 'timer 2-7' class */
762 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
766 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
767 SYSC_HAS_RESET_STATUS,
768 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
770 .sysc_fields = &omap_hwmod_sysc_type2,
773 struct omap_hwmod_class am33xx_timer_hwmod_class = {
775 .sysc = &am33xx_timer_sysc,
779 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
783 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
784 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
785 SYSS_HAS_RESET_STATUS),
786 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
787 .sysc_fields = &omap_hwmod_sysc_type1,
790 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
792 .sysc = &am33xx_timer1ms_sysc,
795 struct omap_hwmod am33xx_timer1_hwmod = {
797 .class = &am33xx_timer1ms_hwmod_class,
798 .clkdm_name = "l4_wkup_clkdm",
799 .main_clk = "timer1_fck",
802 .modulemode = MODULEMODE_SWCTRL,
807 struct omap_hwmod am33xx_timer2_hwmod = {
809 .class = &am33xx_timer_hwmod_class,
810 .clkdm_name = "l4ls_clkdm",
811 .main_clk = "timer2_fck",
814 .modulemode = MODULEMODE_SWCTRL,
819 struct omap_hwmod am33xx_timer3_hwmod = {
821 .class = &am33xx_timer_hwmod_class,
822 .clkdm_name = "l4ls_clkdm",
823 .main_clk = "timer3_fck",
826 .modulemode = MODULEMODE_SWCTRL,
831 struct omap_hwmod am33xx_timer4_hwmod = {
833 .class = &am33xx_timer_hwmod_class,
834 .clkdm_name = "l4ls_clkdm",
835 .main_clk = "timer4_fck",
838 .modulemode = MODULEMODE_SWCTRL,
843 struct omap_hwmod am33xx_timer5_hwmod = {
845 .class = &am33xx_timer_hwmod_class,
846 .clkdm_name = "l4ls_clkdm",
847 .main_clk = "timer5_fck",
850 .modulemode = MODULEMODE_SWCTRL,
855 struct omap_hwmod am33xx_timer6_hwmod = {
857 .class = &am33xx_timer_hwmod_class,
858 .clkdm_name = "l4ls_clkdm",
859 .main_clk = "timer6_fck",
862 .modulemode = MODULEMODE_SWCTRL,
867 struct omap_hwmod am33xx_timer7_hwmod = {
869 .class = &am33xx_timer_hwmod_class,
870 .clkdm_name = "l4ls_clkdm",
871 .main_clk = "timer7_fck",
874 .modulemode = MODULEMODE_SWCTRL,
880 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
884 struct omap_hwmod am33xx_tpcc_hwmod = {
886 .class = &am33xx_tpcc_hwmod_class,
887 .clkdm_name = "l3_clkdm",
888 .main_clk = "l3_gclk",
891 .modulemode = MODULEMODE_SWCTRL,
896 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
899 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
901 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
902 .sysc_fields = &omap_hwmod_sysc_type2,
906 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
908 .sysc = &am33xx_tptc_sysc,
912 struct omap_hwmod am33xx_tptc0_hwmod = {
914 .class = &am33xx_tptc_hwmod_class,
915 .clkdm_name = "l3_clkdm",
916 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
917 .main_clk = "l3_gclk",
920 .modulemode = MODULEMODE_SWCTRL,
926 struct omap_hwmod am33xx_tptc1_hwmod = {
928 .class = &am33xx_tptc_hwmod_class,
929 .clkdm_name = "l3_clkdm",
930 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
931 .main_clk = "l3_gclk",
934 .modulemode = MODULEMODE_SWCTRL,
940 struct omap_hwmod am33xx_tptc2_hwmod = {
942 .class = &am33xx_tptc_hwmod_class,
943 .clkdm_name = "l3_clkdm",
944 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
945 .main_clk = "l3_gclk",
948 .modulemode = MODULEMODE_SWCTRL,
953 /* 'wd_timer' class */
954 static struct omap_hwmod_class_sysconfig wdt_sysc = {
958 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
959 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
960 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
962 .sysc_fields = &omap_hwmod_sysc_type1,
965 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
968 .pre_shutdown = &omap2_wd_timer_disable,
972 * XXX: device.c file uses hardcoded name for watchdog timer
973 * driver "wd_timer2, so we are also using same name as of now...
975 struct omap_hwmod am33xx_wd_timer1_hwmod = {
977 .class = &am33xx_wd_timer_hwmod_class,
978 .clkdm_name = "l4_wkup_clkdm",
979 .flags = HWMOD_SWSUP_SIDLE,
980 .main_clk = "wdt1_fck",
983 .modulemode = MODULEMODE_SWCTRL,
988 static void omap_hwmod_am33xx_clkctrl(void)
990 CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
991 CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
992 CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
993 CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
994 CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
995 CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
996 CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
997 CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
998 CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
999 CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1000 CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1001 CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1002 CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1003 CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1004 CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1005 CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1006 CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1007 CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1008 CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1009 CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1010 CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1011 CLKCTRL(am33xx_smartreflex0_hwmod,
1012 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1013 CLKCTRL(am33xx_smartreflex1_hwmod,
1014 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1015 CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1016 CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1017 CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1018 PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
1019 CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1020 CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1021 CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1022 CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1023 CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1024 CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1025 CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1026 CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1027 CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1028 CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1029 CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1030 CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1031 CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1032 CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1033 CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1034 CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
1037 static void omap_hwmod_am33xx_rst(void)
1039 RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1040 RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1041 RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1044 void omap_hwmod_am33xx_reg(void)
1046 omap_hwmod_am33xx_clkctrl();
1047 omap_hwmod_am33xx_rst();
1050 static void omap_hwmod_am43xx_clkctrl(void)
1052 CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1053 CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1054 CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1055 CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1056 CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1057 CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1058 CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1059 CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1060 CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1061 CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1062 CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1063 CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1064 CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1065 CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1066 CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1067 CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1068 CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1069 CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1070 CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1071 CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1072 CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1073 CLKCTRL(am33xx_smartreflex0_hwmod,
1074 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1075 CLKCTRL(am33xx_smartreflex1_hwmod,
1076 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1077 CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1078 CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1079 CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1080 CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1081 CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1082 CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1083 CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1084 CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1085 CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1086 CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1087 CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1088 CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1089 CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1090 CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1091 CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1092 CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1093 CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1094 CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1095 CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
1098 static void omap_hwmod_am43xx_rst(void)
1100 RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1101 RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1102 RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1103 RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1106 void omap_hwmod_am43xx_reg(void)
1108 omap_hwmod_am43xx_clkctrl();
1109 omap_hwmod_am43xx_rst();