2 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
4 * Copyright (C) 2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/platform_data/gpio-omap.h>
13 #include <linux/omap-dma.h>
14 #include <plat/dmtimer.h>
15 #include <linux/platform_data/spi-omap2-mcspi.h>
17 #include "omap_hwmod.h"
18 #include "omap_hwmod_common_data.h"
19 #include "cm-regbits-24xx.h"
20 #include "prm-regbits-24xx.h"
23 static struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
24 { .name = "dispc", .dma_req = 5 },
33 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
37 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
38 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
39 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
40 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
41 .sysc_fields = &omap_hwmod_sysc_type1,
44 struct omap_hwmod_class omap2_dispc_hwmod_class = {
46 .sysc = &omap2_dispc_sysc,
49 /* OMAP2xxx Timer Common */
50 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
54 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
55 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
56 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
57 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
58 .clockact = CLOCKACT_TEST_ICLK,
59 .sysc_fields = &omap_hwmod_sysc_type1,
62 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
64 .sysc = &omap2xxx_timer_sysc,
69 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
73 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
77 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
78 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
79 .sysc_fields = &omap_hwmod_sysc_type1,
82 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
84 .sysc = &omap2xxx_wd_timer_sysc,
85 .pre_shutdown = &omap2_wd_timer_disable,
86 .reset = &omap2_wd_timer_reset,
91 * general purpose io module
93 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
97 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
98 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
99 SYSS_HAS_RESET_STATUS),
100 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
101 .sysc_fields = &omap_hwmod_sysc_type1,
104 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
106 .sysc = &omap2xxx_gpio_sysc,
111 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
115 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
116 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
117 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
118 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
119 .sysc_fields = &omap_hwmod_sysc_type1,
122 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
124 .sysc = &omap2xxx_dma_sysc,
129 * mailbox module allowing communication between the on-chip processors
130 * using a queued mailbox-interrupt mechanism.
133 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
137 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
138 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
139 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
140 .sysc_fields = &omap_hwmod_sysc_type1,
143 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
145 .sysc = &omap2xxx_mailbox_sysc,
150 * multichannel serial port interface (mcspi) / master/slave synchronous serial
154 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
158 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
159 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
160 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
161 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
162 .sysc_fields = &omap_hwmod_sysc_type1,
165 struct omap_hwmod_class omap2xxx_mcspi_class = {
167 .sysc = &omap2xxx_mcspi_sysc,
168 .rev = OMAP2_MCSPI_REV,
173 * general purpose memory controller
176 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
180 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
181 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
182 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
183 .sysc_fields = &omap_hwmod_sysc_type1,
186 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
188 .sysc = &omap2xxx_gpmc_sysc,
196 struct omap_hwmod omap2xxx_l3_main_hwmod = {
198 .class = &l3_hwmod_class,
199 .flags = HWMOD_NO_IDLEST,
203 struct omap_hwmod omap2xxx_l4_core_hwmod = {
205 .class = &l4_hwmod_class,
206 .flags = HWMOD_NO_IDLEST,
210 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
212 .class = &l4_hwmod_class,
213 .flags = HWMOD_NO_IDLEST,
217 struct omap_hwmod omap2xxx_mpu_hwmod = {
219 .class = &mpu_hwmod_class,
220 .main_clk = "mpu_ck",
224 struct omap_hwmod omap2xxx_iva_hwmod = {
226 .class = &iva_hwmod_class,
229 /* always-on timers dev attribute */
230 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
231 .timer_capability = OMAP_TIMER_ALWON,
234 /* pwm timers dev attribute */
235 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
236 .timer_capability = OMAP_TIMER_HAS_PWM,
239 /* timers with DSP interrupt dev attribute */
240 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
241 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
246 struct omap_hwmod omap2xxx_timer1_hwmod = {
248 .main_clk = "gpt1_fck",
252 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
253 .module_offs = WKUP_MOD,
255 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
258 .dev_attr = &capability_alwon_dev_attr,
259 .class = &omap2xxx_timer_hwmod_class,
260 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
265 struct omap_hwmod omap2xxx_timer2_hwmod = {
267 .main_clk = "gpt2_fck",
271 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
272 .module_offs = CORE_MOD,
274 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
277 .class = &omap2xxx_timer_hwmod_class,
278 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
283 struct omap_hwmod omap2xxx_timer3_hwmod = {
285 .main_clk = "gpt3_fck",
289 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
290 .module_offs = CORE_MOD,
292 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
295 .class = &omap2xxx_timer_hwmod_class,
296 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
301 struct omap_hwmod omap2xxx_timer4_hwmod = {
303 .main_clk = "gpt4_fck",
307 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
308 .module_offs = CORE_MOD,
310 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
313 .class = &omap2xxx_timer_hwmod_class,
314 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
319 struct omap_hwmod omap2xxx_timer5_hwmod = {
321 .main_clk = "gpt5_fck",
325 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
326 .module_offs = CORE_MOD,
328 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
331 .dev_attr = &capability_dsp_dev_attr,
332 .class = &omap2xxx_timer_hwmod_class,
333 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
338 struct omap_hwmod omap2xxx_timer6_hwmod = {
340 .main_clk = "gpt6_fck",
344 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
345 .module_offs = CORE_MOD,
347 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
350 .dev_attr = &capability_dsp_dev_attr,
351 .class = &omap2xxx_timer_hwmod_class,
352 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
357 struct omap_hwmod omap2xxx_timer7_hwmod = {
359 .main_clk = "gpt7_fck",
363 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
364 .module_offs = CORE_MOD,
366 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
369 .dev_attr = &capability_dsp_dev_attr,
370 .class = &omap2xxx_timer_hwmod_class,
371 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
376 struct omap_hwmod omap2xxx_timer8_hwmod = {
378 .main_clk = "gpt8_fck",
382 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
383 .module_offs = CORE_MOD,
385 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
388 .dev_attr = &capability_dsp_dev_attr,
389 .class = &omap2xxx_timer_hwmod_class,
390 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
395 struct omap_hwmod omap2xxx_timer9_hwmod = {
397 .main_clk = "gpt9_fck",
401 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
402 .module_offs = CORE_MOD,
404 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
407 .dev_attr = &capability_pwm_dev_attr,
408 .class = &omap2xxx_timer_hwmod_class,
409 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
414 struct omap_hwmod omap2xxx_timer10_hwmod = {
416 .main_clk = "gpt10_fck",
420 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
421 .module_offs = CORE_MOD,
423 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
426 .dev_attr = &capability_pwm_dev_attr,
427 .class = &omap2xxx_timer_hwmod_class,
428 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
433 struct omap_hwmod omap2xxx_timer11_hwmod = {
435 .main_clk = "gpt11_fck",
439 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
440 .module_offs = CORE_MOD,
442 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
445 .dev_attr = &capability_pwm_dev_attr,
446 .class = &omap2xxx_timer_hwmod_class,
447 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
452 struct omap_hwmod omap2xxx_timer12_hwmod = {
454 .main_clk = "gpt12_fck",
458 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
459 .module_offs = CORE_MOD,
461 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
464 .dev_attr = &capability_pwm_dev_attr,
465 .class = &omap2xxx_timer_hwmod_class,
466 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
470 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
472 .class = &omap2xxx_wd_timer_hwmod_class,
473 .main_clk = "mpu_wdt_fck",
477 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
478 .module_offs = WKUP_MOD,
480 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
487 struct omap_hwmod omap2xxx_uart1_hwmod = {
489 .main_clk = "uart1_fck",
490 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
493 .module_offs = CORE_MOD,
495 .module_bit = OMAP24XX_EN_UART1_SHIFT,
497 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
500 .class = &omap2_uart_class,
505 struct omap_hwmod omap2xxx_uart2_hwmod = {
507 .main_clk = "uart2_fck",
508 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
511 .module_offs = CORE_MOD,
513 .module_bit = OMAP24XX_EN_UART2_SHIFT,
515 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
518 .class = &omap2_uart_class,
523 struct omap_hwmod omap2xxx_uart3_hwmod = {
525 .main_clk = "uart3_fck",
526 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
529 .module_offs = CORE_MOD,
531 .module_bit = OMAP24XX_EN_UART3_SHIFT,
533 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
536 .class = &omap2_uart_class,
541 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
543 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
544 * driver does not use these clocks.
546 { .role = "tv_clk", .clk = "dss_54m_fck" },
547 { .role = "sys_clk", .clk = "dss2_fck" },
550 struct omap_hwmod omap2xxx_dss_core_hwmod = {
552 .class = &omap2_dss_hwmod_class,
553 .main_clk = "dss1_fck", /* instead of dss_fck */
554 .sdma_reqs = omap2xxx_dss_sdma_chs,
558 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
559 .module_offs = CORE_MOD,
561 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
564 .opt_clks = dss_opt_clks,
565 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
566 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
569 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
571 .class = &omap2_dispc_hwmod_class,
572 .mpu_irqs = omap2_dispc_irqs,
573 .main_clk = "dss1_fck",
577 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
578 .module_offs = CORE_MOD,
580 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
583 .flags = HWMOD_NO_IDLEST,
584 .dev_attr = &omap2_3_dss_dispc_dev_attr,
587 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
588 { .role = "ick", .clk = "dss_ick" },
591 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
593 .class = &omap2_rfbi_hwmod_class,
594 .main_clk = "dss1_fck",
598 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
599 .module_offs = CORE_MOD,
602 .opt_clks = dss_rfbi_opt_clks,
603 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
604 .flags = HWMOD_NO_IDLEST,
607 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
609 .class = &omap2_venc_hwmod_class,
610 .main_clk = "dss_54m_fck",
614 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
615 .module_offs = CORE_MOD,
618 .flags = HWMOD_NO_IDLEST,
622 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
628 struct omap_hwmod omap2xxx_gpio1_hwmod = {
630 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
631 .main_clk = "gpios_fck",
635 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
636 .module_offs = WKUP_MOD,
638 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
641 .class = &omap2xxx_gpio_hwmod_class,
642 .dev_attr = &omap2xxx_gpio_dev_attr,
646 struct omap_hwmod omap2xxx_gpio2_hwmod = {
648 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
649 .main_clk = "gpios_fck",
653 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
654 .module_offs = WKUP_MOD,
656 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
659 .class = &omap2xxx_gpio_hwmod_class,
660 .dev_attr = &omap2xxx_gpio_dev_attr,
664 struct omap_hwmod omap2xxx_gpio3_hwmod = {
666 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
667 .main_clk = "gpios_fck",
671 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
672 .module_offs = WKUP_MOD,
674 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
677 .class = &omap2xxx_gpio_hwmod_class,
678 .dev_attr = &omap2xxx_gpio_dev_attr,
682 struct omap_hwmod omap2xxx_gpio4_hwmod = {
684 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
685 .main_clk = "gpios_fck",
689 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
690 .module_offs = WKUP_MOD,
692 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
695 .class = &omap2xxx_gpio_hwmod_class,
696 .dev_attr = &omap2xxx_gpio_dev_attr,
700 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
704 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
706 .main_clk = "mcspi1_fck",
709 .module_offs = CORE_MOD,
711 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
713 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
716 .class = &omap2xxx_mcspi_class,
717 .dev_attr = &omap_mcspi1_dev_attr,
721 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
725 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
727 .main_clk = "mcspi2_fck",
730 .module_offs = CORE_MOD,
732 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
734 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
737 .class = &omap2xxx_mcspi_class,
738 .dev_attr = &omap_mcspi2_dev_attr,
741 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
745 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
746 .name = "counter_32k",
747 .main_clk = "func_32k_ck",
750 .module_offs = WKUP_MOD,
752 .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
754 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
757 .class = &omap2xxx_counter_hwmod_class,
761 struct omap_hwmod omap2xxx_gpmc_hwmod = {
763 .class = &omap2xxx_gpmc_hwmod_class,
764 .main_clk = "gpmc_fck",
765 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
766 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
770 .module_bit = OMAP24XX_EN_GPMC_MASK,
771 .module_offs = CORE_MOD,
778 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
782 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
783 SYSS_HAS_RESET_STATUS),
784 .sysc_fields = &omap_hwmod_sysc_type1,
787 static struct omap_hwmod_class omap2_rng_hwmod_class = {
789 .sysc = &omap2_rng_sysc,
792 struct omap_hwmod omap2xxx_rng_hwmod = {
797 .module_offs = CORE_MOD,
799 .module_bit = OMAP24XX_EN_RNG_SHIFT,
801 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
805 * XXX The first read from the SYSSTATUS register of the RNG
806 * after the SYSCONFIG SOFTRESET bit is set triggers an
807 * imprecise external abort. It's unclear why this happens.
808 * Until this is analyzed, skip the IP block reset.
810 .flags = HWMOD_INIT_NO_RESET,
811 .class = &omap2_rng_hwmod_class,
816 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
820 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
821 SYSS_HAS_RESET_STATUS),
822 .sysc_fields = &omap_hwmod_sysc_type1,
825 static struct omap_hwmod_class omap2xxx_sham_class = {
827 .sysc = &omap2_sham_sysc,
830 struct omap_hwmod omap2xxx_sham_hwmod = {
835 .module_offs = CORE_MOD,
837 .module_bit = OMAP24XX_EN_SHA_SHIFT,
839 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
842 .class = &omap2xxx_sham_class,
847 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
851 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
852 SYSS_HAS_RESET_STATUS),
853 .sysc_fields = &omap_hwmod_sysc_type1,
856 static struct omap_hwmod_class omap2xxx_aes_class = {
858 .sysc = &omap2_aes_sysc,
861 struct omap_hwmod omap2xxx_aes_hwmod = {
866 .module_offs = CORE_MOD,
868 .module_bit = OMAP24XX_EN_AES_SHIFT,
870 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
873 .class = &omap2xxx_aes_class,