1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
5 * Copyright (C) 2011 Nokia Corporation
9 #include <linux/types.h>
11 #include "omap_hwmod.h"
12 #include "omap_hwmod_common_data.h"
13 #include "cm-regbits-24xx.h"
14 #include "prm-regbits-24xx.h"
22 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
26 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
27 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
28 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
29 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
30 .sysc_fields = &omap_hwmod_sysc_type1,
33 static struct omap_hwmod_class omap2_dispc_hwmod_class = {
35 .sysc = &omap2_dispc_sysc,
38 /* OMAP2xxx Timer Common */
39 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
43 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
44 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
45 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
46 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
47 .sysc_fields = &omap_hwmod_sysc_type1,
50 static struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
52 .sysc = &omap2xxx_timer_sysc,
57 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
61 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
65 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
66 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
67 .sysc_fields = &omap_hwmod_sysc_type1,
70 static struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
72 .sysc = &omap2xxx_wd_timer_sysc,
73 .pre_shutdown = &omap2_wd_timer_disable,
74 .reset = &omap2_wd_timer_reset,
79 * general purpose io module
81 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
85 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
86 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
87 SYSS_HAS_RESET_STATUS),
88 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
89 .sysc_fields = &omap_hwmod_sysc_type1,
92 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
94 .sysc = &omap2xxx_gpio_sysc,
99 * mailbox module allowing communication between the on-chip processors
100 * using a queued mailbox-interrupt mechanism.
103 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
107 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
108 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
109 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
110 .sysc_fields = &omap_hwmod_sysc_type1,
113 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
115 .sysc = &omap2xxx_mailbox_sysc,
120 * multichannel serial port interface (mcspi) / master/slave synchronous serial
124 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
128 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
129 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
130 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
131 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
132 .sysc_fields = &omap_hwmod_sysc_type1,
135 struct omap_hwmod_class omap2xxx_mcspi_class = {
137 .sysc = &omap2xxx_mcspi_sysc,
142 * general purpose memory controller
145 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
149 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
150 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
151 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
152 .sysc_fields = &omap_hwmod_sysc_type1,
155 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
157 .sysc = &omap2xxx_gpmc_sysc,
165 struct omap_hwmod omap2xxx_l3_main_hwmod = {
167 .class = &l3_hwmod_class,
168 .flags = HWMOD_NO_IDLEST,
172 struct omap_hwmod omap2xxx_l4_core_hwmod = {
174 .class = &l4_hwmod_class,
175 .flags = HWMOD_NO_IDLEST,
179 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
181 .class = &l4_hwmod_class,
182 .flags = HWMOD_NO_IDLEST,
186 struct omap_hwmod omap2xxx_mpu_hwmod = {
188 .class = &mpu_hwmod_class,
189 .main_clk = "mpu_ck",
193 struct omap_hwmod omap2xxx_timer3_hwmod = {
195 .main_clk = "gpt3_fck",
198 .module_offs = CORE_MOD,
200 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
203 .class = &omap2xxx_timer_hwmod_class,
204 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
208 struct omap_hwmod omap2xxx_timer4_hwmod = {
210 .main_clk = "gpt4_fck",
213 .module_offs = CORE_MOD,
215 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
218 .class = &omap2xxx_timer_hwmod_class,
219 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
223 struct omap_hwmod omap2xxx_timer5_hwmod = {
225 .main_clk = "gpt5_fck",
228 .module_offs = CORE_MOD,
230 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
233 .class = &omap2xxx_timer_hwmod_class,
234 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
238 struct omap_hwmod omap2xxx_timer6_hwmod = {
240 .main_clk = "gpt6_fck",
243 .module_offs = CORE_MOD,
245 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
248 .class = &omap2xxx_timer_hwmod_class,
249 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
253 struct omap_hwmod omap2xxx_timer7_hwmod = {
255 .main_clk = "gpt7_fck",
258 .module_offs = CORE_MOD,
260 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
263 .class = &omap2xxx_timer_hwmod_class,
264 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
268 struct omap_hwmod omap2xxx_timer8_hwmod = {
270 .main_clk = "gpt8_fck",
273 .module_offs = CORE_MOD,
275 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
278 .class = &omap2xxx_timer_hwmod_class,
279 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
283 struct omap_hwmod omap2xxx_timer9_hwmod = {
285 .main_clk = "gpt9_fck",
288 .module_offs = CORE_MOD,
290 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
293 .class = &omap2xxx_timer_hwmod_class,
294 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
298 struct omap_hwmod omap2xxx_timer10_hwmod = {
300 .main_clk = "gpt10_fck",
303 .module_offs = CORE_MOD,
305 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
308 .class = &omap2xxx_timer_hwmod_class,
309 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
313 struct omap_hwmod omap2xxx_timer11_hwmod = {
315 .main_clk = "gpt11_fck",
318 .module_offs = CORE_MOD,
320 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
323 .class = &omap2xxx_timer_hwmod_class,
324 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
328 struct omap_hwmod omap2xxx_timer12_hwmod = {
330 .main_clk = "gpt12_fck",
333 .module_offs = CORE_MOD,
335 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
338 .class = &omap2xxx_timer_hwmod_class,
339 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
343 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
345 .class = &omap2xxx_wd_timer_hwmod_class,
346 .main_clk = "mpu_wdt_fck",
349 .module_offs = WKUP_MOD,
351 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
358 struct omap_hwmod omap2xxx_uart1_hwmod = {
360 .main_clk = "uart1_fck",
361 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
364 .module_offs = CORE_MOD,
366 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
369 .class = &omap2_uart_class,
374 struct omap_hwmod omap2xxx_uart2_hwmod = {
376 .main_clk = "uart2_fck",
377 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
380 .module_offs = CORE_MOD,
382 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
385 .class = &omap2_uart_class,
390 struct omap_hwmod omap2xxx_uart3_hwmod = {
392 .main_clk = "uart3_fck",
393 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
396 .module_offs = CORE_MOD,
398 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
401 .class = &omap2_uart_class,
406 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
408 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
409 * driver does not use these clocks.
411 { .role = "tv_clk", .clk = "dss_54m_fck" },
412 { .role = "sys_clk", .clk = "dss2_fck" },
415 struct omap_hwmod omap2xxx_dss_core_hwmod = {
417 .class = &omap2_dss_hwmod_class,
418 .main_clk = "dss1_fck", /* instead of dss_fck */
421 .module_offs = CORE_MOD,
425 .opt_clks = dss_opt_clks,
426 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
427 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
430 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
432 .class = &omap2_dispc_hwmod_class,
433 .main_clk = "dss1_fck",
436 .module_offs = CORE_MOD,
440 .flags = HWMOD_NO_IDLEST,
441 .dev_attr = &omap2_3_dss_dispc_dev_attr,
444 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
445 { .role = "ick", .clk = "dss_ick" },
448 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
450 .class = &omap2_rfbi_hwmod_class,
451 .main_clk = "dss1_fck",
454 .module_offs = CORE_MOD,
457 .opt_clks = dss_rfbi_opt_clks,
458 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
459 .flags = HWMOD_NO_IDLEST,
462 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
464 .class = &omap2_venc_hwmod_class,
465 .main_clk = "dss_54m_fck",
468 .module_offs = CORE_MOD,
471 .flags = HWMOD_NO_IDLEST,
475 struct omap_hwmod omap2xxx_gpio1_hwmod = {
477 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
478 .main_clk = "gpios_fck",
481 .module_offs = WKUP_MOD,
483 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
486 .class = &omap2xxx_gpio_hwmod_class,
490 struct omap_hwmod omap2xxx_gpio2_hwmod = {
492 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
493 .main_clk = "gpios_fck",
496 .module_offs = WKUP_MOD,
498 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
501 .class = &omap2xxx_gpio_hwmod_class,
505 struct omap_hwmod omap2xxx_gpio3_hwmod = {
507 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
508 .main_clk = "gpios_fck",
511 .module_offs = WKUP_MOD,
513 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
516 .class = &omap2xxx_gpio_hwmod_class,
520 struct omap_hwmod omap2xxx_gpio4_hwmod = {
522 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
523 .main_clk = "gpios_fck",
526 .module_offs = WKUP_MOD,
528 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
531 .class = &omap2xxx_gpio_hwmod_class,
535 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
537 .main_clk = "mcspi1_fck",
540 .module_offs = CORE_MOD,
542 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
545 .class = &omap2xxx_mcspi_class,
549 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
551 .main_clk = "mcspi2_fck",
554 .module_offs = CORE_MOD,
556 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
559 .class = &omap2xxx_mcspi_class,
563 struct omap_hwmod omap2xxx_gpmc_hwmod = {
565 .class = &omap2xxx_gpmc_hwmod_class,
566 .main_clk = "gpmc_fck",
567 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
568 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
571 .module_offs = CORE_MOD,
578 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
582 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
583 SYSS_HAS_RESET_STATUS),
584 .sysc_fields = &omap_hwmod_sysc_type1,
587 static struct omap_hwmod_class omap2_rng_hwmod_class = {
589 .sysc = &omap2_rng_sysc,
592 struct omap_hwmod omap2xxx_rng_hwmod = {
597 .module_offs = CORE_MOD,
599 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
603 * XXX The first read from the SYSSTATUS register of the RNG
604 * after the SYSCONFIG SOFTRESET bit is set triggers an
605 * imprecise external abort. It's unclear why this happens.
606 * Until this is analyzed, skip the IP block reset.
608 .flags = HWMOD_INIT_NO_RESET,
609 .class = &omap2_rng_hwmod_class,
614 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
618 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
619 SYSS_HAS_RESET_STATUS),
620 .sysc_fields = &omap_hwmod_sysc_type1,
623 static struct omap_hwmod_class omap2xxx_sham_class = {
625 .sysc = &omap2_sham_sysc,
628 struct omap_hwmod omap2xxx_sham_hwmod = {
633 .module_offs = CORE_MOD,
635 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
638 .class = &omap2xxx_sham_class,
643 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
647 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
648 SYSS_HAS_RESET_STATUS),
649 .sysc_fields = &omap_hwmod_sysc_type1,
652 static struct omap_hwmod_class omap2xxx_aes_class = {
654 .sysc = &omap2_aes_sysc,
657 struct omap_hwmod omap2xxx_aes_hwmod = {
662 .module_offs = CORE_MOD,
664 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
667 .class = &omap2xxx_aes_class,