1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
5 * Copyright (C) 2011 Nokia Corporation
9 #include <linux/types.h>
10 #include <linux/omap-dma.h>
12 #include "omap_hwmod.h"
13 #include "omap_hwmod_common_data.h"
14 #include "cm-regbits-24xx.h"
15 #include "prm-regbits-24xx.h"
23 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
27 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
28 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
29 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
30 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
31 .sysc_fields = &omap_hwmod_sysc_type1,
34 struct omap_hwmod_class omap2_dispc_hwmod_class = {
36 .sysc = &omap2_dispc_sysc,
39 /* OMAP2xxx Timer Common */
40 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
44 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
45 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
46 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
47 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
48 .sysc_fields = &omap_hwmod_sysc_type1,
51 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
53 .sysc = &omap2xxx_timer_sysc,
58 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
62 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
66 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
67 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
68 .sysc_fields = &omap_hwmod_sysc_type1,
71 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
73 .sysc = &omap2xxx_wd_timer_sysc,
74 .pre_shutdown = &omap2_wd_timer_disable,
75 .reset = &omap2_wd_timer_reset,
80 * general purpose io module
82 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
86 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
87 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
88 SYSS_HAS_RESET_STATUS),
89 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
90 .sysc_fields = &omap_hwmod_sysc_type1,
93 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
95 .sysc = &omap2xxx_gpio_sysc,
99 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
103 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
104 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
105 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
106 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
107 .sysc_fields = &omap_hwmod_sysc_type1,
110 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
112 .sysc = &omap2xxx_dma_sysc,
117 * mailbox module allowing communication between the on-chip processors
118 * using a queued mailbox-interrupt mechanism.
121 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
125 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
126 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
127 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
128 .sysc_fields = &omap_hwmod_sysc_type1,
131 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
133 .sysc = &omap2xxx_mailbox_sysc,
138 * multichannel serial port interface (mcspi) / master/slave synchronous serial
142 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
146 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
147 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
148 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
149 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
150 .sysc_fields = &omap_hwmod_sysc_type1,
153 struct omap_hwmod_class omap2xxx_mcspi_class = {
155 .sysc = &omap2xxx_mcspi_sysc,
160 * general purpose memory controller
163 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
167 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
168 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
169 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
170 .sysc_fields = &omap_hwmod_sysc_type1,
173 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
175 .sysc = &omap2xxx_gpmc_sysc,
183 struct omap_hwmod omap2xxx_l3_main_hwmod = {
185 .class = &l3_hwmod_class,
186 .flags = HWMOD_NO_IDLEST,
190 struct omap_hwmod omap2xxx_l4_core_hwmod = {
192 .class = &l4_hwmod_class,
193 .flags = HWMOD_NO_IDLEST,
197 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
199 .class = &l4_hwmod_class,
200 .flags = HWMOD_NO_IDLEST,
204 struct omap_hwmod omap2xxx_mpu_hwmod = {
206 .class = &mpu_hwmod_class,
207 .main_clk = "mpu_ck",
211 struct omap_hwmod omap2xxx_iva_hwmod = {
213 .class = &iva_hwmod_class,
217 struct omap_hwmod omap2xxx_timer1_hwmod = {
219 .main_clk = "gpt1_fck",
222 .module_offs = WKUP_MOD,
224 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
227 .class = &omap2xxx_timer_hwmod_class,
228 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
232 struct omap_hwmod omap2xxx_timer2_hwmod = {
234 .main_clk = "gpt2_fck",
237 .module_offs = CORE_MOD,
239 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
242 .class = &omap2xxx_timer_hwmod_class,
243 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
247 struct omap_hwmod omap2xxx_timer3_hwmod = {
249 .main_clk = "gpt3_fck",
252 .module_offs = CORE_MOD,
254 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
257 .class = &omap2xxx_timer_hwmod_class,
258 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
262 struct omap_hwmod omap2xxx_timer4_hwmod = {
264 .main_clk = "gpt4_fck",
267 .module_offs = CORE_MOD,
269 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
272 .class = &omap2xxx_timer_hwmod_class,
273 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
277 struct omap_hwmod omap2xxx_timer5_hwmod = {
279 .main_clk = "gpt5_fck",
282 .module_offs = CORE_MOD,
284 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
287 .class = &omap2xxx_timer_hwmod_class,
288 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
292 struct omap_hwmod omap2xxx_timer6_hwmod = {
294 .main_clk = "gpt6_fck",
297 .module_offs = CORE_MOD,
299 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
302 .class = &omap2xxx_timer_hwmod_class,
303 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
307 struct omap_hwmod omap2xxx_timer7_hwmod = {
309 .main_clk = "gpt7_fck",
312 .module_offs = CORE_MOD,
314 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
317 .class = &omap2xxx_timer_hwmod_class,
318 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
322 struct omap_hwmod omap2xxx_timer8_hwmod = {
324 .main_clk = "gpt8_fck",
327 .module_offs = CORE_MOD,
329 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
332 .class = &omap2xxx_timer_hwmod_class,
333 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
337 struct omap_hwmod omap2xxx_timer9_hwmod = {
339 .main_clk = "gpt9_fck",
342 .module_offs = CORE_MOD,
344 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
347 .class = &omap2xxx_timer_hwmod_class,
348 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
352 struct omap_hwmod omap2xxx_timer10_hwmod = {
354 .main_clk = "gpt10_fck",
357 .module_offs = CORE_MOD,
359 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
362 .class = &omap2xxx_timer_hwmod_class,
363 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
367 struct omap_hwmod omap2xxx_timer11_hwmod = {
369 .main_clk = "gpt11_fck",
372 .module_offs = CORE_MOD,
374 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
377 .class = &omap2xxx_timer_hwmod_class,
378 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
382 struct omap_hwmod omap2xxx_timer12_hwmod = {
384 .main_clk = "gpt12_fck",
387 .module_offs = CORE_MOD,
389 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
392 .class = &omap2xxx_timer_hwmod_class,
393 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
397 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
399 .class = &omap2xxx_wd_timer_hwmod_class,
400 .main_clk = "mpu_wdt_fck",
403 .module_offs = WKUP_MOD,
405 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
412 struct omap_hwmod omap2xxx_uart1_hwmod = {
414 .main_clk = "uart1_fck",
415 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
418 .module_offs = CORE_MOD,
420 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
423 .class = &omap2_uart_class,
428 struct omap_hwmod omap2xxx_uart2_hwmod = {
430 .main_clk = "uart2_fck",
431 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
434 .module_offs = CORE_MOD,
436 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
439 .class = &omap2_uart_class,
444 struct omap_hwmod omap2xxx_uart3_hwmod = {
446 .main_clk = "uart3_fck",
447 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
450 .module_offs = CORE_MOD,
452 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
455 .class = &omap2_uart_class,
460 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
462 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
463 * driver does not use these clocks.
465 { .role = "tv_clk", .clk = "dss_54m_fck" },
466 { .role = "sys_clk", .clk = "dss2_fck" },
469 struct omap_hwmod omap2xxx_dss_core_hwmod = {
471 .class = &omap2_dss_hwmod_class,
472 .main_clk = "dss1_fck", /* instead of dss_fck */
475 .module_offs = CORE_MOD,
479 .opt_clks = dss_opt_clks,
480 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
481 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
484 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
486 .class = &omap2_dispc_hwmod_class,
487 .main_clk = "dss1_fck",
490 .module_offs = CORE_MOD,
494 .flags = HWMOD_NO_IDLEST,
495 .dev_attr = &omap2_3_dss_dispc_dev_attr,
498 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
499 { .role = "ick", .clk = "dss_ick" },
502 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
504 .class = &omap2_rfbi_hwmod_class,
505 .main_clk = "dss1_fck",
508 .module_offs = CORE_MOD,
511 .opt_clks = dss_rfbi_opt_clks,
512 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
513 .flags = HWMOD_NO_IDLEST,
516 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
518 .class = &omap2_venc_hwmod_class,
519 .main_clk = "dss_54m_fck",
522 .module_offs = CORE_MOD,
525 .flags = HWMOD_NO_IDLEST,
529 struct omap_hwmod omap2xxx_gpio1_hwmod = {
531 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
532 .main_clk = "gpios_fck",
535 .module_offs = WKUP_MOD,
537 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
540 .class = &omap2xxx_gpio_hwmod_class,
544 struct omap_hwmod omap2xxx_gpio2_hwmod = {
546 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
547 .main_clk = "gpios_fck",
550 .module_offs = WKUP_MOD,
552 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
555 .class = &omap2xxx_gpio_hwmod_class,
559 struct omap_hwmod omap2xxx_gpio3_hwmod = {
561 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
562 .main_clk = "gpios_fck",
565 .module_offs = WKUP_MOD,
567 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
570 .class = &omap2xxx_gpio_hwmod_class,
574 struct omap_hwmod omap2xxx_gpio4_hwmod = {
576 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
577 .main_clk = "gpios_fck",
580 .module_offs = WKUP_MOD,
582 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
585 .class = &omap2xxx_gpio_hwmod_class,
589 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
591 .main_clk = "mcspi1_fck",
594 .module_offs = CORE_MOD,
596 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
599 .class = &omap2xxx_mcspi_class,
603 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
605 .main_clk = "mcspi2_fck",
608 .module_offs = CORE_MOD,
610 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
613 .class = &omap2xxx_mcspi_class,
616 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
620 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
621 .name = "counter_32k",
622 .main_clk = "func_32k_ck",
625 .module_offs = WKUP_MOD,
627 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
630 .class = &omap2xxx_counter_hwmod_class,
634 struct omap_hwmod omap2xxx_gpmc_hwmod = {
636 .class = &omap2xxx_gpmc_hwmod_class,
637 .main_clk = "gpmc_fck",
638 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
639 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
642 .module_offs = CORE_MOD,
649 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
653 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
654 SYSS_HAS_RESET_STATUS),
655 .sysc_fields = &omap_hwmod_sysc_type1,
658 static struct omap_hwmod_class omap2_rng_hwmod_class = {
660 .sysc = &omap2_rng_sysc,
663 struct omap_hwmod omap2xxx_rng_hwmod = {
668 .module_offs = CORE_MOD,
670 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
674 * XXX The first read from the SYSSTATUS register of the RNG
675 * after the SYSCONFIG SOFTRESET bit is set triggers an
676 * imprecise external abort. It's unclear why this happens.
677 * Until this is analyzed, skip the IP block reset.
679 .flags = HWMOD_INIT_NO_RESET,
680 .class = &omap2_rng_hwmod_class,
685 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
689 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
690 SYSS_HAS_RESET_STATUS),
691 .sysc_fields = &omap_hwmod_sysc_type1,
694 static struct omap_hwmod_class omap2xxx_sham_class = {
696 .sysc = &omap2_sham_sysc,
699 struct omap_hwmod omap2xxx_sham_hwmod = {
704 .module_offs = CORE_MOD,
706 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
709 .class = &omap2xxx_sham_class,
714 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
718 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
719 SYSS_HAS_RESET_STATUS),
720 .sysc_fields = &omap_hwmod_sysc_type1,
723 static struct omap_hwmod_class omap2xxx_aes_class = {
725 .sysc = &omap2_aes_sysc,
728 struct omap_hwmod omap2xxx_aes_hwmod = {
733 .module_offs = CORE_MOD,
735 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
738 .class = &omap2xxx_aes_class,