2 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
4 * Copyright (C) 2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/platform_data/gpio-omap.h>
13 #include <linux/omap-dma.h>
14 #include <plat/dmtimer.h>
15 #include <linux/platform_data/spi-omap2-mcspi.h>
17 #include "omap_hwmod.h"
18 #include "omap_hwmod_common_data.h"
19 #include "cm-regbits-24xx.h"
20 #include "prm-regbits-24xx.h"
23 static struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
24 { .name = "dispc", .dma_req = 5 },
33 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
37 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
38 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
39 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
40 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
41 .sysc_fields = &omap_hwmod_sysc_type1,
44 struct omap_hwmod_class omap2_dispc_hwmod_class = {
46 .sysc = &omap2_dispc_sysc,
49 /* OMAP2xxx Timer Common */
50 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
54 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
55 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
56 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
57 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
58 .sysc_fields = &omap_hwmod_sysc_type1,
61 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
63 .sysc = &omap2xxx_timer_sysc,
68 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
72 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
76 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
77 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
78 .sysc_fields = &omap_hwmod_sysc_type1,
81 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
83 .sysc = &omap2xxx_wd_timer_sysc,
84 .pre_shutdown = &omap2_wd_timer_disable,
85 .reset = &omap2_wd_timer_reset,
90 * general purpose io module
92 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
96 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
97 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
98 SYSS_HAS_RESET_STATUS),
99 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
100 .sysc_fields = &omap_hwmod_sysc_type1,
103 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
105 .sysc = &omap2xxx_gpio_sysc,
110 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
114 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
115 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
116 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
117 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
118 .sysc_fields = &omap_hwmod_sysc_type1,
121 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
123 .sysc = &omap2xxx_dma_sysc,
128 * mailbox module allowing communication between the on-chip processors
129 * using a queued mailbox-interrupt mechanism.
132 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
136 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
137 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
138 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
139 .sysc_fields = &omap_hwmod_sysc_type1,
142 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
144 .sysc = &omap2xxx_mailbox_sysc,
149 * multichannel serial port interface (mcspi) / master/slave synchronous serial
153 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
157 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
158 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
159 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
160 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
161 .sysc_fields = &omap_hwmod_sysc_type1,
164 struct omap_hwmod_class omap2xxx_mcspi_class = {
166 .sysc = &omap2xxx_mcspi_sysc,
167 .rev = OMAP2_MCSPI_REV,
172 * general purpose memory controller
175 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
179 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
180 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
181 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
182 .sysc_fields = &omap_hwmod_sysc_type1,
185 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
187 .sysc = &omap2xxx_gpmc_sysc,
195 struct omap_hwmod omap2xxx_l3_main_hwmod = {
197 .class = &l3_hwmod_class,
198 .flags = HWMOD_NO_IDLEST,
202 struct omap_hwmod omap2xxx_l4_core_hwmod = {
204 .class = &l4_hwmod_class,
205 .flags = HWMOD_NO_IDLEST,
209 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
211 .class = &l4_hwmod_class,
212 .flags = HWMOD_NO_IDLEST,
216 struct omap_hwmod omap2xxx_mpu_hwmod = {
218 .class = &mpu_hwmod_class,
219 .main_clk = "mpu_ck",
223 struct omap_hwmod omap2xxx_iva_hwmod = {
225 .class = &iva_hwmod_class,
228 /* always-on timers dev attribute */
229 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
230 .timer_capability = OMAP_TIMER_ALWON,
233 /* pwm timers dev attribute */
234 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
235 .timer_capability = OMAP_TIMER_HAS_PWM,
238 /* timers with DSP interrupt dev attribute */
239 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
240 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
245 struct omap_hwmod omap2xxx_timer1_hwmod = {
247 .main_clk = "gpt1_fck",
251 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
252 .module_offs = WKUP_MOD,
254 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
257 .dev_attr = &capability_alwon_dev_attr,
258 .class = &omap2xxx_timer_hwmod_class,
259 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
264 struct omap_hwmod omap2xxx_timer2_hwmod = {
266 .main_clk = "gpt2_fck",
270 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
271 .module_offs = CORE_MOD,
273 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
276 .class = &omap2xxx_timer_hwmod_class,
277 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
282 struct omap_hwmod omap2xxx_timer3_hwmod = {
284 .main_clk = "gpt3_fck",
288 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
289 .module_offs = CORE_MOD,
291 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
294 .class = &omap2xxx_timer_hwmod_class,
295 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
300 struct omap_hwmod omap2xxx_timer4_hwmod = {
302 .main_clk = "gpt4_fck",
306 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
307 .module_offs = CORE_MOD,
309 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
312 .class = &omap2xxx_timer_hwmod_class,
313 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
318 struct omap_hwmod omap2xxx_timer5_hwmod = {
320 .main_clk = "gpt5_fck",
324 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
325 .module_offs = CORE_MOD,
327 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
330 .dev_attr = &capability_dsp_dev_attr,
331 .class = &omap2xxx_timer_hwmod_class,
332 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
337 struct omap_hwmod omap2xxx_timer6_hwmod = {
339 .main_clk = "gpt6_fck",
343 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
344 .module_offs = CORE_MOD,
346 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
349 .dev_attr = &capability_dsp_dev_attr,
350 .class = &omap2xxx_timer_hwmod_class,
351 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
356 struct omap_hwmod omap2xxx_timer7_hwmod = {
358 .main_clk = "gpt7_fck",
362 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
363 .module_offs = CORE_MOD,
365 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
368 .dev_attr = &capability_dsp_dev_attr,
369 .class = &omap2xxx_timer_hwmod_class,
370 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
375 struct omap_hwmod omap2xxx_timer8_hwmod = {
377 .main_clk = "gpt8_fck",
381 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
382 .module_offs = CORE_MOD,
384 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
387 .dev_attr = &capability_dsp_dev_attr,
388 .class = &omap2xxx_timer_hwmod_class,
389 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
394 struct omap_hwmod omap2xxx_timer9_hwmod = {
396 .main_clk = "gpt9_fck",
400 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
401 .module_offs = CORE_MOD,
403 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
406 .dev_attr = &capability_pwm_dev_attr,
407 .class = &omap2xxx_timer_hwmod_class,
408 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
413 struct omap_hwmod omap2xxx_timer10_hwmod = {
415 .main_clk = "gpt10_fck",
419 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
420 .module_offs = CORE_MOD,
422 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
425 .dev_attr = &capability_pwm_dev_attr,
426 .class = &omap2xxx_timer_hwmod_class,
427 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
432 struct omap_hwmod omap2xxx_timer11_hwmod = {
434 .main_clk = "gpt11_fck",
438 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
439 .module_offs = CORE_MOD,
441 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
444 .dev_attr = &capability_pwm_dev_attr,
445 .class = &omap2xxx_timer_hwmod_class,
446 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
451 struct omap_hwmod omap2xxx_timer12_hwmod = {
453 .main_clk = "gpt12_fck",
457 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
458 .module_offs = CORE_MOD,
460 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
463 .dev_attr = &capability_pwm_dev_attr,
464 .class = &omap2xxx_timer_hwmod_class,
465 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
469 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
471 .class = &omap2xxx_wd_timer_hwmod_class,
472 .main_clk = "mpu_wdt_fck",
476 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
477 .module_offs = WKUP_MOD,
479 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
486 struct omap_hwmod omap2xxx_uart1_hwmod = {
488 .main_clk = "uart1_fck",
489 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
492 .module_offs = CORE_MOD,
494 .module_bit = OMAP24XX_EN_UART1_SHIFT,
496 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
499 .class = &omap2_uart_class,
504 struct omap_hwmod omap2xxx_uart2_hwmod = {
506 .main_clk = "uart2_fck",
507 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
510 .module_offs = CORE_MOD,
512 .module_bit = OMAP24XX_EN_UART2_SHIFT,
514 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
517 .class = &omap2_uart_class,
522 struct omap_hwmod omap2xxx_uart3_hwmod = {
524 .main_clk = "uart3_fck",
525 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
528 .module_offs = CORE_MOD,
530 .module_bit = OMAP24XX_EN_UART3_SHIFT,
532 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
535 .class = &omap2_uart_class,
540 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
542 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
543 * driver does not use these clocks.
545 { .role = "tv_clk", .clk = "dss_54m_fck" },
546 { .role = "sys_clk", .clk = "dss2_fck" },
549 struct omap_hwmod omap2xxx_dss_core_hwmod = {
551 .class = &omap2_dss_hwmod_class,
552 .main_clk = "dss1_fck", /* instead of dss_fck */
553 .sdma_reqs = omap2xxx_dss_sdma_chs,
557 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
558 .module_offs = CORE_MOD,
560 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
563 .opt_clks = dss_opt_clks,
564 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
565 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
568 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
570 .class = &omap2_dispc_hwmod_class,
571 .main_clk = "dss1_fck",
575 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
576 .module_offs = CORE_MOD,
578 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
581 .flags = HWMOD_NO_IDLEST,
582 .dev_attr = &omap2_3_dss_dispc_dev_attr,
585 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
586 { .role = "ick", .clk = "dss_ick" },
589 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
591 .class = &omap2_rfbi_hwmod_class,
592 .main_clk = "dss1_fck",
596 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
597 .module_offs = CORE_MOD,
600 .opt_clks = dss_rfbi_opt_clks,
601 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
602 .flags = HWMOD_NO_IDLEST,
605 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
607 .class = &omap2_venc_hwmod_class,
608 .main_clk = "dss_54m_fck",
612 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
613 .module_offs = CORE_MOD,
616 .flags = HWMOD_NO_IDLEST,
620 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
626 struct omap_hwmod omap2xxx_gpio1_hwmod = {
628 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
629 .main_clk = "gpios_fck",
633 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
634 .module_offs = WKUP_MOD,
636 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
639 .class = &omap2xxx_gpio_hwmod_class,
640 .dev_attr = &omap2xxx_gpio_dev_attr,
644 struct omap_hwmod omap2xxx_gpio2_hwmod = {
646 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
647 .main_clk = "gpios_fck",
651 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
652 .module_offs = WKUP_MOD,
654 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
657 .class = &omap2xxx_gpio_hwmod_class,
658 .dev_attr = &omap2xxx_gpio_dev_attr,
662 struct omap_hwmod omap2xxx_gpio3_hwmod = {
664 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
665 .main_clk = "gpios_fck",
669 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
670 .module_offs = WKUP_MOD,
672 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
675 .class = &omap2xxx_gpio_hwmod_class,
676 .dev_attr = &omap2xxx_gpio_dev_attr,
680 struct omap_hwmod omap2xxx_gpio4_hwmod = {
682 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
683 .main_clk = "gpios_fck",
687 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
688 .module_offs = WKUP_MOD,
690 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
693 .class = &omap2xxx_gpio_hwmod_class,
694 .dev_attr = &omap2xxx_gpio_dev_attr,
698 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
702 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
704 .main_clk = "mcspi1_fck",
707 .module_offs = CORE_MOD,
709 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
711 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
714 .class = &omap2xxx_mcspi_class,
715 .dev_attr = &omap_mcspi1_dev_attr,
719 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
723 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
725 .main_clk = "mcspi2_fck",
728 .module_offs = CORE_MOD,
730 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
732 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
735 .class = &omap2xxx_mcspi_class,
736 .dev_attr = &omap_mcspi2_dev_attr,
739 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
743 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
744 .name = "counter_32k",
745 .main_clk = "func_32k_ck",
748 .module_offs = WKUP_MOD,
750 .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
752 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
755 .class = &omap2xxx_counter_hwmod_class,
759 struct omap_hwmod omap2xxx_gpmc_hwmod = {
761 .class = &omap2xxx_gpmc_hwmod_class,
762 .main_clk = "gpmc_fck",
763 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
764 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
768 .module_bit = OMAP24XX_EN_GPMC_MASK,
769 .module_offs = CORE_MOD,
776 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
780 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
781 SYSS_HAS_RESET_STATUS),
782 .sysc_fields = &omap_hwmod_sysc_type1,
785 static struct omap_hwmod_class omap2_rng_hwmod_class = {
787 .sysc = &omap2_rng_sysc,
790 struct omap_hwmod omap2xxx_rng_hwmod = {
795 .module_offs = CORE_MOD,
797 .module_bit = OMAP24XX_EN_RNG_SHIFT,
799 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
803 * XXX The first read from the SYSSTATUS register of the RNG
804 * after the SYSCONFIG SOFTRESET bit is set triggers an
805 * imprecise external abort. It's unclear why this happens.
806 * Until this is analyzed, skip the IP block reset.
808 .flags = HWMOD_INIT_NO_RESET,
809 .class = &omap2_rng_hwmod_class,
814 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
818 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
819 SYSS_HAS_RESET_STATUS),
820 .sysc_fields = &omap_hwmod_sysc_type1,
823 static struct omap_hwmod_class omap2xxx_sham_class = {
825 .sysc = &omap2_sham_sysc,
828 struct omap_hwmod omap2xxx_sham_hwmod = {
833 .module_offs = CORE_MOD,
835 .module_bit = OMAP24XX_EN_SHA_SHIFT,
837 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
840 .class = &omap2xxx_sham_class,
845 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
849 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
850 SYSS_HAS_RESET_STATUS),
851 .sysc_fields = &omap_hwmod_sysc_type1,
854 static struct omap_hwmod_class omap2xxx_aes_class = {
856 .sysc = &omap2_aes_sysc,
859 struct omap_hwmod omap2xxx_aes_hwmod = {
864 .module_offs = CORE_MOD,
866 .module_bit = OMAP24XX_EN_AES_SHIFT,
868 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
871 .class = &omap2xxx_aes_class,