GNU Linux-libre 4.19.304-gnu1
[releases.git] / arch / arm / mach-omap2 / omap_hwmod_2430_data.c
1 /*
2  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
3  *
4  * Copyright (C) 2009-2011 Nokia Corporation
5  * Copyright (C) 2012 Texas Instruments, Inc.
6  * Paul Walmsley
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * XXX handle crossbar/shared link difference for L3?
13  * XXX these should be marked initdata for multi-OMAP kernels
14  */
15
16 #include <linux/platform_data/i2c-omap.h>
17 #include <linux/platform_data/hsmmc-omap.h>
18 #include <linux/omap-dma.h>
19
20 #include "omap_hwmod.h"
21 #include "l3_2xxx.h"
22
23 #include "soc.h"
24 #include "omap_hwmod_common_data.h"
25 #include "prm-regbits-24xx.h"
26 #include "cm-regbits-24xx.h"
27 #include "i2c.h"
28 #include "wd_timer.h"
29
30 /*
31  * OMAP2430 hardware module integration data
32  *
33  * All of the data in this section should be autogeneratable from the
34  * TI hardware database or other technical documentation.  Data that
35  * is driver-specific or driver-kernel integration-specific belongs
36  * elsewhere.
37  */
38
39 /*
40  * IP blocks
41  */
42
43 /* IVA2 (IVA2) */
44 static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
45         { .name = "logic", .rst_shift = 0 },
46         { .name = "mmu", .rst_shift = 1 },
47 };
48
49 static struct omap_hwmod omap2430_iva_hwmod = {
50         .name           = "iva",
51         .class          = &iva_hwmod_class,
52         .clkdm_name     = "dsp_clkdm",
53         .rst_lines      = omap2430_iva_resets,
54         .rst_lines_cnt  = ARRAY_SIZE(omap2430_iva_resets),
55         .main_clk       = "dsp_fck",
56 };
57
58 /* I2C common */
59 static struct omap_hwmod_class_sysconfig i2c_sysc = {
60         .rev_offs       = 0x00,
61         .sysc_offs      = 0x20,
62         .syss_offs      = 0x10,
63         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
64                            SYSS_HAS_RESET_STATUS),
65         .sysc_fields    = &omap_hwmod_sysc_type1,
66 };
67
68 static struct omap_hwmod_class i2c_class = {
69         .name           = "i2c",
70         .sysc           = &i2c_sysc,
71         .rev            = OMAP_I2C_IP_VERSION_1,
72         .reset          = &omap_i2c_reset,
73 };
74
75 /* I2C1 */
76 static struct omap_hwmod omap2430_i2c1_hwmod = {
77         .name           = "i2c1",
78         .flags          = HWMOD_16BIT_REG,
79         .main_clk       = "i2chs1_fck",
80         .prcm           = {
81                 .omap2 = {
82                         /*
83                          * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
84                          * I2CHS IP's do not follow the usual pattern.
85                          * prcm_reg_id alone cannot be used to program
86                          * the iclk and fclk. Needs to be handled using
87                          * additional flags when clk handling is moved
88                          * to hwmod framework.
89                          */
90                         .module_offs = CORE_MOD,
91                         .idlest_reg_id = 1,
92                         .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
93                 },
94         },
95         .class          = &i2c_class,
96 };
97
98 /* I2C2 */
99 static struct omap_hwmod omap2430_i2c2_hwmod = {
100         .name           = "i2c2",
101         .flags          = HWMOD_16BIT_REG,
102         .main_clk       = "i2chs2_fck",
103         .prcm           = {
104                 .omap2 = {
105                         .module_offs = CORE_MOD,
106                         .idlest_reg_id = 1,
107                         .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
108                 },
109         },
110         .class          = &i2c_class,
111 };
112
113 /* gpio5 */
114 static struct omap_hwmod omap2430_gpio5_hwmod = {
115         .name           = "gpio5",
116         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
117         .main_clk       = "gpio5_fck",
118         .prcm           = {
119                 .omap2 = {
120                         .module_offs = CORE_MOD,
121                         .idlest_reg_id = 2,
122                         .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
123                 },
124         },
125         .class          = &omap2xxx_gpio_hwmod_class,
126 };
127
128 /* dma attributes */
129 static struct omap_dma_dev_attr dma_dev_attr = {
130         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
131                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
132         .lch_count = 32,
133 };
134
135 static struct omap_hwmod omap2430_dma_system_hwmod = {
136         .name           = "dma",
137         .class          = &omap2xxx_dma_hwmod_class,
138         .main_clk       = "core_l3_ck",
139         .dev_attr       = &dma_dev_attr,
140         .flags          = HWMOD_NO_IDLEST,
141 };
142
143 /* mailbox */
144 static struct omap_hwmod omap2430_mailbox_hwmod = {
145         .name           = "mailbox",
146         .class          = &omap2xxx_mailbox_hwmod_class,
147         .main_clk       = "mailboxes_ick",
148         .prcm           = {
149                 .omap2 = {
150                         .module_offs = CORE_MOD,
151                         .idlest_reg_id = 1,
152                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
153                 },
154         },
155 };
156
157 /* mcspi3 */
158 static struct omap_hwmod omap2430_mcspi3_hwmod = {
159         .name           = "mcspi3",
160         .main_clk       = "mcspi3_fck",
161         .prcm           = {
162                 .omap2 = {
163                         .module_offs = CORE_MOD,
164                         .idlest_reg_id = 2,
165                         .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
166                 },
167         },
168         .class          = &omap2xxx_mcspi_class,
169 };
170
171 /* usbhsotg */
172 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
173         .rev_offs       = 0x0400,
174         .sysc_offs      = 0x0404,
175         .syss_offs      = 0x0408,
176         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
177                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
178                           SYSC_HAS_AUTOIDLE),
179         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
180                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
181         .sysc_fields    = &omap_hwmod_sysc_type1,
182 };
183
184 static struct omap_hwmod_class usbotg_class = {
185         .name = "usbotg",
186         .sysc = &omap2430_usbhsotg_sysc,
187 };
188
189 /* usb_otg_hs */
190 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
191         .name           = "usb_otg_hs",
192         .main_clk       = "usbhs_ick",
193         .prcm           = {
194                 .omap2 = {
195                         .module_offs = CORE_MOD,
196                         .idlest_reg_id = 1,
197                         .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
198                 },
199         },
200         .class          = &usbotg_class,
201         /*
202          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
203          * broken when autoidle is enabled
204          * workaround is to disable the autoidle bit at module level.
205          */
206         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
207                                 | HWMOD_SWSUP_MSTANDBY,
208 };
209
210 /*
211  * 'mcbsp' class
212  * multi channel buffered serial port controller
213  */
214
215 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
216         .rev_offs       = 0x007C,
217         .sysc_offs      = 0x008C,
218         .sysc_flags     = (SYSC_HAS_SOFTRESET),
219         .sysc_fields    = &omap_hwmod_sysc_type1,
220 };
221
222 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
223         .name = "mcbsp",
224         .sysc = &omap2430_mcbsp_sysc,
225 };
226
227 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
228         { .role = "pad_fck", .clk = "mcbsp_clks" },
229         { .role = "prcm_fck", .clk = "func_96m_ck" },
230 };
231
232 /* mcbsp1 */
233 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
234         .name           = "mcbsp1",
235         .class          = &omap2430_mcbsp_hwmod_class,
236         .main_clk       = "mcbsp1_fck",
237         .prcm           = {
238                 .omap2 = {
239                         .module_offs = CORE_MOD,
240                         .idlest_reg_id = 1,
241                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
242                 },
243         },
244         .opt_clks       = mcbsp_opt_clks,
245         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
246 };
247
248 /* mcbsp2 */
249 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
250         .name           = "mcbsp2",
251         .class          = &omap2430_mcbsp_hwmod_class,
252         .main_clk       = "mcbsp2_fck",
253         .prcm           = {
254                 .omap2 = {
255                         .module_offs = CORE_MOD,
256                         .idlest_reg_id = 1,
257                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
258                 },
259         },
260         .opt_clks       = mcbsp_opt_clks,
261         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
262 };
263
264 /* mcbsp3 */
265 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
266         .name           = "mcbsp3",
267         .class          = &omap2430_mcbsp_hwmod_class,
268         .main_clk       = "mcbsp3_fck",
269         .prcm           = {
270                 .omap2 = {
271                         .module_offs = CORE_MOD,
272                         .idlest_reg_id = 2,
273                         .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
274                 },
275         },
276         .opt_clks       = mcbsp_opt_clks,
277         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
278 };
279
280 /* mcbsp4 */
281 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
282         .name           = "mcbsp4",
283         .class          = &omap2430_mcbsp_hwmod_class,
284         .main_clk       = "mcbsp4_fck",
285         .prcm           = {
286                 .omap2 = {
287                         .module_offs = CORE_MOD,
288                         .idlest_reg_id = 2,
289                         .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
290                 },
291         },
292         .opt_clks       = mcbsp_opt_clks,
293         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
294 };
295
296 /* mcbsp5 */
297 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
298         .name           = "mcbsp5",
299         .class          = &omap2430_mcbsp_hwmod_class,
300         .main_clk       = "mcbsp5_fck",
301         .prcm           = {
302                 .omap2 = {
303                         .module_offs = CORE_MOD,
304                         .idlest_reg_id = 2,
305                         .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
306                 },
307         },
308         .opt_clks       = mcbsp_opt_clks,
309         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
310 };
311
312 /* MMC/SD/SDIO common */
313 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
314         .rev_offs       = 0x1fc,
315         .sysc_offs      = 0x10,
316         .syss_offs      = 0x14,
317         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
318                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
319                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
320         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
321         .sysc_fields    = &omap_hwmod_sysc_type1,
322 };
323
324 static struct omap_hwmod_class omap2430_mmc_class = {
325         .name = "mmc",
326         .sysc = &omap2430_mmc_sysc,
327 };
328
329 /* MMC/SD/SDIO1 */
330 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
331         { .role = "dbck", .clk = "mmchsdb1_fck" },
332 };
333
334 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
335         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
336 };
337
338 static struct omap_hwmod omap2430_mmc1_hwmod = {
339         .name           = "mmc1",
340         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
341         .opt_clks       = omap2430_mmc1_opt_clks,
342         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
343         .main_clk       = "mmchs1_fck",
344         .prcm           = {
345                 .omap2 = {
346                         .module_offs = CORE_MOD,
347                         .idlest_reg_id = 2,
348                         .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
349                 },
350         },
351         .dev_attr       = &mmc1_dev_attr,
352         .class          = &omap2430_mmc_class,
353 };
354
355 /* MMC/SD/SDIO2 */
356 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
357         { .role = "dbck", .clk = "mmchsdb2_fck" },
358 };
359
360 static struct omap_hwmod omap2430_mmc2_hwmod = {
361         .name           = "mmc2",
362         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
363         .opt_clks       = omap2430_mmc2_opt_clks,
364         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
365         .main_clk       = "mmchs2_fck",
366         .prcm           = {
367                 .omap2 = {
368                         .module_offs = CORE_MOD,
369                         .idlest_reg_id = 2,
370                         .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
371                 },
372         },
373         .class          = &omap2430_mmc_class,
374 };
375
376 /* HDQ1W/1-wire */
377 static struct omap_hwmod omap2430_hdq1w_hwmod = {
378         .name           = "hdq1w",
379         .main_clk       = "hdq_fck",
380         .prcm           = {
381                 .omap2 = {
382                         .module_offs = CORE_MOD,
383                         .idlest_reg_id = 1,
384                         .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
385                 },
386         },
387         .class          = &omap2_hdq1w_class,
388 };
389
390 /*
391  * interfaces
392  */
393
394 /* L3 -> L4_CORE interface */
395 /* l3_core -> usbhsotg  interface */
396 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
397         .master         = &omap2430_usbhsotg_hwmod,
398         .slave          = &omap2xxx_l3_main_hwmod,
399         .clk            = "core_l3_ck",
400         .user           = OCP_USER_MPU,
401 };
402
403 /* L4 CORE -> I2C1 interface */
404 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
405         .master         = &omap2xxx_l4_core_hwmod,
406         .slave          = &omap2430_i2c1_hwmod,
407         .clk            = "i2c1_ick",
408         .user           = OCP_USER_MPU | OCP_USER_SDMA,
409 };
410
411 /* L4 CORE -> I2C2 interface */
412 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
413         .master         = &omap2xxx_l4_core_hwmod,
414         .slave          = &omap2430_i2c2_hwmod,
415         .clk            = "i2c2_ick",
416         .user           = OCP_USER_MPU | OCP_USER_SDMA,
417 };
418
419 /*  l4_core ->usbhsotg  interface */
420 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
421         .master         = &omap2xxx_l4_core_hwmod,
422         .slave          = &omap2430_usbhsotg_hwmod,
423         .clk            = "usb_l4_ick",
424         .user           = OCP_USER_MPU,
425 };
426
427 /* L4 CORE -> MMC1 interface */
428 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
429         .master         = &omap2xxx_l4_core_hwmod,
430         .slave          = &omap2430_mmc1_hwmod,
431         .clk            = "mmchs1_ick",
432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
433 };
434
435 /* L4 CORE -> MMC2 interface */
436 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
437         .master         = &omap2xxx_l4_core_hwmod,
438         .slave          = &omap2430_mmc2_hwmod,
439         .clk            = "mmchs2_ick",
440         .user           = OCP_USER_MPU | OCP_USER_SDMA,
441 };
442
443 /* l4 core -> mcspi3 interface */
444 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
445         .master         = &omap2xxx_l4_core_hwmod,
446         .slave          = &omap2430_mcspi3_hwmod,
447         .clk            = "mcspi3_ick",
448         .user           = OCP_USER_MPU | OCP_USER_SDMA,
449 };
450
451 /* IVA2 <- L3 interface */
452 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
453         .master         = &omap2xxx_l3_main_hwmod,
454         .slave          = &omap2430_iva_hwmod,
455         .clk            = "core_l3_ck",
456         .user           = OCP_USER_MPU | OCP_USER_SDMA,
457 };
458
459 /* l4_wkup -> timer1 */
460 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
461         .master         = &omap2xxx_l4_wkup_hwmod,
462         .slave          = &omap2xxx_timer1_hwmod,
463         .clk            = "gpt1_ick",
464         .user           = OCP_USER_MPU | OCP_USER_SDMA,
465 };
466
467 /* l4_wkup -> wd_timer2 */
468 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
469         .master         = &omap2xxx_l4_wkup_hwmod,
470         .slave          = &omap2xxx_wd_timer2_hwmod,
471         .clk            = "mpu_wdt_ick",
472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
473 };
474
475 /* l4_wkup -> gpio1 */
476 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
477         .master         = &omap2xxx_l4_wkup_hwmod,
478         .slave          = &omap2xxx_gpio1_hwmod,
479         .clk            = "gpios_ick",
480         .user           = OCP_USER_MPU | OCP_USER_SDMA,
481 };
482
483 /* l4_wkup -> gpio2 */
484 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
485         .master         = &omap2xxx_l4_wkup_hwmod,
486         .slave          = &omap2xxx_gpio2_hwmod,
487         .clk            = "gpios_ick",
488         .user           = OCP_USER_MPU | OCP_USER_SDMA,
489 };
490
491 /* l4_wkup -> gpio3 */
492 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
493         .master         = &omap2xxx_l4_wkup_hwmod,
494         .slave          = &omap2xxx_gpio3_hwmod,
495         .clk            = "gpios_ick",
496         .user           = OCP_USER_MPU | OCP_USER_SDMA,
497 };
498
499 /* l4_wkup -> gpio4 */
500 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
501         .master         = &omap2xxx_l4_wkup_hwmod,
502         .slave          = &omap2xxx_gpio4_hwmod,
503         .clk            = "gpios_ick",
504         .user           = OCP_USER_MPU | OCP_USER_SDMA,
505 };
506
507 /* l4_core -> gpio5 */
508 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
509         .master         = &omap2xxx_l4_core_hwmod,
510         .slave          = &omap2430_gpio5_hwmod,
511         .clk            = "gpio5_ick",
512         .user           = OCP_USER_MPU | OCP_USER_SDMA,
513 };
514
515 /* dma_system -> L3 */
516 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
517         .master         = &omap2430_dma_system_hwmod,
518         .slave          = &omap2xxx_l3_main_hwmod,
519         .clk            = "core_l3_ck",
520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
521 };
522
523 /* l4_core -> dma_system */
524 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
525         .master         = &omap2xxx_l4_core_hwmod,
526         .slave          = &omap2430_dma_system_hwmod,
527         .clk            = "sdma_ick",
528         .user           = OCP_USER_MPU | OCP_USER_SDMA,
529 };
530
531 /* l4_core -> mailbox */
532 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
533         .master         = &omap2xxx_l4_core_hwmod,
534         .slave          = &omap2430_mailbox_hwmod,
535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
536 };
537
538 /* l4_core -> mcbsp1 */
539 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
540         .master         = &omap2xxx_l4_core_hwmod,
541         .slave          = &omap2430_mcbsp1_hwmod,
542         .clk            = "mcbsp1_ick",
543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
544 };
545
546 /* l4_core -> mcbsp2 */
547 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
548         .master         = &omap2xxx_l4_core_hwmod,
549         .slave          = &omap2430_mcbsp2_hwmod,
550         .clk            = "mcbsp2_ick",
551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
552 };
553
554 /* l4_core -> mcbsp3 */
555 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
556         .master         = &omap2xxx_l4_core_hwmod,
557         .slave          = &omap2430_mcbsp3_hwmod,
558         .clk            = "mcbsp3_ick",
559         .user           = OCP_USER_MPU | OCP_USER_SDMA,
560 };
561
562 /* l4_core -> mcbsp4 */
563 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
564         .master         = &omap2xxx_l4_core_hwmod,
565         .slave          = &omap2430_mcbsp4_hwmod,
566         .clk            = "mcbsp4_ick",
567         .user           = OCP_USER_MPU | OCP_USER_SDMA,
568 };
569
570 /* l4_core -> mcbsp5 */
571 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
572         .master         = &omap2xxx_l4_core_hwmod,
573         .slave          = &omap2430_mcbsp5_hwmod,
574         .clk            = "mcbsp5_ick",
575         .user           = OCP_USER_MPU | OCP_USER_SDMA,
576 };
577
578 /* l4_core -> hdq1w */
579 static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
580         .master         = &omap2xxx_l4_core_hwmod,
581         .slave          = &omap2430_hdq1w_hwmod,
582         .clk            = "hdq_ick",
583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
584         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
585 };
586
587 /* l4_wkup -> 32ksync_counter */
588 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
589         .master         = &omap2xxx_l4_wkup_hwmod,
590         .slave          = &omap2xxx_counter_32k_hwmod,
591         .clk            = "sync_32k_ick",
592         .user           = OCP_USER_MPU | OCP_USER_SDMA,
593 };
594
595 static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
596         .master         = &omap2xxx_l3_main_hwmod,
597         .slave          = &omap2xxx_gpmc_hwmod,
598         .clk            = "core_l3_ck",
599         .user           = OCP_USER_MPU | OCP_USER_SDMA,
600 };
601
602 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
603         &omap2xxx_l3_main__l4_core,
604         &omap2xxx_mpu__l3_main,
605         &omap2xxx_dss__l3,
606         &omap2430_usbhsotg__l3,
607         &omap2430_l4_core__i2c1,
608         &omap2430_l4_core__i2c2,
609         &omap2xxx_l4_core__l4_wkup,
610         &omap2_l4_core__uart1,
611         &omap2_l4_core__uart2,
612         &omap2_l4_core__uart3,
613         &omap2430_l4_core__usbhsotg,
614         &omap2430_l4_core__mmc1,
615         &omap2430_l4_core__mmc2,
616         &omap2xxx_l4_core__mcspi1,
617         &omap2xxx_l4_core__mcspi2,
618         &omap2430_l4_core__mcspi3,
619         &omap2430_l3__iva,
620         &omap2430_l4_wkup__timer1,
621         &omap2xxx_l4_core__timer2,
622         &omap2xxx_l4_core__timer3,
623         &omap2xxx_l4_core__timer4,
624         &omap2xxx_l4_core__timer5,
625         &omap2xxx_l4_core__timer6,
626         &omap2xxx_l4_core__timer7,
627         &omap2xxx_l4_core__timer8,
628         &omap2xxx_l4_core__timer9,
629         &omap2xxx_l4_core__timer10,
630         &omap2xxx_l4_core__timer11,
631         &omap2xxx_l4_core__timer12,
632         &omap2430_l4_wkup__wd_timer2,
633         &omap2xxx_l4_core__dss,
634         &omap2xxx_l4_core__dss_dispc,
635         &omap2xxx_l4_core__dss_rfbi,
636         &omap2xxx_l4_core__dss_venc,
637         &omap2430_l4_wkup__gpio1,
638         &omap2430_l4_wkup__gpio2,
639         &omap2430_l4_wkup__gpio3,
640         &omap2430_l4_wkup__gpio4,
641         &omap2430_l4_core__gpio5,
642         &omap2430_dma_system__l3,
643         &omap2430_l4_core__dma_system,
644         &omap2430_l4_core__mailbox,
645         &omap2430_l4_core__mcbsp1,
646         &omap2430_l4_core__mcbsp2,
647         &omap2430_l4_core__mcbsp3,
648         &omap2430_l4_core__mcbsp4,
649         &omap2430_l4_core__mcbsp5,
650         &omap2430_l4_core__hdq1w,
651         &omap2xxx_l4_core__rng,
652         &omap2xxx_l4_core__sham,
653         &omap2xxx_l4_core__aes,
654         &omap2430_l4_wkup__counter_32k,
655         &omap2430_l3__gpmc,
656         NULL,
657 };
658
659 int __init omap2430_hwmod_init(void)
660 {
661         omap_hwmod_init();
662         return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
663 }