2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * XXX handle crossbar/shared link difference for L3?
13 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <linux/platform_data/i2c-omap.h>
17 #include <linux/omap-dma.h>
19 #include "omap_hwmod.h"
23 #include "omap_hwmod_common_data.h"
25 #include "cm-regbits-24xx.h"
26 #include "prm-regbits-24xx.h"
33 * OMAP2420 hardware module integration data
35 * All of the data in this section should be autogeneratable from the
36 * TI hardware database or other technical documentation. Data that
37 * is driver-specific or driver-kernel integration-specific belongs
46 static struct omap_hwmod_class iva1_hwmod_class = {
50 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
51 { .name = "iva", .rst_shift = 8 },
54 static struct omap_hwmod omap2420_iva_hwmod = {
56 .class = &iva1_hwmod_class,
57 .clkdm_name = "iva1_clkdm",
58 .rst_lines = omap2420_iva_resets,
59 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
60 .main_clk = "iva1_ifck",
64 static struct omap_hwmod_class dsp_hwmod_class = {
68 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
69 { .name = "logic", .rst_shift = 0 },
70 { .name = "mmu", .rst_shift = 1 },
73 static struct omap_hwmod omap2420_dsp_hwmod = {
75 .class = &dsp_hwmod_class,
76 .clkdm_name = "dsp_clkdm",
77 .rst_lines = omap2420_dsp_resets,
78 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
79 .main_clk = "dsp_fck",
83 static struct omap_hwmod_class_sysconfig i2c_sysc = {
87 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
88 .sysc_fields = &omap_hwmod_sysc_type1,
91 static struct omap_hwmod_class i2c_class = {
94 .rev = OMAP_I2C_IP_VERSION_1,
95 .reset = &omap_i2c_reset,
99 static struct omap_hwmod omap2420_i2c1_hwmod = {
101 .main_clk = "i2c1_fck",
104 .module_offs = CORE_MOD,
106 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
111 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
112 * while a transfer is active seems to cause the I2C block to
113 * timeout. Why? Good question."
115 .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
119 static struct omap_hwmod omap2420_i2c2_hwmod = {
121 .main_clk = "i2c2_fck",
124 .module_offs = CORE_MOD,
126 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
130 .flags = HWMOD_16BIT_REG,
134 static struct omap_dma_dev_attr dma_dev_attr = {
135 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
136 IS_CSSA_32 | IS_CDSA_32,
140 static struct omap_hwmod omap2420_dma_system_hwmod = {
142 .class = &omap2xxx_dma_hwmod_class,
143 .main_clk = "core_l3_ck",
144 .dev_attr = &dma_dev_attr,
145 .flags = HWMOD_NO_IDLEST,
149 static struct omap_hwmod omap2420_mailbox_hwmod = {
151 .class = &omap2xxx_mailbox_hwmod_class,
152 .main_clk = "mailboxes_ick",
155 .module_offs = CORE_MOD,
157 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
164 * multi channel buffered serial port controller
167 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
171 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
172 { .role = "pad_fck", .clk = "mcbsp_clks" },
173 { .role = "prcm_fck", .clk = "func_96m_ck" },
177 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
179 .class = &omap2420_mcbsp_hwmod_class,
180 .main_clk = "mcbsp1_fck",
183 .module_offs = CORE_MOD,
185 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
188 .opt_clks = mcbsp_opt_clks,
189 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
193 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
195 .class = &omap2420_mcbsp_hwmod_class,
196 .main_clk = "mcbsp2_fck",
199 .module_offs = CORE_MOD,
201 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
204 .opt_clks = mcbsp_opt_clks,
205 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
208 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
212 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
213 .sysc_fields = &omap_hwmod_sysc_type1,
216 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
218 .sysc = &omap2420_msdi_sysc,
219 .reset = &omap_msdi_reset,
223 static struct omap_hwmod omap2420_msdi1_hwmod = {
225 .class = &omap2420_msdi_hwmod_class,
226 .main_clk = "mmc_fck",
229 .module_offs = CORE_MOD,
231 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
234 .flags = HWMOD_16BIT_REG,
238 static struct omap_hwmod omap2420_hdq1w_hwmod = {
240 .main_clk = "hdq_fck",
243 .module_offs = CORE_MOD,
245 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
248 .class = &omap2_hdq1w_class,
255 /* L4 CORE -> I2C1 interface */
256 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
257 .master = &omap2xxx_l4_core_hwmod,
258 .slave = &omap2420_i2c1_hwmod,
260 .user = OCP_USER_MPU | OCP_USER_SDMA,
263 /* L4 CORE -> I2C2 interface */
264 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
265 .master = &omap2xxx_l4_core_hwmod,
266 .slave = &omap2420_i2c2_hwmod,
268 .user = OCP_USER_MPU | OCP_USER_SDMA,
271 /* IVA <- L3 interface */
272 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
273 .master = &omap2xxx_l3_main_hwmod,
274 .slave = &omap2420_iva_hwmod,
276 .user = OCP_USER_MPU | OCP_USER_SDMA,
279 /* DSP <- L3 interface */
280 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
281 .master = &omap2xxx_l3_main_hwmod,
282 .slave = &omap2420_dsp_hwmod,
284 .user = OCP_USER_MPU | OCP_USER_SDMA,
287 /* l4_wkup -> timer1 */
288 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
289 .master = &omap2xxx_l4_wkup_hwmod,
290 .slave = &omap2xxx_timer1_hwmod,
292 .user = OCP_USER_MPU | OCP_USER_SDMA,
295 /* l4_wkup -> wd_timer2 */
296 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
297 .master = &omap2xxx_l4_wkup_hwmod,
298 .slave = &omap2xxx_wd_timer2_hwmod,
299 .clk = "mpu_wdt_ick",
300 .user = OCP_USER_MPU | OCP_USER_SDMA,
303 /* l4_wkup -> gpio1 */
304 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
305 .master = &omap2xxx_l4_wkup_hwmod,
306 .slave = &omap2xxx_gpio1_hwmod,
308 .user = OCP_USER_MPU | OCP_USER_SDMA,
311 /* l4_wkup -> gpio2 */
312 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
313 .master = &omap2xxx_l4_wkup_hwmod,
314 .slave = &omap2xxx_gpio2_hwmod,
316 .user = OCP_USER_MPU | OCP_USER_SDMA,
319 /* l4_wkup -> gpio3 */
320 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
321 .master = &omap2xxx_l4_wkup_hwmod,
322 .slave = &omap2xxx_gpio3_hwmod,
324 .user = OCP_USER_MPU | OCP_USER_SDMA,
327 /* l4_wkup -> gpio4 */
328 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
329 .master = &omap2xxx_l4_wkup_hwmod,
330 .slave = &omap2xxx_gpio4_hwmod,
332 .user = OCP_USER_MPU | OCP_USER_SDMA,
335 /* dma_system -> L3 */
336 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
337 .master = &omap2420_dma_system_hwmod,
338 .slave = &omap2xxx_l3_main_hwmod,
340 .user = OCP_USER_MPU | OCP_USER_SDMA,
343 /* l4_core -> dma_system */
344 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
345 .master = &omap2xxx_l4_core_hwmod,
346 .slave = &omap2420_dma_system_hwmod,
348 .user = OCP_USER_MPU | OCP_USER_SDMA,
351 /* l4_core -> mailbox */
352 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
353 .master = &omap2xxx_l4_core_hwmod,
354 .slave = &omap2420_mailbox_hwmod,
355 .user = OCP_USER_MPU | OCP_USER_SDMA,
358 /* l4_core -> mcbsp1 */
359 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
360 .master = &omap2xxx_l4_core_hwmod,
361 .slave = &omap2420_mcbsp1_hwmod,
363 .user = OCP_USER_MPU | OCP_USER_SDMA,
366 /* l4_core -> mcbsp2 */
367 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
368 .master = &omap2xxx_l4_core_hwmod,
369 .slave = &omap2420_mcbsp2_hwmod,
371 .user = OCP_USER_MPU | OCP_USER_SDMA,
374 /* l4_core -> msdi1 */
375 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
376 .master = &omap2xxx_l4_core_hwmod,
377 .slave = &omap2420_msdi1_hwmod,
379 .user = OCP_USER_MPU | OCP_USER_SDMA,
382 /* l4_core -> hdq1w interface */
383 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
384 .master = &omap2xxx_l4_core_hwmod,
385 .slave = &omap2420_hdq1w_hwmod,
387 .user = OCP_USER_MPU | OCP_USER_SDMA,
388 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
392 /* l4_wkup -> 32ksync_counter */
393 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
394 .master = &omap2xxx_l4_wkup_hwmod,
395 .slave = &omap2xxx_counter_32k_hwmod,
396 .clk = "sync_32k_ick",
397 .user = OCP_USER_MPU | OCP_USER_SDMA,
400 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
401 .master = &omap2xxx_l3_main_hwmod,
402 .slave = &omap2xxx_gpmc_hwmod,
404 .user = OCP_USER_MPU | OCP_USER_SDMA,
407 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
408 &omap2xxx_l3_main__l4_core,
409 &omap2xxx_mpu__l3_main,
411 &omap2xxx_l4_core__mcspi1,
412 &omap2xxx_l4_core__mcspi2,
413 &omap2xxx_l4_core__l4_wkup,
414 &omap2_l4_core__uart1,
415 &omap2_l4_core__uart2,
416 &omap2_l4_core__uart3,
417 &omap2420_l4_core__i2c1,
418 &omap2420_l4_core__i2c2,
421 &omap2420_l4_wkup__timer1,
422 &omap2xxx_l4_core__timer2,
423 &omap2xxx_l4_core__timer3,
424 &omap2xxx_l4_core__timer4,
425 &omap2xxx_l4_core__timer5,
426 &omap2xxx_l4_core__timer6,
427 &omap2xxx_l4_core__timer7,
428 &omap2xxx_l4_core__timer8,
429 &omap2xxx_l4_core__timer9,
430 &omap2xxx_l4_core__timer10,
431 &omap2xxx_l4_core__timer11,
432 &omap2xxx_l4_core__timer12,
433 &omap2420_l4_wkup__wd_timer2,
434 &omap2xxx_l4_core__dss,
435 &omap2xxx_l4_core__dss_dispc,
436 &omap2xxx_l4_core__dss_rfbi,
437 &omap2xxx_l4_core__dss_venc,
438 &omap2420_l4_wkup__gpio1,
439 &omap2420_l4_wkup__gpio2,
440 &omap2420_l4_wkup__gpio3,
441 &omap2420_l4_wkup__gpio4,
442 &omap2420_dma_system__l3,
443 &omap2420_l4_core__dma_system,
444 &omap2420_l4_core__mailbox,
445 &omap2420_l4_core__mcbsp1,
446 &omap2420_l4_core__mcbsp2,
447 &omap2420_l4_core__msdi1,
448 &omap2xxx_l4_core__rng,
449 &omap2xxx_l4_core__sham,
450 &omap2xxx_l4_core__aes,
451 &omap2420_l4_core__hdq1w,
452 &omap2420_l4_wkup__counter_32k,
457 int __init omap2420_hwmod_init(void)
460 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);