2 * OMAP4 SMP source file. It contains platform specific functions
3 * needed for the linux smp kernel.
5 * Copyright (C) 2009 Texas Instruments, Inc.
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * Platform file needed for the OMAP4 SMP. This file is based on arm
11 * realview smp platform.
12 * * Copyright (c) 2002 ARM Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/smp.h>
22 #include <linux/irqchip/arm-gic.h>
24 #include <asm/smp_scu.h>
27 #include "omap-secure.h"
28 #include "omap-wakeupgen.h"
29 #include <asm/cputype.h>
34 #include "clockdomain.h"
37 #define CPU_MASK 0xff0ffff0
38 #define CPU_CORTEX_A9 0x410FC090
39 #define CPU_CORTEX_A15 0x410FC0F0
41 #define OMAP5_CORE_COUNT 0x2
43 struct omap_smp_config {
44 unsigned long cpu1_rstctrl_pa;
45 void __iomem *cpu1_rstctrl_va;
46 void __iomem *scu_base;
50 static struct omap_smp_config cfg;
52 static const struct omap_smp_config omap443x_cfg __initconst = {
53 .cpu1_rstctrl_pa = 0x4824380c,
54 .startup_addr = omap4_secondary_startup,
57 static const struct omap_smp_config omap446x_cfg __initconst = {
58 .cpu1_rstctrl_pa = 0x4824380c,
59 .startup_addr = omap4460_secondary_startup,
62 static const struct omap_smp_config omap5_cfg __initconst = {
63 .cpu1_rstctrl_pa = 0x48243810,
64 .startup_addr = omap5_secondary_startup,
67 static DEFINE_SPINLOCK(boot_lock);
69 void __iomem *omap4_get_scu_base(void)
74 #ifdef CONFIG_OMAP5_ERRATA_801819
75 void omap5_erratum_workaround_801819(void)
80 /* REVIDR[3] indicates erratum fix available on silicon */
81 asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr));
82 if (revidr & (0x1 << 3))
85 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
87 * BIT(27) - Disables streaming. All write-allocate lines allocate in
89 * BIT(25) - Disables streaming. All write-allocate lines allocate in
92 acr_mask = (0x3 << 25) | (0x3 << 27);
93 /* do we already have it done.. if yes, skip expensive smc */
94 if ((acr & acr_mask) == acr_mask)
98 omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
100 pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n",
101 __func__, smp_processor_id());
104 static inline void omap5_erratum_workaround_801819(void) { }
107 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
109 * Configure ACR and enable ACTLR[0] (Enable invalidates of BTB with
110 * ICIALLU) to activate the workaround for secondary Core.
111 * NOTE: it is assumed that the primary core's configuration is done
112 * by the boot loader (kernel will detect a misconfiguration and complain
113 * if this is not done).
115 * In General Purpose(GP) devices, ACR bit settings can only be done
116 * by ROM code in "secure world" using the smc call and there is no
117 * option to update the "firmware" on such devices. This also works for
118 * High security(HS) devices, as a backup option in case the
119 * "update" is not done in the "security firmware".
121 static void omap5_secondary_harden_predictor(void)
125 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
128 * ACTLR[0] (Enable invalidates of BTB with ICIALLU)
132 /* Do we already have it done.. if yes, skip expensive smc */
133 if ((acr & acr_mask) == acr_mask)
137 omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
139 pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n",
140 __func__, smp_processor_id());
143 static inline void omap5_secondary_harden_predictor(void) { }
146 static void omap4_secondary_init(unsigned int cpu)
149 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
150 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
151 * init and for CPU1, a secure PPA API provided. CPU0 must be ON
152 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
153 * OMAP443X GP devices- SMP bit isn't accessible.
154 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
156 if (soc_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
157 omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
160 if (soc_is_omap54xx() || soc_is_dra7xx()) {
162 * Configure the CNTFRQ register for the secondary cpu's which
163 * indicates the frequency of the cpu local timers.
166 /* Configure ACR to disable streaming WA for 801819 */
167 omap5_erratum_workaround_801819();
168 /* Enable ACR to allow for ICUALLU workaround */
169 omap5_secondary_harden_predictor();
173 * Synchronise with the boot thread.
175 spin_lock(&boot_lock);
176 spin_unlock(&boot_lock);
179 static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
181 static struct clockdomain *cpu1_clkdm;
183 static struct powerdomain *cpu1_pwrdm;
184 void __iomem *base = omap_get_wakeupgen_base();
187 * Set synchronisation state between this boot processor
188 * and the secondary one
190 spin_lock(&boot_lock);
193 * Update the AuxCoreBoot0 with boot state for secondary core.
194 * omap4_secondary_startup() routine will hold the secondary core till
195 * the AuxCoreBoot1 register is updated with cpu state
196 * A barrier is added to ensure that write buffer is drained
198 if (omap_secure_apis_support())
199 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
201 writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0);
203 if (!cpu1_clkdm && !cpu1_pwrdm) {
204 cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
205 cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
209 * The SGI(Software Generated Interrupts) are not wakeup capable
210 * from low power states. This is known limitation on OMAP4 and
211 * needs to be worked around by using software forced clockdomain
212 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
213 * software force wakeup. The clockdomain is then put back to
214 * hardware supervised mode.
215 * More details can be found in OMAP4430 TRM - Version J
217 * 4.3.4.2 Power States of CPU0 and CPU1
219 if (booted && cpu1_pwrdm && cpu1_clkdm) {
221 * GIC distributor control register has changed between
222 * CortexA9 r1pX and r2pX. The Control Register secure
223 * banked version is now composed of 2 bits:
224 * bit 0 == Secure Enable
225 * bit 1 == Non-Secure Enable
226 * The Non-Secure banked register has not changed
227 * Because the ROM Code is based on the r1pX GIC, the CPU1
228 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
229 * The workaround must be:
230 * 1) Before doing the CPU1 wakeup, CPU0 must disable
231 * the GIC distributor
232 * 2) CPU1 must re-enable the GIC distributor on
235 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
241 * Ensure that CPU power state is set to ON to avoid CPU
242 * powerdomain transition on wfi
244 clkdm_deny_idle_nolock(cpu1_clkdm);
245 pwrdm_set_next_pwrst(cpu1_pwrdm, PWRDM_POWER_ON);
246 clkdm_allow_idle_nolock(cpu1_clkdm);
248 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
249 while (gic_dist_disabled()) {
253 gic_timer_retrigger();
261 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
264 * Now the secondary core is starting up let it run its
265 * calibrations, then wait for it to finish
267 spin_unlock(&boot_lock);
273 * Initialise the CPU possible map early - this describes the CPUs
274 * which may be present or become present in the system.
276 static void __init omap4_smp_init_cpus(void)
278 unsigned int i = 0, ncores = 1, cpu_id;
280 /* Use ARM cpuid check here, as SoC detection will not work so early */
281 cpu_id = read_cpuid_id() & CPU_MASK;
282 if (cpu_id == CPU_CORTEX_A9) {
284 * Currently we can't call ioremap here because
285 * SoC detection won't work until after init_early.
287 cfg.scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
288 BUG_ON(!cfg.scu_base);
289 ncores = scu_get_core_count(cfg.scu_base);
290 } else if (cpu_id == CPU_CORTEX_A15) {
291 ncores = OMAP5_CORE_COUNT;
295 if (ncores > nr_cpu_ids) {
296 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
301 for (i = 0; i < ncores; i++)
302 set_cpu_possible(i, true);
305 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
307 void __iomem *base = omap_get_wakeupgen_base();
308 const struct omap_smp_config *c = NULL;
310 if (soc_is_omap443x())
312 else if (soc_is_omap446x())
314 else if (soc_is_dra74x() || soc_is_omap54xx())
318 pr_err("%s Unknown SMP SoC?\n", __func__);
322 /* Must preserve cfg.scu_base set earlier */
323 cfg.cpu1_rstctrl_pa = c->cpu1_rstctrl_pa;
324 cfg.startup_addr = c->startup_addr;
326 if (soc_is_dra74x() || soc_is_omap54xx()) {
327 if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
328 cfg.startup_addr = omap5_secondary_hyp_startup;
329 omap5_erratum_workaround_801819();
332 cfg.cpu1_rstctrl_va = ioremap(cfg.cpu1_rstctrl_pa, 4);
333 if (!cfg.cpu1_rstctrl_va)
337 * Initialise the SCU and wake up the secondary core using
338 * wakeup_secondary().
341 scu_enable(cfg.scu_base);
344 * Reset CPU1 before configuring, otherwise kexec will
345 * end up trying to use old kernel startup address.
347 if (cfg.cpu1_rstctrl_va) {
348 writel_relaxed(1, cfg.cpu1_rstctrl_va);
349 readl_relaxed(cfg.cpu1_rstctrl_va);
350 writel_relaxed(0, cfg.cpu1_rstctrl_va);
354 * Write the address of secondary startup routine into the
355 * AuxCoreBoot1 where ROM code will jump and start executing
356 * on secondary core once out of WFE
357 * A barrier is added to ensure that write buffer is drained
359 if (omap_secure_apis_support())
360 omap_auxcoreboot_addr(virt_to_phys(cfg.startup_addr));
362 writel_relaxed(virt_to_phys(cfg.startup_addr),
363 base + OMAP_AUX_CORE_BOOT_1);
366 const struct smp_operations omap4_smp_ops __initconst = {
367 .smp_init_cpus = omap4_smp_init_cpus,
368 .smp_prepare_cpus = omap4_smp_prepare_cpus,
369 .smp_secondary_init = omap4_secondary_init,
370 .smp_boot_secondary = omap4_boot_secondary,
371 #ifdef CONFIG_HOTPLUG_CPU
372 .cpu_die = omap4_cpu_die,
373 .cpu_kill = omap4_cpu_kill,