GNU Linux-libre 4.19.304-gnu1
[releases.git] / arch / arm / mach-omap2 / id.c
1 /*
2  * linux/arch/arm/mach-omap2/id.c
3  *
4  * OMAP2 CPU identification code
5  *
6  * Copyright (C) 2005 Nokia Corporation
7  * Written by Tony Lindgren <tony@atomide.com>
8  *
9  * Copyright (C) 2009-11 Texas Instruments
10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  */
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
21 #include <linux/random.h>
22 #include <linux/slab.h>
23
24 #ifdef CONFIG_SOC_BUS
25 #include <linux/sys_soc.h>
26 #endif
27
28 #include <asm/cputype.h>
29
30 #include "common.h"
31
32 #include "id.h"
33
34 #include "soc.h"
35 #include "control.h"
36
37 #define OMAP4_SILICON_TYPE_STANDARD             0x01
38 #define OMAP4_SILICON_TYPE_PERFORMANCE          0x02
39
40 #define OMAP_SOC_MAX_NAME_LENGTH                16
41
42 static unsigned int omap_revision;
43 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
44 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
45 u32 omap_features;
46
47 unsigned int omap_rev(void)
48 {
49         return omap_revision;
50 }
51 EXPORT_SYMBOL(omap_rev);
52
53 int omap_type(void)
54 {
55         static u32 val = OMAP2_DEVICETYPE_MASK;
56
57         if (val < OMAP2_DEVICETYPE_MASK)
58                 return val;
59
60         if (soc_is_omap24xx()) {
61                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
62         } else if (soc_is_ti81xx()) {
63                 val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
64         } else if (soc_is_am33xx() || soc_is_am43xx()) {
65                 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
66         } else if (soc_is_omap34xx()) {
67                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
68         } else if (soc_is_omap44xx()) {
69                 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
70         } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
71                 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
72                 val &= OMAP5_DEVICETYPE_MASK;
73                 val >>= 6;
74                 goto out;
75         } else {
76                 pr_err("Cannot detect omap type!\n");
77                 goto out;
78         }
79
80         val &= OMAP2_DEVICETYPE_MASK;
81         val >>= 8;
82
83 out:
84         return val;
85 }
86 EXPORT_SYMBOL(omap_type);
87
88
89 /*----------------------------------------------------------------------------*/
90
91 #define OMAP_TAP_IDCODE         0x0204
92 #define OMAP_TAP_DIE_ID_0       0x0218
93 #define OMAP_TAP_DIE_ID_1       0x021C
94 #define OMAP_TAP_DIE_ID_2       0x0220
95 #define OMAP_TAP_DIE_ID_3       0x0224
96
97 #define OMAP_TAP_DIE_ID_44XX_0  0x0200
98 #define OMAP_TAP_DIE_ID_44XX_1  0x0208
99 #define OMAP_TAP_DIE_ID_44XX_2  0x020c
100 #define OMAP_TAP_DIE_ID_44XX_3  0x0210
101
102 #define read_tap_reg(reg)       readl_relaxed(tap_base  + (reg))
103
104 struct omap_id {
105         u16     hawkeye;        /* Silicon type (Hawkeye id) */
106         u8      dev;            /* Device type from production_id reg */
107         u32     type;           /* Combined type id copied to omap_revision */
108 };
109
110 /* Register values to detect the OMAP version */
111 static struct omap_id omap_ids[] __initdata = {
112         { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
113         { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
114         { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
115         { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
116         { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
117         { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
118 };
119
120 static void __iomem *tap_base;
121 static u16 tap_prod_id;
122
123 void omap_get_die_id(struct omap_die_id *odi)
124 {
125         if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
126                 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
127                 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
128                 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
129                 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
130
131                 return;
132         }
133         odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
134         odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
135         odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
136         odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
137 }
138
139 static int __init omap_feed_randpool(void)
140 {
141         struct omap_die_id odi;
142
143         /* Throw the die ID into the entropy pool at boot */
144         omap_get_die_id(&odi);
145         add_device_randomness(&odi, sizeof(odi));
146         return 0;
147 }
148 omap_device_initcall(omap_feed_randpool);
149
150 void __init omap2xxx_check_revision(void)
151 {
152         int i, j;
153         u32 idcode, prod_id;
154         u16 hawkeye;
155         u8  dev_type, rev;
156         struct omap_die_id odi;
157
158         idcode = read_tap_reg(OMAP_TAP_IDCODE);
159         prod_id = read_tap_reg(tap_prod_id);
160         hawkeye = (idcode >> 12) & 0xffff;
161         rev = (idcode >> 28) & 0x0f;
162         dev_type = (prod_id >> 16) & 0x0f;
163         omap_get_die_id(&odi);
164
165         pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
166                  idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
167         pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
168         pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
169                  odi.id_1, (odi.id_1 >> 28) & 0xf);
170         pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
171         pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
172         pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
173                  prod_id, dev_type);
174
175         /* Check hawkeye ids */
176         for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
177                 if (hawkeye == omap_ids[i].hawkeye)
178                         break;
179         }
180
181         if (i == ARRAY_SIZE(omap_ids)) {
182                 printk(KERN_ERR "Unknown OMAP CPU id\n");
183                 return;
184         }
185
186         for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
187                 if (dev_type == omap_ids[j].dev)
188                         break;
189         }
190
191         if (j == ARRAY_SIZE(omap_ids)) {
192                 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
193                        omap_ids[i].type >> 16);
194                 j = i;
195         }
196
197         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
198         sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
199
200         pr_info("%s", soc_name);
201         if ((omap_rev() >> 8) & 0x0f)
202                 pr_cont("%s", soc_rev);
203         pr_cont("\n");
204 }
205
206 #define OMAP3_SHOW_FEATURE(feat)                \
207         if (omap3_has_ ##feat())                \
208                 n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
209
210 static void __init omap3_cpuinfo(void)
211 {
212         const char *cpu_name;
213         char buf[64];
214         int n = 0;
215
216         memset(buf, 0, sizeof(buf));
217
218         /*
219          * OMAP3430 and OMAP3530 are assumed to be same.
220          *
221          * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
222          * on available features. Upon detection, update the CPU id
223          * and CPU class bits.
224          */
225         if (soc_is_omap3630()) {
226                 if (omap3_has_iva() && omap3_has_sgx()) {
227                         cpu_name = (omap3_has_isp()) ? "OMAP3630/DM3730" : "OMAP3621";
228                 } else if (omap3_has_iva()) {
229                         cpu_name = "DM3725";
230                 } else if (omap3_has_sgx()) {
231                         cpu_name = "OMAP3615/AM3715";
232                 } else {
233                         cpu_name = (omap3_has_isp()) ? "AM3703" : "OMAP3611";
234                 }
235         } else if (soc_is_am35xx()) {
236                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
237         } else if (soc_is_ti816x()) {
238                 cpu_name = "TI816X";
239         } else if (soc_is_am335x()) {
240                 cpu_name =  "AM335X";
241         } else if (soc_is_am437x()) {
242                 cpu_name =  "AM437x";
243         } else if (soc_is_ti814x()) {
244                 cpu_name = "TI814X";
245         } else if (omap3_has_iva() && omap3_has_sgx()) {
246                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
247                 cpu_name = "OMAP3430/3530";
248         } else if (omap3_has_iva()) {
249                 cpu_name = "OMAP3525";
250         } else if (omap3_has_sgx()) {
251                 cpu_name = "OMAP3515";
252         } else {
253                 cpu_name = "OMAP3503";
254         }
255
256         scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name);
257
258         /* Print verbose information */
259         n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev);
260
261         OMAP3_SHOW_FEATURE(l2cache);
262         OMAP3_SHOW_FEATURE(iva);
263         OMAP3_SHOW_FEATURE(sgx);
264         OMAP3_SHOW_FEATURE(neon);
265         OMAP3_SHOW_FEATURE(isp);
266         OMAP3_SHOW_FEATURE(192mhz_clk);
267         if (*(buf + n - 1) == ' ')
268                 n--;
269         n += scnprintf(buf + n, sizeof(buf) - n, ")\n");
270         pr_info("%s", buf);
271 }
272
273 #define OMAP3_CHECK_FEATURE(status,feat)                                \
274         if (((status & OMAP3_ ##feat## _MASK)                           \
275                 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
276                 omap_features |= OMAP3_HAS_ ##feat;                     \
277         }
278
279 void __init omap3xxx_check_features(void)
280 {
281         u32 status;
282
283         omap_features = 0;
284
285         status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
286
287         OMAP3_CHECK_FEATURE(status, L2CACHE);
288         OMAP3_CHECK_FEATURE(status, IVA);
289         OMAP3_CHECK_FEATURE(status, SGX);
290         OMAP3_CHECK_FEATURE(status, NEON);
291         OMAP3_CHECK_FEATURE(status, ISP);
292         if (soc_is_omap3630())
293                 omap_features |= OMAP3_HAS_192MHZ_CLK;
294         if (soc_is_omap3430() || soc_is_omap3630())
295                 omap_features |= OMAP3_HAS_IO_WAKEUP;
296         if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
297             omap_rev() == OMAP3430_REV_ES3_1_2)
298                 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
299
300         omap_features |= OMAP3_HAS_SDRC;
301
302         /*
303          * am35x fixups:
304          * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
305          *   reserved and therefore return 0 when read.  Unfortunately,
306          *   OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
307          *   mean that a feature is present even though it isn't so clear
308          *   the incorrectly set feature bits.
309          */
310         if (soc_is_am35xx())
311                 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
312
313         /*
314          * TODO: Get additional info (where applicable)
315          *       e.g. Size of L2 cache.
316          */
317
318         omap3_cpuinfo();
319 }
320
321 void __init omap4xxx_check_features(void)
322 {
323         u32 si_type;
324
325         si_type =
326         (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
327
328         if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
329                 omap_features = OMAP4_HAS_PERF_SILICON;
330 }
331
332 void __init ti81xx_check_features(void)
333 {
334         omap_features = OMAP3_HAS_NEON;
335         omap3_cpuinfo();
336 }
337
338 void __init am33xx_check_features(void)
339 {
340         u32 status;
341
342         omap_features = OMAP3_HAS_NEON;
343
344         status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
345         if (status & AM33XX_SGX_MASK)
346                 omap_features |= OMAP3_HAS_SGX;
347
348         omap3_cpuinfo();
349 }
350
351 void __init omap3xxx_check_revision(void)
352 {
353         const char *cpu_rev;
354         u32 cpuid, idcode;
355         u16 hawkeye;
356         u8 rev;
357
358         /*
359          * We cannot access revision registers on ES1.0.
360          * If the processor type is Cortex-A8 and the revision is 0x0
361          * it means its Cortex r0p0 which is 3430 ES1.0.
362          */
363         cpuid = read_cpuid_id();
364         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
365                 omap_revision = OMAP3430_REV_ES1_0;
366                 cpu_rev = "1.0";
367                 return;
368         }
369
370         /*
371          * Detection for 34xx ES2.0 and above can be done with just
372          * hawkeye and rev. See TRM 1.5.2 Device Identification.
373          * Note that rev does not map directly to our defined processor
374          * revision numbers as ES1.0 uses value 0.
375          */
376         idcode = read_tap_reg(OMAP_TAP_IDCODE);
377         hawkeye = (idcode >> 12) & 0xffff;
378         rev = (idcode >> 28) & 0xff;
379
380         switch (hawkeye) {
381         case 0xb7ae:
382                 /* Handle 34xx/35xx devices */
383                 switch (rev) {
384                 case 0: /* Take care of early samples */
385                 case 1:
386                         omap_revision = OMAP3430_REV_ES2_0;
387                         cpu_rev = "2.0";
388                         break;
389                 case 2:
390                         omap_revision = OMAP3430_REV_ES2_1;
391                         cpu_rev = "2.1";
392                         break;
393                 case 3:
394                         omap_revision = OMAP3430_REV_ES3_0;
395                         cpu_rev = "3.0";
396                         break;
397                 case 4:
398                         omap_revision = OMAP3430_REV_ES3_1;
399                         cpu_rev = "3.1";
400                         break;
401                 case 7:
402                 /* FALLTHROUGH */
403                 default:
404                         /* Use the latest known revision as default */
405                         omap_revision = OMAP3430_REV_ES3_1_2;
406                         cpu_rev = "3.1.2";
407                 }
408                 break;
409         case 0xb868:
410                 /*
411                  * Handle OMAP/AM 3505/3517 devices
412                  *
413                  * Set the device to be OMAP3517 here. Actual device
414                  * is identified later based on the features.
415                  */
416                 switch (rev) {
417                 case 0:
418                         omap_revision = AM35XX_REV_ES1_0;
419                         cpu_rev = "1.0";
420                         break;
421                 case 1:
422                 /* FALLTHROUGH */
423                 default:
424                         omap_revision = AM35XX_REV_ES1_1;
425                         cpu_rev = "1.1";
426                 }
427                 break;
428         case 0xb891:
429                 /* Handle 36xx devices */
430
431                 switch(rev) {
432                 case 0: /* Take care of early samples */
433                         omap_revision = OMAP3630_REV_ES1_0;
434                         cpu_rev = "1.0";
435                         break;
436                 case 1:
437                         omap_revision = OMAP3630_REV_ES1_1;
438                         cpu_rev = "1.1";
439                         break;
440                 case 2:
441                 /* FALLTHROUGH */
442                 default:
443                         omap_revision = OMAP3630_REV_ES1_2;
444                         cpu_rev = "1.2";
445                 }
446                 break;
447         case 0xb81e:
448                 switch (rev) {
449                 case 0:
450                         omap_revision = TI8168_REV_ES1_0;
451                         cpu_rev = "1.0";
452                         break;
453                 case 1:
454                         omap_revision = TI8168_REV_ES1_1;
455                         cpu_rev = "1.1";
456                         break;
457                 case 2:
458                         omap_revision = TI8168_REV_ES2_0;
459                         cpu_rev = "2.0";
460                         break;
461                 case 3:
462                         /* FALLTHROUGH */
463                 default:
464                         omap_revision = TI8168_REV_ES2_1;
465                         cpu_rev = "2.1";
466                 }
467                 break;
468         case 0xb944:
469                 switch (rev) {
470                 case 0:
471                         omap_revision = AM335X_REV_ES1_0;
472                         cpu_rev = "1.0";
473                         break;
474                 case 1:
475                         omap_revision = AM335X_REV_ES2_0;
476                         cpu_rev = "2.0";
477                         break;
478                 case 2:
479                 /* FALLTHROUGH */
480                 default:
481                         omap_revision = AM335X_REV_ES2_1;
482                         cpu_rev = "2.1";
483                         break;
484                 }
485                 break;
486         case 0xb98c:
487                 switch (rev) {
488                 case 0:
489                         omap_revision = AM437X_REV_ES1_0;
490                         cpu_rev = "1.0";
491                         break;
492                 case 1:
493                         omap_revision = AM437X_REV_ES1_1;
494                         cpu_rev = "1.1";
495                         break;
496                 case 2:
497                 /* FALLTHROUGH */
498                 default:
499                         omap_revision = AM437X_REV_ES1_2;
500                         cpu_rev = "1.2";
501                         break;
502                 }
503                 break;
504         case 0xb8f2:
505         case 0xb968:
506                 switch (rev) {
507                 case 0:
508                 /* FALLTHROUGH */
509                 case 1:
510                         omap_revision = TI8148_REV_ES1_0;
511                         cpu_rev = "1.0";
512                         break;
513                 case 2:
514                         omap_revision = TI8148_REV_ES2_0;
515                         cpu_rev = "2.0";
516                         break;
517                 case 3:
518                 /* FALLTHROUGH */
519                 default:
520                         omap_revision = TI8148_REV_ES2_1;
521                         cpu_rev = "2.1";
522                         break;
523                 }
524                 break;
525         default:
526                 /* Unknown default to latest silicon rev as default */
527                 omap_revision = OMAP3630_REV_ES1_2;
528                 cpu_rev = "1.2";
529                 pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
530                         hawkeye);
531         }
532         sprintf(soc_rev, "ES%s", cpu_rev);
533 }
534
535 void __init omap4xxx_check_revision(void)
536 {
537         u32 idcode;
538         u16 hawkeye;
539         u8 rev;
540
541         /*
542          * The IC rev detection is done with hawkeye and rev.
543          * Note that rev does not map directly to defined processor
544          * revision numbers as ES1.0 uses value 0.
545          */
546         idcode = read_tap_reg(OMAP_TAP_IDCODE);
547         hawkeye = (idcode >> 12) & 0xffff;
548         rev = (idcode >> 28) & 0xf;
549
550         /*
551          * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
552          * Use ARM register to detect the correct ES version
553          */
554         if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
555                 idcode = read_cpuid_id();
556                 rev = (idcode & 0xf) - 1;
557         }
558
559         switch (hawkeye) {
560         case 0xb852:
561                 switch (rev) {
562                 case 0:
563                         omap_revision = OMAP4430_REV_ES1_0;
564                         break;
565                 case 1:
566                 default:
567                         omap_revision = OMAP4430_REV_ES2_0;
568                 }
569                 break;
570         case 0xb95c:
571                 switch (rev) {
572                 case 3:
573                         omap_revision = OMAP4430_REV_ES2_1;
574                         break;
575                 case 4:
576                         omap_revision = OMAP4430_REV_ES2_2;
577                         break;
578                 case 6:
579                 default:
580                         omap_revision = OMAP4430_REV_ES2_3;
581                 }
582                 break;
583         case 0xb94e:
584                 switch (rev) {
585                 case 0:
586                         omap_revision = OMAP4460_REV_ES1_0;
587                         break;
588                 case 2:
589                 default:
590                         omap_revision = OMAP4460_REV_ES1_1;
591                         break;
592                 }
593                 break;
594         case 0xb975:
595                 switch (rev) {
596                 case 0:
597                 default:
598                         omap_revision = OMAP4470_REV_ES1_0;
599                         break;
600                 }
601                 break;
602         default:
603                 /* Unknown default to latest silicon rev as default */
604                 omap_revision = OMAP4430_REV_ES2_3;
605         }
606
607         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
608         sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
609                                                 (omap_rev() >> 8) & 0xf);
610         pr_info("%s %s\n", soc_name, soc_rev);
611 }
612
613 void __init omap5xxx_check_revision(void)
614 {
615         u32 idcode;
616         u16 hawkeye;
617         u8 rev;
618
619         idcode = read_tap_reg(OMAP_TAP_IDCODE);
620         hawkeye = (idcode >> 12) & 0xffff;
621         rev = (idcode >> 28) & 0xff;
622         switch (hawkeye) {
623         case 0xb942:
624                 switch (rev) {
625                 case 0:
626                         /* No support for ES1.0 Test chip */
627                         BUG();
628                 case 1:
629                 default:
630                         omap_revision = OMAP5430_REV_ES2_0;
631                 }
632                 break;
633
634         case 0xb998:
635                 switch (rev) {
636                 case 0:
637                         /* No support for ES1.0 Test chip */
638                         BUG();
639                 case 1:
640                 default:
641                         omap_revision = OMAP5432_REV_ES2_0;
642                 }
643                 break;
644
645         default:
646                 /* Unknown default to latest silicon rev as default*/
647                 omap_revision = OMAP5430_REV_ES2_0;
648         }
649
650         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
651         sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
652
653         pr_info("%s %s\n", soc_name, soc_rev);
654 }
655
656 void __init dra7xxx_check_revision(void)
657 {
658         u32 idcode;
659         u16 hawkeye;
660         u8 rev, package;
661         struct omap_die_id odi;
662
663         omap_get_die_id(&odi);
664         package = (odi.id_2 >> 16) & 0x3;
665         idcode = read_tap_reg(OMAP_TAP_IDCODE);
666         hawkeye = (idcode >> 12) & 0xffff;
667         rev = (idcode >> 28) & 0xff;
668         switch (hawkeye) {
669         case 0xbb50:
670                 switch (rev) {
671                 case 0:
672                 default:
673                         switch (package) {
674                         case 0x2:
675                                 omap_revision = DRA762_ABZ_REV_ES1_0;
676                                 break;
677                         case 0x3:
678                                 omap_revision = DRA762_ACD_REV_ES1_0;
679                                 break;
680                         default:
681                                 omap_revision = DRA762_REV_ES1_0;
682                                 break;
683                         }
684                         break;
685                 }
686                 break;
687
688         case 0xb990:
689                 switch (rev) {
690                 case 0:
691                         omap_revision = DRA752_REV_ES1_0;
692                         break;
693                 case 1:
694                         omap_revision = DRA752_REV_ES1_1;
695                         break;
696                 case 2:
697                 default:
698                         omap_revision = DRA752_REV_ES2_0;
699                         break;
700                 }
701                 break;
702
703         case 0xb9bc:
704                 switch (rev) {
705                 case 0:
706                         omap_revision = DRA722_REV_ES1_0;
707                         break;
708                 case 1:
709                         omap_revision = DRA722_REV_ES2_0;
710                         break;
711                 case 2:
712                 default:
713                         omap_revision = DRA722_REV_ES2_1;
714                         break;
715                 }
716                 break;
717
718         default:
719                 /* Unknown default to latest silicon rev as default*/
720                 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
721                         __func__, idcode, hawkeye, rev);
722                 omap_revision = DRA752_REV_ES2_0;
723         }
724
725         sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
726         sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
727                 (omap_rev() >> 8) & 0xf);
728
729         pr_info("%s %s\n", soc_name, soc_rev);
730 }
731
732 /*
733  * Set up things for map_io and processor detection later on. Gets called
734  * pretty much first thing from board init. For multi-omap, this gets
735  * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
736  * detect the exact revision later on in omap2_detect_revision() once map_io
737  * is done.
738  */
739 void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
740 {
741         omap_revision = class;
742         tap_base = tap;
743
744         /* XXX What is this intended to do? */
745         if (soc_is_omap34xx())
746                 tap_prod_id = 0x0210;
747         else
748                 tap_prod_id = 0x0208;
749 }
750
751 #ifdef CONFIG_SOC_BUS
752
753 static const char * const omap_types[] = {
754         [OMAP2_DEVICE_TYPE_TEST]        = "TST",
755         [OMAP2_DEVICE_TYPE_EMU]         = "EMU",
756         [OMAP2_DEVICE_TYPE_SEC]         = "HS",
757         [OMAP2_DEVICE_TYPE_GP]          = "GP",
758         [OMAP2_DEVICE_TYPE_BAD]         = "BAD",
759 };
760
761 static const char * __init omap_get_family(void)
762 {
763         if (soc_is_omap24xx())
764                 return kasprintf(GFP_KERNEL, "OMAP2");
765         else if (soc_is_omap34xx())
766                 return kasprintf(GFP_KERNEL, "OMAP3");
767         else if (soc_is_omap44xx())
768                 return kasprintf(GFP_KERNEL, "OMAP4");
769         else if (soc_is_omap54xx())
770                 return kasprintf(GFP_KERNEL, "OMAP5");
771         else if (soc_is_am33xx() || soc_is_am335x())
772                 return kasprintf(GFP_KERNEL, "AM33xx");
773         else if (soc_is_am43xx())
774                 return kasprintf(GFP_KERNEL, "AM43xx");
775         else if (soc_is_dra7xx())
776                 return kasprintf(GFP_KERNEL, "DRA7");
777         else
778                 return kasprintf(GFP_KERNEL, "Unknown");
779 }
780
781 static ssize_t omap_get_type(struct device *dev,
782                                         struct device_attribute *attr,
783                                         char *buf)
784 {
785         return sprintf(buf, "%s\n", omap_types[omap_type()]);
786 }
787
788 static struct device_attribute omap_soc_attr =
789         __ATTR(type,  S_IRUGO, omap_get_type,  NULL);
790
791 void __init omap_soc_device_init(void)
792 {
793         struct device *parent;
794         struct soc_device *soc_dev;
795         struct soc_device_attribute *soc_dev_attr;
796
797         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
798         if (!soc_dev_attr)
799                 return;
800
801         soc_dev_attr->machine  = soc_name;
802         soc_dev_attr->family   = omap_get_family();
803         if (!soc_dev_attr->family) {
804                 kfree(soc_dev_attr);
805                 return;
806         }
807         soc_dev_attr->revision = soc_rev;
808
809         soc_dev = soc_device_register(soc_dev_attr);
810         if (IS_ERR(soc_dev)) {
811                 kfree(soc_dev_attr->family);
812                 kfree(soc_dev_attr);
813                 return;
814         }
815
816         parent = soc_device_to_device(soc_dev);
817         device_create_file(parent, &omap_soc_attr);
818 }
819 #endif /* CONFIG_SOC_BUS */