2 * linux/arch/arm/mach-omap2/gpmc-onenand.c
4 * Copyright (C) 2006 - 2009 Nokia Corporation
5 * Contacts: Juha Yrjola
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/string.h>
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/mtd/onenand_regs.h>
18 #include <linux/omap-gpmc.h>
19 #include <linux/platform_data/mtd-onenand-omap2.h>
20 #include <linux/err.h>
22 #include <asm/mach/flash.h>
26 #define ONENAND_IO_SIZE SZ_128K
28 #define ONENAND_FLAG_SYNCREAD (1 << 0)
29 #define ONENAND_FLAG_SYNCWRITE (1 << 1)
30 #define ONENAND_FLAG_HF (1 << 2)
31 #define ONENAND_FLAG_VHF (1 << 3)
33 static unsigned onenand_flags;
34 static unsigned latency;
36 static struct omap_onenand_platform_data *gpmc_onenand_data;
38 static struct resource gpmc_onenand_resource = {
39 .flags = IORESOURCE_MEM,
42 static struct platform_device gpmc_onenand_device = {
43 .name = "omap2-onenand",
46 .resource = &gpmc_onenand_resource,
49 static struct gpmc_settings onenand_async = {
50 .device_width = GPMC_DEVWIDTH_16BIT,
51 .mux_add_data = GPMC_MUX_AD,
54 static struct gpmc_settings onenand_sync = {
57 .burst_len = GPMC_BURST_16,
58 .device_width = GPMC_DEVWIDTH_16BIT,
59 .mux_add_data = GPMC_MUX_AD,
63 static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
65 struct gpmc_device_timings dev_t;
67 const int t_avdp = 12;
68 const int t_aavdh = 7;
72 const int t_cez = 20; /* max of t_cez, t_oez */
76 memset(&dev_t, 0, sizeof(dev_t));
78 dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
79 dev_t.t_avdp_w = dev_t.t_avdp_r;
80 dev_t.t_aavdh = t_aavdh * 1000;
81 dev_t.t_aa = t_aa * 1000;
82 dev_t.t_ce = t_ce * 1000;
83 dev_t.t_oe = t_oe * 1000;
84 dev_t.t_cez_r = t_cez * 1000;
85 dev_t.t_cez_w = dev_t.t_cez_r;
86 dev_t.t_wpl = t_wpl * 1000;
87 dev_t.t_wph = t_wph * 1000;
89 gpmc_calc_timings(t, &onenand_async, &dev_t);
92 static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
96 /* Ensure sync read and sync write are disabled */
97 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
98 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
99 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
102 static void set_onenand_cfg(void __iomem *onenand_base)
104 u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
106 reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
107 ONENAND_SYS_CFG1_BL_16;
108 if (onenand_flags & ONENAND_FLAG_SYNCREAD)
109 reg |= ONENAND_SYS_CFG1_SYNC_READ;
111 reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
112 if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
113 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
115 reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
116 if (onenand_flags & ONENAND_FLAG_HF)
117 reg |= ONENAND_SYS_CFG1_HF;
119 reg &= ~ONENAND_SYS_CFG1_HF;
120 if (onenand_flags & ONENAND_FLAG_VHF)
121 reg |= ONENAND_SYS_CFG1_VHF;
123 reg &= ~ONENAND_SYS_CFG1_VHF;
125 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
128 static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
129 void __iomem *onenand_base)
131 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
134 switch ((ver >> 4) & 0xf) {
151 pr_err("onenand rate not detected, bad GPMC async timings?\n");
158 static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
162 struct gpmc_device_timings dev_t;
163 const int t_cer = 15;
164 const int t_avdp = 12;
165 const int t_cez = 20; /* max of t_cez, t_oez */
166 const int t_wpl = 40;
167 const int t_wph = 30;
168 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
169 int div, gpmc_clk_ns;
171 if (flags & ONENAND_SYNC_READ)
172 onenand_flags = ONENAND_FLAG_SYNCREAD;
173 else if (flags & ONENAND_SYNC_READWRITE)
174 onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
178 min_gpmc_clk_period = 9600; /* 104 MHz */
187 min_gpmc_clk_period = 12000; /* 83 MHz */
196 min_gpmc_clk_period = 15000; /* 66 MHz */
205 min_gpmc_clk_period = 18500; /* 54 MHz */
212 onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
216 div = gpmc_calc_divider(min_gpmc_clk_period);
217 gpmc_clk_ns = gpmc_ticks_to_ns(div);
218 if (gpmc_clk_ns < 15) /* >66MHz */
219 onenand_flags |= ONENAND_FLAG_HF;
221 onenand_flags &= ~ONENAND_FLAG_HF;
222 if (gpmc_clk_ns < 12) /* >83MHz */
223 onenand_flags |= ONENAND_FLAG_VHF;
225 onenand_flags &= ~ONENAND_FLAG_VHF;
226 if (onenand_flags & ONENAND_FLAG_VHF)
228 else if (onenand_flags & ONENAND_FLAG_HF)
230 else if (gpmc_clk_ns >= 25) /* 40 MHz*/
235 /* Set synchronous read timings */
236 memset(&dev_t, 0, sizeof(dev_t));
238 if (onenand_flags & ONENAND_FLAG_SYNCREAD)
239 onenand_sync.sync_read = true;
240 if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
241 onenand_sync.sync_write = true;
242 onenand_sync.burst_write = true;
244 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
245 dev_t.t_wpl = t_wpl * 1000;
246 dev_t.t_wph = t_wph * 1000;
247 dev_t.t_aavdh = t_aavdh * 1000;
249 dev_t.ce_xdelay = true;
250 dev_t.avd_xdelay = true;
251 dev_t.oe_xdelay = true;
252 dev_t.we_xdelay = true;
253 dev_t.clk = min_gpmc_clk_period;
254 dev_t.t_bacc = dev_t.clk;
255 dev_t.t_ces = t_ces * 1000;
256 dev_t.t_avds = t_avds * 1000;
257 dev_t.t_avdh = t_avdh * 1000;
258 dev_t.t_ach = t_ach * 1000;
259 dev_t.cyc_iaa = (latency + 1);
260 dev_t.t_cez_r = t_cez * 1000;
261 dev_t.t_cez_w = dev_t.t_cez_r;
262 dev_t.cyc_aavdh_oe = 1;
263 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
265 gpmc_calc_timings(t, &onenand_sync, &dev_t);
268 static int omap2_onenand_setup_async(void __iomem *onenand_base)
270 struct gpmc_timings t;
274 * Note that we need to keep sync_write set for the call to
275 * omap2_onenand_set_async_mode() to work to detect the onenand
276 * supported clock rate for the sync timings.
278 if (gpmc_onenand_data->of_node) {
279 gpmc_read_settings_dt(gpmc_onenand_data->of_node,
281 if (onenand_async.sync_read || onenand_async.sync_write) {
282 if (onenand_async.sync_write)
283 gpmc_onenand_data->flags |=
284 ONENAND_SYNC_READWRITE;
286 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
287 onenand_async.sync_read = false;
291 onenand_async.sync_write = true;
292 omap2_onenand_calc_async_timings(&t);
294 ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
298 ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async);
302 omap2_onenand_set_async_mode(onenand_base);
307 static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
309 int ret, freq = *freq_ptr;
310 struct gpmc_timings t;
313 /* Very first call freq is not known */
314 freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
317 set_onenand_cfg(onenand_base);
320 if (gpmc_onenand_data->of_node) {
321 gpmc_read_settings_dt(gpmc_onenand_data->of_node,
325 * FIXME: Appears to be legacy code from initial ONENAND commit.
326 * Unclear what boards this is for and if this can be removed.
328 if (!cpu_is_omap34xx())
329 onenand_sync.wait_on_read = true;
332 omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
334 ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
338 ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync);
342 set_onenand_cfg(onenand_base);
349 static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
351 struct device *dev = &gpmc_onenand_device.dev;
352 unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
355 ret = omap2_onenand_setup_async(onenand_base);
357 dev_err(dev, "unable to set to async mode\n");
361 if (!(gpmc_onenand_data->flags & l))
364 ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
366 dev_err(dev, "unable to set to sync mode\n");
370 int gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
373 struct device *dev = &gpmc_onenand_device.dev;
375 gpmc_onenand_data = _onenand_data;
376 gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
377 gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
379 if (cpu_is_omap24xx() &&
380 (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
381 dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
382 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
383 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
386 if (cpu_is_omap34xx())
387 gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
389 gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
391 err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
392 (unsigned long *)&gpmc_onenand_resource.start);
394 dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
395 gpmc_onenand_data->cs, err);
399 gpmc_onenand_resource.end = gpmc_onenand_resource.start +
402 err = platform_device_register(&gpmc_onenand_device);
404 dev_err(dev, "Unable to register OneNAND device\n");
405 gpmc_cs_free(gpmc_onenand_data->cs);