2 * OMAP2plus display device setup / initialization.
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25 #include <linux/delay.h>
27 #include <linux/of_platform.h>
28 #include <linux/slab.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/regmap.h>
32 #include <linux/platform_data/omapdss.h>
33 #include "omap_hwmod.h"
34 #include "omap_device.h"
44 #define DISPC_CONTROL 0x0040
45 #define DISPC_CONTROL2 0x0238
46 #define DISPC_CONTROL3 0x0848
47 #define DISPC_IRQSTATUS 0x0018
49 #define DSS_SYSCONFIG 0x10
50 #define DSS_SYSSTATUS 0x14
51 #define DSS_CONTROL 0x40
52 #define DSS_SDI_CONTROL 0x44
53 #define DSS_PLL_CONTROL 0x48
55 #define LCD_EN_MASK (0x1 << 0)
56 #define DIGIT_EN_MASK (0x1 << 1)
58 #define FRAMEDONE_IRQ_SHIFT 0
59 #define EVSYNC_EVEN_IRQ_SHIFT 2
60 #define EVSYNC_ODD_IRQ_SHIFT 3
61 #define FRAMEDONE2_IRQ_SHIFT 22
62 #define FRAMEDONE3_IRQ_SHIFT 30
63 #define FRAMEDONETV_IRQ_SHIFT 24
66 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
67 * reset before deciding that something has gone wrong
69 #define FRAMEDONE_IRQ_TIMEOUT 100
71 static struct platform_device omap_display_device = {
75 .platform_data = NULL,
79 struct omap_dss_hwmod_data {
85 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
86 { "dss_core", "omapdss_dss", -1 },
87 { "dss_dispc", "omapdss_dispc", -1 },
88 { "dss_rfbi", "omapdss_rfbi", -1 },
89 { "dss_venc", "omapdss_venc", -1 },
92 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
93 { "dss_core", "omapdss_dss", -1 },
94 { "dss_dispc", "omapdss_dispc", -1 },
95 { "dss_rfbi", "omapdss_rfbi", -1 },
96 { "dss_venc", "omapdss_venc", -1 },
97 { "dss_dsi1", "omapdss_dsi", 0 },
100 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
101 { "dss_core", "omapdss_dss", -1 },
102 { "dss_dispc", "omapdss_dispc", -1 },
103 { "dss_rfbi", "omapdss_rfbi", -1 },
104 { "dss_dsi1", "omapdss_dsi", 0 },
105 { "dss_dsi2", "omapdss_dsi", 1 },
106 { "dss_hdmi", "omapdss_hdmi", -1 },
109 #define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
111 static struct regmap *omap4_dsi_mux_syscon;
113 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
115 u32 enable_mask, enable_shift;
116 u32 pipd_mask, pipd_shift;
121 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
122 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
123 pipd_mask = OMAP4_DSI1_PIPD_MASK;
124 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
125 } else if (dsi_id == 1) {
126 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
127 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
128 pipd_mask = OMAP4_DSI2_PIPD_MASK;
129 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
134 ret = regmap_read(omap4_dsi_mux_syscon,
135 OMAP4_DSIPHY_SYSCON_OFFSET,
143 reg |= (lanes << enable_shift) & enable_mask;
144 reg |= (lanes << pipd_shift) & pipd_mask;
146 regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
151 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
153 if (cpu_is_omap44xx())
154 return omap4_dsi_mux_pads(dsi_id, lane_mask);
159 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
161 if (cpu_is_omap44xx())
162 omap4_dsi_mux_pads(dsi_id, 0);
165 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
167 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
170 static struct platform_device *create_dss_pdev(const char *pdev_name,
171 int pdev_id, const char *oh_name, void *pdata, int pdata_len,
172 struct platform_device *parent)
174 struct platform_device *pdev;
175 struct omap_device *od;
176 struct omap_hwmod *ohs[1];
177 struct omap_hwmod *oh;
180 oh = omap_hwmod_lookup(oh_name);
182 pr_err("Could not look up %s\n", oh_name);
187 pdev = platform_device_alloc(pdev_name, pdev_id);
189 pr_err("Could not create pdev for %s\n", pdev_name);
195 pdev->dev.parent = &parent->dev;
198 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
200 dev_set_name(&pdev->dev, "%s", pdev->name);
203 od = omap_device_alloc(pdev, ohs, 1);
205 pr_err("Could not alloc omap_device for %s\n", pdev_name);
210 r = platform_device_add_data(pdev, pdata, pdata_len);
212 pr_err("Could not set pdata for %s\n", pdev_name);
216 r = omap_device_register(pdev);
218 pr_err("Could not register omap_device for %s\n", pdev_name);
228 static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
229 int pdev_id, void *pdata, int pdata_len,
230 struct platform_device *parent)
232 struct platform_device *pdev;
235 pdev = platform_device_alloc(pdev_name, pdev_id);
237 pr_err("Could not create pdev for %s\n", pdev_name);
243 pdev->dev.parent = &parent->dev;
246 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
248 dev_set_name(&pdev->dev, "%s", pdev->name);
250 r = platform_device_add_data(pdev, pdata, pdata_len);
252 pr_err("Could not set pdata for %s\n", pdev_name);
256 r = platform_device_add(pdev);
258 pr_err("Could not register platform_device for %s\n", pdev_name);
268 static enum omapdss_version __init omap_display_get_version(void)
270 if (cpu_is_omap24xx())
271 return OMAPDSS_VER_OMAP24xx;
272 else if (cpu_is_omap3630())
273 return OMAPDSS_VER_OMAP3630;
274 else if (cpu_is_omap34xx()) {
275 if (soc_is_am35xx()) {
276 return OMAPDSS_VER_AM35xx;
278 if (omap_rev() < OMAP3430_REV_ES3_0)
279 return OMAPDSS_VER_OMAP34xx_ES1;
281 return OMAPDSS_VER_OMAP34xx_ES3;
283 } else if (omap_rev() == OMAP4430_REV_ES1_0)
284 return OMAPDSS_VER_OMAP4430_ES1;
285 else if (omap_rev() == OMAP4430_REV_ES2_0 ||
286 omap_rev() == OMAP4430_REV_ES2_1 ||
287 omap_rev() == OMAP4430_REV_ES2_2)
288 return OMAPDSS_VER_OMAP4430_ES2;
289 else if (cpu_is_omap44xx())
290 return OMAPDSS_VER_OMAP4;
291 else if (soc_is_omap54xx())
292 return OMAPDSS_VER_OMAP5;
293 else if (soc_is_am43xx())
294 return OMAPDSS_VER_AM43xx;
295 else if (soc_is_dra7xx())
296 return OMAPDSS_VER_DRA7xx;
298 return OMAPDSS_VER_UNKNOWN;
301 int __init omap_display_init(struct omap_dss_board_info *board_data)
304 struct platform_device *pdev;
306 const struct omap_dss_hwmod_data *curr_dss_hwmod;
307 struct platform_device *dss_pdev;
308 enum omapdss_version ver;
310 /* create omapdss device */
312 ver = omap_display_get_version();
314 if (ver == OMAPDSS_VER_UNKNOWN) {
315 pr_err("DSS not supported on this SoC\n");
319 board_data->version = ver;
320 board_data->dsi_enable_pads = omap_dsi_enable_pads;
321 board_data->dsi_disable_pads = omap_dsi_disable_pads;
322 board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
324 omap_display_device.dev.platform_data = board_data;
326 r = platform_device_register(&omap_display_device);
328 pr_err("Unable to register omapdss device\n");
332 /* create devices for dss hwmods */
334 if (cpu_is_omap24xx()) {
335 curr_dss_hwmod = omap2_dss_hwmod_data;
336 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
337 } else if (cpu_is_omap34xx()) {
338 curr_dss_hwmod = omap3_dss_hwmod_data;
339 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
341 curr_dss_hwmod = omap4_dss_hwmod_data;
342 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
346 * First create the pdev for dss_core, which is used as a parent device
347 * by the other dss pdevs. Note: dss_core has to be the first item in
350 dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
351 curr_dss_hwmod[0].id,
352 curr_dss_hwmod[0].oh_name,
353 board_data, sizeof(*board_data),
356 if (IS_ERR(dss_pdev)) {
357 pr_err("Could not build omap_device for %s\n",
358 curr_dss_hwmod[0].oh_name);
360 return PTR_ERR(dss_pdev);
363 for (i = 1; i < oh_count; i++) {
364 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
365 curr_dss_hwmod[i].id,
366 curr_dss_hwmod[i].oh_name,
367 board_data, sizeof(*board_data),
371 pr_err("Could not build omap_device for %s\n",
372 curr_dss_hwmod[i].oh_name);
374 return PTR_ERR(pdev);
378 /* Create devices for DPI and SDI */
380 pdev = create_simple_dss_pdev("omapdss_dpi", 0,
381 board_data, sizeof(*board_data), dss_pdev);
383 pr_err("Could not build platform_device for omapdss_dpi\n");
384 return PTR_ERR(pdev);
387 if (cpu_is_omap34xx()) {
388 pdev = create_simple_dss_pdev("omapdss_sdi", 0,
389 board_data, sizeof(*board_data), dss_pdev);
391 pr_err("Could not build platform_device for omapdss_sdi\n");
392 return PTR_ERR(pdev);
396 /* create DRM device */
399 pr_err("Unable to register omapdrm device\n");
403 /* create vrfb device */
404 r = omap_init_vrfb();
406 pr_err("Unable to register omapvrfb device\n");
410 /* create FB device */
413 pr_err("Unable to register omapfb device\n");
417 /* create V4L2 display device */
418 r = omap_init_vout();
420 pr_err("Unable to register omap_vout device\n");
427 static void dispc_disable_outputs(void)
430 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
432 struct omap_dss_dispc_dev_attr *da;
433 struct omap_hwmod *oh;
435 oh = omap_hwmod_lookup("dss_dispc");
437 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
442 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
446 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
448 /* store value of LCDENABLE and DIGITENABLE bits */
449 v = omap_hwmod_read(oh, DISPC_CONTROL);
450 lcd_en = v & LCD_EN_MASK;
451 digit_en = v & DIGIT_EN_MASK;
453 /* store value of LCDENABLE for LCD2 */
454 if (da->manager_count > 2) {
455 v = omap_hwmod_read(oh, DISPC_CONTROL2);
456 lcd2_en = v & LCD_EN_MASK;
459 /* store value of LCDENABLE for LCD3 */
460 if (da->manager_count > 3) {
461 v = omap_hwmod_read(oh, DISPC_CONTROL3);
462 lcd3_en = v & LCD_EN_MASK;
465 if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
466 return; /* no managers currently enabled */
469 * If any manager was enabled, we need to disable it before
470 * DSS clocks are disabled or DISPC module is reset
473 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
476 if (da->has_framedonetv_irq) {
477 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
479 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
480 1 << EVSYNC_ODD_IRQ_SHIFT;
485 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
487 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
490 * clear any previous FRAMEDONE, FRAMEDONETV,
491 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
493 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
495 /* disable LCD and TV managers */
496 v = omap_hwmod_read(oh, DISPC_CONTROL);
497 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
498 omap_hwmod_write(v, oh, DISPC_CONTROL);
500 /* disable LCD2 manager */
501 if (da->manager_count > 2) {
502 v = omap_hwmod_read(oh, DISPC_CONTROL2);
504 omap_hwmod_write(v, oh, DISPC_CONTROL2);
507 /* disable LCD3 manager */
508 if (da->manager_count > 3) {
509 v = omap_hwmod_read(oh, DISPC_CONTROL3);
511 omap_hwmod_write(v, oh, DISPC_CONTROL3);
515 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
518 if (i > FRAMEDONE_IRQ_TIMEOUT) {
519 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
526 int omap_dss_reset(struct omap_hwmod *oh)
528 struct omap_hwmod_opt_clk *oc;
532 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
533 pr_err("dss_core: hwmod data doesn't contain reset data\n");
537 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
539 clk_prepare_enable(oc->_clk);
541 dispc_disable_outputs();
543 /* clear SDI registers */
544 if (cpu_is_omap3430()) {
545 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
546 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
550 * clear DSS_CONTROL register to switch DSS clock sources to
553 omap_hwmod_write(0x0, oh, DSS_CONTROL);
555 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
556 & SYSS_RESETDONE_MASK),
557 MAX_MODULE_SOFTRESET_WAIT, c);
559 if (c == MAX_MODULE_SOFTRESET_WAIT)
560 pr_warn("dss_core: waiting for reset to finish failed\n");
562 pr_debug("dss_core: softreset done\n");
564 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
566 clk_disable_unprepare(oc->_clk);
568 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
573 void __init omapdss_early_init_of(void)
578 static const char * const omapdss_compat_names[] __initconst = {
586 struct device_node * __init omapdss_find_dss_of_node(void)
588 struct device_node *node;
591 for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
592 node = of_find_compatible_node(NULL, NULL,
593 omapdss_compat_names[i]);
601 int __init omapdss_init_of(void)
604 enum omapdss_version ver;
605 struct device_node *node;
606 struct platform_device *pdev;
608 static struct omap_dss_board_info board_data = {
609 .dsi_enable_pads = omap_dsi_enable_pads,
610 .dsi_disable_pads = omap_dsi_disable_pads,
611 .set_min_bus_tput = omap_dss_set_min_bus_tput,
614 /* only create dss helper devices if dss is enabled in the .dts */
616 node = omapdss_find_dss_of_node();
620 if (!of_device_is_available(node))
623 ver = omap_display_get_version();
625 if (ver == OMAPDSS_VER_UNKNOWN) {
626 pr_err("DSS not supported on this SoC\n");
630 pdev = of_find_device_by_node(node);
633 pr_err("Unable to find DSS platform device\n");
637 r = of_platform_populate(node, NULL, NULL, &pdev->dev);
639 pr_err("Unable to populate DSS submodule devices\n");
643 board_data.version = ver;
645 omap_display_device.dev.platform_data = &board_data;
647 r = platform_device_register(&omap_display_device);
649 pr_err("Unable to register omapdss device\n");
653 /* create DRM device */
656 pr_err("Unable to register omapdrm device\n");
660 /* create vrfb device */
661 r = omap_init_vrfb();
663 pr_err("Unable to register omapvrfb device\n");
667 /* create FB device */
670 pr_err("Unable to register omapfb device\n");
674 /* create V4L2 display device */
675 r = omap_init_vout();
677 pr_err("Unable to register omap_vout device\n");
681 /* add DSI info for omap4 */
682 node = of_find_node_by_name(NULL, "omap4_padconf_global");
684 omap4_dsi_mux_syscon = syscon_node_to_regmap(node);