arch/arm/mach-omap2/clockdomains7xx_data.c

   1 /*
   2  * DRA7xx Clock domains framework
   3  *
   4  * Copyright (C) 2009-2013 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2011 Nokia Corporation
   6  *
   7  * Generated by code originally written by:
   8  * Abhijit Pagare (abhijitpagare@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  * Paul Walmsley (paul@pwsan.com)
  11  *
  12  * This file is automatically generated from the OMAP hardware databases.
  13  * We respectfully ask that any modifications to this file be coordinated
  14  * with the public linux-omap@vger.kernel.org mailing list and the
  15  * authors above to ensure that the autogeneration scripts are kept
  16  * up-to-date with the file contents.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/io.h>
  25
  26 #include "clockdomain.h"
  27 #include "cm1_7xx.h"
  28 #include "cm2_7xx.h"
  29
  30 #include "cm-regbits-7xx.h"
  31 #include "prm7xx.h"
  32 #include "prcm44xx.h"
  33 #include "prcm_mpu7xx.h"
  34
  35 /* Static Dependencies for DRA7xx Clock Domains */
  36
  37 static struct clkdm_dep cam_wkup_sleep_deps[] = {
  38         { .clkdm_name = "emif_clkdm" },
  39         { NULL },
  40 };
  41
  42 static struct clkdm_dep dma_wkup_sleep_deps[] = {
  43         { .clkdm_name = "dss_clkdm" },
  44         { .clkdm_name = "emif_clkdm" },
  45         { .clkdm_name = "ipu_clkdm" },
  46         { .clkdm_name = "ipu1_clkdm" },
  47         { .clkdm_name = "ipu2_clkdm" },
  48         { .clkdm_name = "iva_clkdm" },
  49         { .clkdm_name = "l3init_clkdm" },
  50         { .clkdm_name = "l4cfg_clkdm" },
  51         { .clkdm_name = "l4per_clkdm" },
  52         { .clkdm_name = "l4per2_clkdm" },
  53         { .clkdm_name = "l4per3_clkdm" },
  54         { .clkdm_name = "l4sec_clkdm" },
  55         { .clkdm_name = "pcie_clkdm" },
  56         { .clkdm_name = "wkupaon_clkdm" },
  57         { NULL },
  58 };
  59
  60 static struct clkdm_dep dsp1_wkup_sleep_deps[] = {
  61         { .clkdm_name = "atl_clkdm" },
  62         { .clkdm_name = "cam_clkdm" },
  63         { .clkdm_name = "dsp2_clkdm" },
  64         { .clkdm_name = "dss_clkdm" },
  65         { .clkdm_name = "emif_clkdm" },
  66         { .clkdm_name = "eve1_clkdm" },
  67         { .clkdm_name = "eve2_clkdm" },
  68         { .clkdm_name = "eve3_clkdm" },
  69         { .clkdm_name = "eve4_clkdm" },
  70         { .clkdm_name = "gmac_clkdm" },
  71         { .clkdm_name = "gpu_clkdm" },
  72         { .clkdm_name = "ipu_clkdm" },
  73         { .clkdm_name = "ipu1_clkdm" },
  74         { .clkdm_name = "ipu2_clkdm" },
  75         { .clkdm_name = "iva_clkdm" },
  76         { .clkdm_name = "l3init_clkdm" },
  77         { .clkdm_name = "l4per_clkdm" },
  78         { .clkdm_name = "l4per2_clkdm" },
  79         { .clkdm_name = "l4per3_clkdm" },
  80         { .clkdm_name = "l4sec_clkdm" },
  81         { .clkdm_name = "pcie_clkdm" },
  82         { .clkdm_name = "vpe_clkdm" },
  83         { .clkdm_name = "wkupaon_clkdm" },
  84         { NULL },
  85 };
  86
  87 static struct clkdm_dep dsp2_wkup_sleep_deps[] = {
  88         { .clkdm_name = "atl_clkdm" },
  89         { .clkdm_name = "cam_clkdm" },
  90         { .clkdm_name = "dsp1_clkdm" },
  91         { .clkdm_name = "dss_clkdm" },
  92         { .clkdm_name = "emif_clkdm" },
  93         { .clkdm_name = "eve1_clkdm" },
  94         { .clkdm_name = "eve2_clkdm" },
  95         { .clkdm_name = "eve3_clkdm" },
  96         { .clkdm_name = "eve4_clkdm" },
  97         { .clkdm_name = "gmac_clkdm" },
  98         { .clkdm_name = "gpu_clkdm" },
  99         { .clkdm_name = "ipu_clkdm" },
 100         { .clkdm_name = "ipu1_clkdm" },
 101         { .clkdm_name = "ipu2_clkdm" },
 102         { .clkdm_name = "iva_clkdm" },
 103         { .clkdm_name = "l3init_clkdm" },
 104         { .clkdm_name = "l4per_clkdm" },
 105         { .clkdm_name = "l4per2_clkdm" },
 106         { .clkdm_name = "l4per3_clkdm" },
 107         { .clkdm_name = "l4sec_clkdm" },
 108         { .clkdm_name = "pcie_clkdm" },
 109         { .clkdm_name = "vpe_clkdm" },
 110         { .clkdm_name = "wkupaon_clkdm" },
 111         { NULL },
 112 };
 113
 114 static struct clkdm_dep dss_wkup_sleep_deps[] = {
 115         { .clkdm_name = "emif_clkdm" },
 116         { .clkdm_name = "iva_clkdm" },
 117         { NULL },
 118 };
 119
 120 static struct clkdm_dep eve1_wkup_sleep_deps[] = {
 121         { .clkdm_name = "emif_clkdm" },
 122         { .clkdm_name = "eve2_clkdm" },
 123         { .clkdm_name = "eve3_clkdm" },
 124         { .clkdm_name = "eve4_clkdm" },
 125         { .clkdm_name = "iva_clkdm" },
 126         { NULL },
 127 };
 128
 129 static struct clkdm_dep eve2_wkup_sleep_deps[] = {
 130         { .clkdm_name = "emif_clkdm" },
 131         { .clkdm_name = "eve1_clkdm" },
 132         { .clkdm_name = "eve3_clkdm" },
 133         { .clkdm_name = "eve4_clkdm" },
 134         { .clkdm_name = "iva_clkdm" },
 135         { NULL },
 136 };
 137
 138 static struct clkdm_dep eve3_wkup_sleep_deps[] = {
 139         { .clkdm_name = "emif_clkdm" },
 140         { .clkdm_name = "eve1_clkdm" },
 141         { .clkdm_name = "eve2_clkdm" },
 142         { .clkdm_name = "eve4_clkdm" },
 143         { .clkdm_name = "iva_clkdm" },
 144         { NULL },
 145 };
 146
 147 static struct clkdm_dep eve4_wkup_sleep_deps[] = {
 148         { .clkdm_name = "emif_clkdm" },
 149         { .clkdm_name = "eve1_clkdm" },
 150         { .clkdm_name = "eve2_clkdm" },
 151         { .clkdm_name = "eve3_clkdm" },
 152         { .clkdm_name = "iva_clkdm" },
 153         { NULL },
 154 };
 155
 156 static struct clkdm_dep gmac_wkup_sleep_deps[] = {
 157         { .clkdm_name = "emif_clkdm" },
 158         { .clkdm_name = "l4per2_clkdm" },
 159         { NULL },
 160 };
 161
 162 static struct clkdm_dep gpu_wkup_sleep_deps[] = {
 163         { .clkdm_name = "emif_clkdm" },
 164         { .clkdm_name = "iva_clkdm" },
 165         { NULL },
 166 };
 167
 168 static struct clkdm_dep ipu1_wkup_sleep_deps[] = {
 169         { .clkdm_name = "atl_clkdm" },
 170         { .clkdm_name = "dsp1_clkdm" },
 171         { .clkdm_name = "dsp2_clkdm" },
 172         { .clkdm_name = "dss_clkdm" },
 173         { .clkdm_name = "emif_clkdm" },
 174         { .clkdm_name = "eve1_clkdm" },
 175         { .clkdm_name = "eve2_clkdm" },
 176         { .clkdm_name = "eve3_clkdm" },
 177         { .clkdm_name = "eve4_clkdm" },
 178         { .clkdm_name = "gmac_clkdm" },
 179         { .clkdm_name = "gpu_clkdm" },
 180         { .clkdm_name = "ipu_clkdm" },
 181         { .clkdm_name = "ipu2_clkdm" },
 182         { .clkdm_name = "iva_clkdm" },
 183         { .clkdm_name = "l3init_clkdm" },
 184         { .clkdm_name = "l3main1_clkdm" },
 185         { .clkdm_name = "l4cfg_clkdm" },
 186         { .clkdm_name = "l4per_clkdm" },
 187         { .clkdm_name = "l4per2_clkdm" },
 188         { .clkdm_name = "l4per3_clkdm" },
 189         { .clkdm_name = "l4sec_clkdm" },
 190         { .clkdm_name = "pcie_clkdm" },
 191         { .clkdm_name = "vpe_clkdm" },
 192         { .clkdm_name = "wkupaon_clkdm" },
 193         { NULL },
 194 };
 195
 196 static struct clkdm_dep ipu2_wkup_sleep_deps[] = {
 197         { .clkdm_name = "atl_clkdm" },
 198         { .clkdm_name = "dsp1_clkdm" },
 199         { .clkdm_name = "dsp2_clkdm" },
 200         { .clkdm_name = "dss_clkdm" },
 201         { .clkdm_name = "emif_clkdm" },
 202         { .clkdm_name = "eve1_clkdm" },
 203         { .clkdm_name = "eve2_clkdm" },
 204         { .clkdm_name = "eve3_clkdm" },
 205         { .clkdm_name = "eve4_clkdm" },
 206         { .clkdm_name = "gmac_clkdm" },
 207         { .clkdm_name = "gpu_clkdm" },
 208         { .clkdm_name = "ipu_clkdm" },
 209         { .clkdm_name = "ipu1_clkdm" },
 210         { .clkdm_name = "iva_clkdm" },
 211         { .clkdm_name = "l3init_clkdm" },
 212         { .clkdm_name = "l3main1_clkdm" },
 213         { .clkdm_name = "l4cfg_clkdm" },
 214         { .clkdm_name = "l4per_clkdm" },
 215         { .clkdm_name = "l4per2_clkdm" },
 216         { .clkdm_name = "l4per3_clkdm" },
 217         { .clkdm_name = "l4sec_clkdm" },
 218         { .clkdm_name = "pcie_clkdm" },
 219         { .clkdm_name = "vpe_clkdm" },
 220         { .clkdm_name = "wkupaon_clkdm" },
 221         { NULL },
 222 };
 223
 224 static struct clkdm_dep iva_wkup_sleep_deps[] = {
 225         { .clkdm_name = "emif_clkdm" },
 226         { NULL },
 227 };
 228
 229 static struct clkdm_dep l3init_wkup_sleep_deps[] = {
 230         { .clkdm_name = "emif_clkdm" },
 231         { .clkdm_name = "iva_clkdm" },
 232         { .clkdm_name = "l4cfg_clkdm" },
 233         { .clkdm_name = "l4per_clkdm" },
 234         { .clkdm_name = "l4per3_clkdm" },
 235         { .clkdm_name = "l4sec_clkdm" },
 236         { .clkdm_name = "wkupaon_clkdm" },
 237         { NULL },
 238 };
 239
 240 static struct clkdm_dep l4per2_wkup_sleep_deps[] = {
 241         { .clkdm_name = "dsp1_clkdm" },
 242         { .clkdm_name = "dsp2_clkdm" },
 243         { .clkdm_name = "ipu1_clkdm" },
 244         { .clkdm_name = "ipu2_clkdm" },
 245         { NULL },
 246 };
 247
 248 static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
 249         { .clkdm_name = "emif_clkdm" },
 250         { .clkdm_name = "l4per_clkdm" },
 251         { NULL },
 252 };
 253
 254 static struct clkdm_dep mpu_wkup_sleep_deps[] = {
 255         { .clkdm_name = "cam_clkdm" },
 256         { .clkdm_name = "dsp1_clkdm" },
 257         { .clkdm_name = "dsp2_clkdm" },
 258         { .clkdm_name = "dss_clkdm" },
 259         { .clkdm_name = "emif_clkdm" },
 260         { .clkdm_name = "eve1_clkdm" },
 261         { .clkdm_name = "eve2_clkdm" },
 262         { .clkdm_name = "eve3_clkdm" },
 263         { .clkdm_name = "eve4_clkdm" },
 264         { .clkdm_name = "gmac_clkdm" },
 265         { .clkdm_name = "gpu_clkdm" },
 266         { .clkdm_name = "ipu_clkdm" },
 267         { .clkdm_name = "ipu1_clkdm" },
 268         { .clkdm_name = "ipu2_clkdm" },
 269         { .clkdm_name = "iva_clkdm" },
 270         { .clkdm_name = "l3init_clkdm" },
 271         { .clkdm_name = "l3main1_clkdm" },
 272         { .clkdm_name = "l4cfg_clkdm" },
 273         { .clkdm_name = "l4per_clkdm" },
 274         { .clkdm_name = "l4per2_clkdm" },
 275         { .clkdm_name = "l4per3_clkdm" },
 276         { .clkdm_name = "l4sec_clkdm" },
 277         { .clkdm_name = "pcie_clkdm" },
 278         { .clkdm_name = "vpe_clkdm" },
 279         { .clkdm_name = "wkupaon_clkdm" },
 280         { NULL },
 281 };
 282
 283 static struct clkdm_dep pcie_wkup_sleep_deps[] = {
 284         { .clkdm_name = "atl_clkdm" },
 285         { .clkdm_name = "cam_clkdm" },
 286         { .clkdm_name = "dsp1_clkdm" },
 287         { .clkdm_name = "dsp2_clkdm" },
 288         { .clkdm_name = "dss_clkdm" },
 289         { .clkdm_name = "emif_clkdm" },
 290         { .clkdm_name = "eve1_clkdm" },
 291         { .clkdm_name = "eve2_clkdm" },
 292         { .clkdm_name = "eve3_clkdm" },
 293         { .clkdm_name = "eve4_clkdm" },
 294         { .clkdm_name = "gmac_clkdm" },
 295         { .clkdm_name = "gpu_clkdm" },
 296         { .clkdm_name = "ipu_clkdm" },
 297         { .clkdm_name = "ipu1_clkdm" },
 298         { .clkdm_name = "iva_clkdm" },
 299         { .clkdm_name = "l3init_clkdm" },
 300         { .clkdm_name = "l4cfg_clkdm" },
 301         { .clkdm_name = "l4per_clkdm" },
 302         { .clkdm_name = "l4per2_clkdm" },
 303         { .clkdm_name = "l4per3_clkdm" },
 304         { .clkdm_name = "l4sec_clkdm" },
 305         { .clkdm_name = "vpe_clkdm" },
 306         { NULL },
 307 };
 308
 309 static struct clkdm_dep vpe_wkup_sleep_deps[] = {
 310         { .clkdm_name = "emif_clkdm" },
 311         { .clkdm_name = "l4per3_clkdm" },
 312         { NULL },
 313 };
 314
 315 static struct clockdomain l4per3_7xx_clkdm = {
 316         .name             = "l4per3_clkdm",
 317         .pwrdm            = { .name = "l4per_pwrdm" },
 318         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 319         .cm_inst          = DRA7XX_CM_CORE_L4PER_INST,
 320         .clkdm_offs       = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
 321         .dep_bit          = DRA7XX_L4PER3_STATDEP_SHIFT,
 322         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 323 };
 324
 325 static struct clockdomain l4per2_7xx_clkdm = {
 326         .name             = "l4per2_clkdm",
 327         .pwrdm            = { .name = "l4per_pwrdm" },
 328         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 329         .cm_inst          = DRA7XX_CM_CORE_L4PER_INST,
 330         .clkdm_offs       = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
 331         .dep_bit          = DRA7XX_L4PER2_STATDEP_SHIFT,
 332         .wkdep_srcs       = l4per2_wkup_sleep_deps,
 333         .sleepdep_srcs    = l4per2_wkup_sleep_deps,
 334         .flags            = CLKDM_CAN_SWSUP,
 335 };
 336
 337 static struct clockdomain mpu0_7xx_clkdm = {
 338         .name             = "mpu0_clkdm",
 339         .pwrdm            = { .name = "cpu0_pwrdm" },
 340         .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
 341         .cm_inst          = DRA7XX_MPU_PRCM_CM_C0_INST,
 342         .clkdm_offs       = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
 343         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 344 };
 345
 346 static struct clockdomain iva_7xx_clkdm = {
 347         .name             = "iva_clkdm",
 348         .pwrdm            = { .name = "iva_pwrdm" },
 349         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 350         .cm_inst          = DRA7XX_CM_CORE_IVA_INST,
 351         .clkdm_offs       = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
 352         .dep_bit          = DRA7XX_IVA_STATDEP_SHIFT,
 353         .wkdep_srcs       = iva_wkup_sleep_deps,
 354         .sleepdep_srcs    = iva_wkup_sleep_deps,
 355         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 356 };
 357
 358 static struct clockdomain coreaon_7xx_clkdm = {
 359         .name             = "coreaon_clkdm",
 360         .pwrdm            = { .name = "coreaon_pwrdm" },
 361         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 362         .cm_inst          = DRA7XX_CM_CORE_COREAON_INST,
 363         .clkdm_offs       = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
 364         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 365 };
 366
 367 static struct clockdomain ipu1_7xx_clkdm = {
 368         .name             = "ipu1_clkdm",
 369         .pwrdm            = { .name = "ipu_pwrdm" },
 370         .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
 371         .cm_inst          = DRA7XX_CM_CORE_AON_IPU_INST,
 372         .clkdm_offs       = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
 373         .dep_bit          = DRA7XX_IPU1_STATDEP_SHIFT,
 374         .wkdep_srcs       = ipu1_wkup_sleep_deps,
 375         .sleepdep_srcs    = ipu1_wkup_sleep_deps,
 376         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 377 };
 378
 379 static struct clockdomain ipu2_7xx_clkdm = {
 380         .name             = "ipu2_clkdm",
 381         .pwrdm            = { .name = "core_pwrdm" },
 382         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 383         .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
 384         .clkdm_offs       = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
 385         .dep_bit          = DRA7XX_IPU2_STATDEP_SHIFT,
 386         .wkdep_srcs       = ipu2_wkup_sleep_deps,
 387         .sleepdep_srcs    = ipu2_wkup_sleep_deps,
 388         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 389 };
 390
 391 static struct clockdomain l3init_7xx_clkdm = {
 392         .name             = "l3init_clkdm",
 393         .pwrdm            = { .name = "l3init_pwrdm" },
 394         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 395         .cm_inst          = DRA7XX_CM_CORE_L3INIT_INST,
 396         .clkdm_offs       = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
 397         .dep_bit          = DRA7XX_L3INIT_STATDEP_SHIFT,
 398         .wkdep_srcs       = l3init_wkup_sleep_deps,
 399         .sleepdep_srcs    = l3init_wkup_sleep_deps,
 400         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 401 };
 402
 403 static struct clockdomain l4sec_7xx_clkdm = {
 404         .name             = "l4sec_clkdm",
 405         .pwrdm            = { .name = "l4per_pwrdm" },
 406         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 407         .cm_inst          = DRA7XX_CM_CORE_L4PER_INST,
 408         .clkdm_offs       = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
 409         .dep_bit          = DRA7XX_L4SEC_STATDEP_SHIFT,
 410         .wkdep_srcs       = l4sec_wkup_sleep_deps,
 411         .sleepdep_srcs    = l4sec_wkup_sleep_deps,
 412         .flags            = CLKDM_CAN_SWSUP,
 413 };
 414
 415 static struct clockdomain l3main1_7xx_clkdm = {
 416         .name             = "l3main1_clkdm",
 417         .pwrdm            = { .name = "core_pwrdm" },
 418         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 419         .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
 420         .clkdm_offs       = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
 421         .dep_bit          = DRA7XX_L3MAIN1_STATDEP_SHIFT,
 422         .flags            = CLKDM_CAN_HWSUP,
 423 };
 424
 425 static struct clockdomain vpe_7xx_clkdm = {
 426         .name             = "vpe_clkdm",
 427         .pwrdm            = { .name = "vpe_pwrdm" },
 428         .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
 429         .cm_inst          = DRA7XX_CM_CORE_AON_VPE_INST,
 430         .clkdm_offs       = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
 431         .dep_bit          = DRA7XX_VPE_STATDEP_SHIFT,
 432         .wkdep_srcs       = vpe_wkup_sleep_deps,
 433         .sleepdep_srcs    = vpe_wkup_sleep_deps,
 434         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 435 };
 436
 437 static struct clockdomain mpu_7xx_clkdm = {
 438         .name             = "mpu_clkdm",
 439         .pwrdm            = { .name = "mpu_pwrdm" },
 440         .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
 441         .cm_inst          = DRA7XX_CM_CORE_AON_MPU_INST,
 442         .clkdm_offs       = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
 443         .wkdep_srcs       = mpu_wkup_sleep_deps,
 444         .sleepdep_srcs    = mpu_wkup_sleep_deps,
 445         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 446 };
 447
 448 static struct clockdomain custefuse_7xx_clkdm = {
 449         .name             = "custefuse_clkdm",
 450         .pwrdm            = { .name = "custefuse_pwrdm" },
 451         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 452         .cm_inst          = DRA7XX_CM_CORE_CUSTEFUSE_INST,
 453         .clkdm_offs       = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
 454         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 455 };
 456
 457 static struct clockdomain ipu_7xx_clkdm = {
 458         .name             = "ipu_clkdm",
 459         .pwrdm            = { .name = "ipu_pwrdm" },
 460         .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
 461         .cm_inst          = DRA7XX_CM_CORE_AON_IPU_INST,
 462         .clkdm_offs       = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
 463         .dep_bit          = DRA7XX_IPU_STATDEP_SHIFT,
 464         .flags            = CLKDM_CAN_SWSUP,
 465 };
 466
 467 static struct clockdomain mpu1_7xx_clkdm = {
 468         .name             = "mpu1_clkdm",
 469         .pwrdm            = { .name = "cpu1_pwrdm" },
 470         .prcm_partition   = DRA7XX_MPU_PRCM_PARTITION,
 471         .cm_inst          = DRA7XX_MPU_PRCM_CM_C1_INST,
 472         .clkdm_offs       = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
 473         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 474 };
 475
 476 static struct clockdomain gmac_7xx_clkdm = {
 477         .name             = "gmac_clkdm",
 478         .pwrdm            = { .name = "l3init_pwrdm" },
 479         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 480         .cm_inst          = DRA7XX_CM_CORE_L3INIT_INST,
 481         .clkdm_offs       = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
 482         .dep_bit          = DRA7XX_GMAC_STATDEP_SHIFT,
 483         .wkdep_srcs       = gmac_wkup_sleep_deps,
 484         .sleepdep_srcs    = gmac_wkup_sleep_deps,
 485         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 486 };
 487
 488 static struct clockdomain l4cfg_7xx_clkdm = {
 489         .name             = "l4cfg_clkdm",
 490         .pwrdm            = { .name = "core_pwrdm" },
 491         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 492         .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
 493         .clkdm_offs       = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
 494         .dep_bit          = DRA7XX_L4CFG_STATDEP_SHIFT,
 495         .flags            = CLKDM_CAN_HWSUP,
 496 };
 497
 498 static struct clockdomain dma_7xx_clkdm = {
 499         .name             = "dma_clkdm",
 500         .pwrdm            = { .name = "core_pwrdm" },
 501         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 502         .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
 503         .clkdm_offs       = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
 504         .wkdep_srcs       = dma_wkup_sleep_deps,
 505         .sleepdep_srcs    = dma_wkup_sleep_deps,
 506         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 507 };
 508
 509 static struct clockdomain rtc_7xx_clkdm = {
 510         .name             = "rtc_clkdm",
 511         .pwrdm            = { .name = "rtc_pwrdm" },
 512         .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
 513         .cm_inst          = DRA7XX_CM_CORE_AON_RTC_INST,
 514         .clkdm_offs       = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
 515         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 516 };
 517
 518 static struct clockdomain pcie_7xx_clkdm = {
 519         .name             = "pcie_clkdm",
 520         .pwrdm            = { .name = "l3init_pwrdm" },
 521         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 522         .cm_inst          = DRA7XX_CM_CORE_L3INIT_INST,
 523         .clkdm_offs       = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
 524         .dep_bit          = DRA7XX_PCIE_STATDEP_SHIFT,
 525         .wkdep_srcs       = pcie_wkup_sleep_deps,
 526         .sleepdep_srcs    = pcie_wkup_sleep_deps,
 527         .flags            = CLKDM_CAN_SWSUP,
 528 };
 529
 530 static struct clockdomain atl_7xx_clkdm = {
 531         .name             = "atl_clkdm",
 532         .pwrdm            = { .name = "core_pwrdm" },
 533         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 534         .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
 535         .clkdm_offs       = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
 536         .dep_bit          = DRA7XX_ATL_STATDEP_SHIFT,
 537         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 538 };
 539
 540 static struct clockdomain l3instr_7xx_clkdm = {
 541         .name             = "l3instr_clkdm",
 542         .pwrdm            = { .name = "core_pwrdm" },
 543         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 544         .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
 545         .clkdm_offs       = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
 546 };
 547
 548 static struct clockdomain dss_7xx_clkdm = {
 549         .name             = "dss_clkdm",
 550         .pwrdm            = { .name = "dss_pwrdm" },
 551         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 552         .cm_inst          = DRA7XX_CM_CORE_DSS_INST,
 553         .clkdm_offs       = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
 554         .dep_bit          = DRA7XX_DSS_STATDEP_SHIFT,
 555         .wkdep_srcs       = dss_wkup_sleep_deps,
 556         .sleepdep_srcs    = dss_wkup_sleep_deps,
 557         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 558 };
 559
 560 static struct clockdomain emif_7xx_clkdm = {
 561         .name             = "emif_clkdm",
 562         .pwrdm            = { .name = "core_pwrdm" },
 563         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 564         .cm_inst          = DRA7XX_CM_CORE_CORE_INST,
 565         .clkdm_offs       = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
 566         .dep_bit          = DRA7XX_EMIF_STATDEP_SHIFT,
 567         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 568 };
 569
 570 static struct clockdomain emu_7xx_clkdm = {
 571         .name             = "emu_clkdm",
 572         .pwrdm            = { .name = "emu_pwrdm" },
 573         .prcm_partition   = DRA7XX_PRM_PARTITION,
 574         .cm_inst          = DRA7XX_PRM_EMU_CM_INST,
 575         .clkdm_offs       = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
 576         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 577 };
 578
 579 static struct clockdomain dsp2_7xx_clkdm = {
 580         .name             = "dsp2_clkdm",
 581         .pwrdm            = { .name = "dsp2_pwrdm" },
 582         .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
 583         .cm_inst          = DRA7XX_CM_CORE_AON_DSP2_INST,
 584         .clkdm_offs       = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
 585         .dep_bit          = DRA7XX_DSP2_STATDEP_SHIFT,
 586         .wkdep_srcs       = dsp2_wkup_sleep_deps,
 587         .sleepdep_srcs    = dsp2_wkup_sleep_deps,
 588         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 589 };
 590
 591 static struct clockdomain dsp1_7xx_clkdm = {
 592         .name             = "dsp1_clkdm",
 593         .pwrdm            = { .name = "dsp1_pwrdm" },
 594         .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
 595         .cm_inst          = DRA7XX_CM_CORE_AON_DSP1_INST,
 596         .clkdm_offs       = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
 597         .dep_bit          = DRA7XX_DSP1_STATDEP_SHIFT,
 598         .wkdep_srcs       = dsp1_wkup_sleep_deps,
 599         .sleepdep_srcs    = dsp1_wkup_sleep_deps,
 600         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 601 };
 602
 603 static struct clockdomain cam_7xx_clkdm = {
 604         .name             = "cam_clkdm",
 605         .pwrdm            = { .name = "cam_pwrdm" },
 606         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 607         .cm_inst          = DRA7XX_CM_CORE_CAM_INST,
 608         .clkdm_offs       = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
 609         .dep_bit          = DRA7XX_CAM_STATDEP_SHIFT,
 610         .wkdep_srcs       = cam_wkup_sleep_deps,
 611         .sleepdep_srcs    = cam_wkup_sleep_deps,
 612         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 613 };
 614
 615 static struct clockdomain l4per_7xx_clkdm = {
 616         .name             = "l4per_clkdm",
 617         .pwrdm            = { .name = "l4per_pwrdm" },
 618         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 619         .cm_inst          = DRA7XX_CM_CORE_L4PER_INST,
 620         .clkdm_offs       = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
 621         .dep_bit          = DRA7XX_L4PER_STATDEP_SHIFT,
 622         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 623 };
 624
 625 static struct clockdomain gpu_7xx_clkdm = {
 626         .name             = "gpu_clkdm",
 627         .pwrdm            = { .name = "gpu_pwrdm" },
 628         .prcm_partition   = DRA7XX_CM_CORE_PARTITION,
 629         .cm_inst          = DRA7XX_CM_CORE_GPU_INST,
 630         .clkdm_offs       = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
 631         .dep_bit          = DRA7XX_GPU_STATDEP_SHIFT,
 632         .wkdep_srcs       = gpu_wkup_sleep_deps,
 633         .sleepdep_srcs    = gpu_wkup_sleep_deps,
 634         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 635 };
 636
 637 static struct clockdomain eve4_7xx_clkdm = {
 638         .name             = "eve4_clkdm",
 639         .pwrdm            = { .name = "eve4_pwrdm" },
 640         .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
 641         .cm_inst          = DRA7XX_CM_CORE_AON_EVE4_INST,
 642         .clkdm_offs       = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
 643         .dep_bit          = DRA7XX_EVE4_STATDEP_SHIFT,
 644         .wkdep_srcs       = eve4_wkup_sleep_deps,
 645         .sleepdep_srcs    = eve4_wkup_sleep_deps,
 646         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 647 };
 648
 649 static struct clockdomain eve2_7xx_clkdm = {
 650         .name             = "eve2_clkdm",
 651         .pwrdm            = { .name = "eve2_pwrdm" },
 652         .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
 653         .cm_inst          = DRA7XX_CM_CORE_AON_EVE2_INST,
 654         .clkdm_offs       = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
 655         .dep_bit          = DRA7XX_EVE2_STATDEP_SHIFT,
 656         .wkdep_srcs       = eve2_wkup_sleep_deps,
 657         .sleepdep_srcs    = eve2_wkup_sleep_deps,
 658         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 659 };
 660
 661 static struct clockdomain eve3_7xx_clkdm = {
 662         .name             = "eve3_clkdm",
 663         .pwrdm            = { .name = "eve3_pwrdm" },
 664         .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
 665         .cm_inst          = DRA7XX_CM_CORE_AON_EVE3_INST,
 666         .clkdm_offs       = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
 667         .dep_bit          = DRA7XX_EVE3_STATDEP_SHIFT,
 668         .wkdep_srcs       = eve3_wkup_sleep_deps,
 669         .sleepdep_srcs    = eve3_wkup_sleep_deps,
 670         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 671 };
 672
 673 static struct clockdomain wkupaon_7xx_clkdm = {
 674         .name             = "wkupaon_clkdm",
 675         .pwrdm            = { .name = "wkupaon_pwrdm" },
 676         .prcm_partition   = DRA7XX_PRM_PARTITION,
 677         .cm_inst          = DRA7XX_PRM_WKUPAON_CM_INST,
 678         .clkdm_offs       = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
 679         .dep_bit          = DRA7XX_WKUPAON_STATDEP_SHIFT,
 680         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 681 };
 682
 683 static struct clockdomain eve1_7xx_clkdm = {
 684         .name             = "eve1_clkdm",
 685         .pwrdm            = { .name = "eve1_pwrdm" },
 686         .prcm_partition   = DRA7XX_CM_CORE_AON_PARTITION,
 687         .cm_inst          = DRA7XX_CM_CORE_AON_EVE1_INST,
 688         .clkdm_offs       = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,
 689         .dep_bit          = DRA7XX_EVE1_STATDEP_SHIFT,
 690         .wkdep_srcs       = eve1_wkup_sleep_deps,
 691         .sleepdep_srcs    = eve1_wkup_sleep_deps,
 692         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 693 };
 694
 695 /* As clockdomains are added or removed above, this list must also be changed */
 696 static struct clockdomain *clockdomains_dra7xx[] __initdata = {
 697         &l4per3_7xx_clkdm,
 698         &l4per2_7xx_clkdm,
 699         &mpu0_7xx_clkdm,
 700         &iva_7xx_clkdm,
 701         &coreaon_7xx_clkdm,
 702         &ipu1_7xx_clkdm,
 703         &ipu2_7xx_clkdm,
 704         &l3init_7xx_clkdm,
 705         &l4sec_7xx_clkdm,
 706         &l3main1_7xx_clkdm,
 707         &vpe_7xx_clkdm,
 708         &mpu_7xx_clkdm,
 709         &custefuse_7xx_clkdm,
 710         &ipu_7xx_clkdm,
 711         &mpu1_7xx_clkdm,
 712         &gmac_7xx_clkdm,
 713         &l4cfg_7xx_clkdm,
 714         &dma_7xx_clkdm,
 715         &rtc_7xx_clkdm,
 716         &pcie_7xx_clkdm,
 717         &atl_7xx_clkdm,
 718         &l3instr_7xx_clkdm,
 719         &dss_7xx_clkdm,
 720         &emif_7xx_clkdm,
 721         &emu_7xx_clkdm,
 722         &dsp2_7xx_clkdm,
 723         &dsp1_7xx_clkdm,
 724         &cam_7xx_clkdm,
 725         &l4per_7xx_clkdm,
 726         &gpu_7xx_clkdm,
 727         &eve4_7xx_clkdm,
 728         &eve2_7xx_clkdm,
 729         &eve3_7xx_clkdm,
 730         &wkupaon_7xx_clkdm,
 731         &eve1_7xx_clkdm,
 732         NULL
 733 };
 734
 735 void __init dra7xx_clockdomains_init(void)
 736 {
 737         clkdm_register_platform_funcs(&omap4_clkdm_operations);
 738         clkdm_register_clkdms(clockdomains_dra7xx);
 739         clkdm_complete_init();
 740 }